DDR3 SDRAM数据手册.pdf

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DDR3 SDRAM

Features

FBGA Part Marking Decoder

State Diagram

Functional Description

Industrial Temperature

General Notes

Functional Block Diagrams

Ball Assignments and Descriptions

Package Dimensions

Electrical Specifications

Absolute Ratings

Input/Output Capacitance

Thermal Characteristics

Electrical Specifications – IDD Specifications and Conditions

Electrical Characteristics – IDD Specifications

Electrical Specifications – DC and AC

DC Operating Conditions

Input Operating Conditions

AC Overshoot/Undershoot Specification

Slew Rate Definitions for Single-Ended Input Signals

Slew Rate Definitions for Differential Input Signals

ODT Characteristics

ODT Resistors

ODT Sensitivity

ODT Timing Definitions

Output Driver Impedance

34 Ohm Output Driver Impedance

34 Ohm Driver

34 Ohm Output Driver Sensitivity

Alternative 40 Ohm Driver

40 Ohm Output Driver Sensitivity

Output Characteristics and Operating Conditions

Reference Output Load

Slew Rate Definitions for Single-Ended Output Signals

Slew Rate Definitions for Differential Output Signals

Speed Bin Tables

Electrical Characteristics and AC Operating Conditions

Command and Address Setup, Hold, and Derating

Data Setup, Hold, and Derating

Commands – Truth Tables

Commands

DESELECT

NO OPERATION

ZQ CALIBRATION LONG

ZQ CALIBRATION SHORT

ACTIVATE

READ

WRITE

PRECHARGE

REFRESH

SELF REFRESH

DLL Disable Mode

Input Clock Frequency Change

Write Leveling

Write Leveling Procedure

Write Leveling Mode Exit Procedure

Initialization

Mode Registers

Mode Register 0 (MR0)

Burst Length

Burst Type

DLL RESET

Write Recovery

Precharge Power-Down (Precharge PD)

CAS Latency (CL)

Mode Register 1 (MR1)

DLL Enable/DLL Disable

Output Drive Strength

OUTPUT ENABLE/DISABLE

TDQS Enable

On-Die Termination

WRITE LEVELING

POSTED CAS ADDITIVE Latency

Mode Register 2 (MR2)

CAS Write Latency (CWL)

AUTO SELF REFRESH (ASR)

SELF REFRESH TEMPERATURE (SRT)

SRT vs. ASR

DYNAMIC ODT

Mode Register 3 (MR3)

MULTIPURPOSE REGISTER (MPR)

MPR Functional Description

MPR Register Address Definitions and Bursting Order

MPR Read Predefined Pattern

MODE REGISTER SET (MRS) Command

ZQ CALIBRATION Operation

ACTIVATE Operation

READ Operation

WRITE Operation

DQ Input Timing

PRECHARGE Operation

SELF REFRESH Operation

Extended Temperature Usage

Power-Down Mode

RESET Operation

On-Die Termination (ODT)

Functional Representation of ODT

Nominal ODT

Dynamic ODT

Dynamic ODT Special Use Case

Functional Description

Synchronous ODT Mode

ODT Latency and Posted ODT

Timing Parameters

ODT Off During READs

Asynchronous ODT Mode

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)

4Gb: x4, x8, x16 DDR3 SDRAM Features DDR3 SDRAM MT41J1G4 – 128 Meg x 4 x 8 banks MT41J512M8 – 64 Meg x 8 x 8 banks MT41J256M16 – 32 Meg x 16 x 8 banks Features • VDD = VDDQ = 1.5V ±0.075V • 1.5V center-terminated push/pull I/O • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS READ latency (CL) • Posted CAS additive latency (AL) • Programmable CAS WRITE latency (CWL) based on tCK • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • TC of 0°C to 95°C – 64ms, 8192 cycle refresh at 0°C to 85°C – 32ms, 8192 cycle refresh at 85°C to 95°C • Self refresh temperature (SRT) • Automatic self refresh temperature (ASR) • Write leveling • Multipurpose register • Output driver calibration Table 1: Key Timing Parameters Options1 • Configuration – 1 Gig x 4 – 512 Meg x 8 – 256 Meg x 16 • FBGA package (Pb-free) – x4, x8 – 78-ball (9mm x 10.5mm) Rev. E • FBGA package (Pb-free) – x16 – 96-ball (9mm x 14mm) Rev. E • Timing – cycle time – 938ps @ CL = 14 (DDR3-2133) – 1.07ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) • Operating temperature – Commercial (0°C ≤ TC ≤ +95°C) – Industrial (–40°C ≤ TC ≤ +95°C) • Revision Marking 1G4 512M8 256M16 RH HA -093 -107 -125 -15E -187E None IT :E Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) -0931, 2, 3, 4 -1071, 2, 3 -1251, 2, -15E1, -187E 2133 1866 1600 1333 1066 14-14-14 13-13-13 11-11-11 9-9-9 7-7-7 13.13 13.91 13.75 13.5 13.1 13.13 13.91 13.75 13.5 13.1 CL (ns) 13.13 13.91 13.75 13.5 13.1 Notes: 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL = 11 (-125). 4. Backward compatible to 1866, CL = 13 (-107). PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN Products and specifications discussed herein are subject to change by Micron without notice. 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features Table 2: Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Page size 1 Gig x 4 512 Meg x 8 256 Meg x 16 128 Meg x 4 x 8 banks 64 Meg x 8 x 8 banks 32 Meg x 16 x 8 banks 8K 64K (A[15:0]) 8 (BA[2:0]) 2K (A[11, 9:0]) 1KB 8K 64K (A[15:0]) 8 (BA[2:0]) 1K (A[9:0]) 1KB 8K 32K (A[14:0]) 8 (BA[2:0]) 1K (A[9:0]) 2KB Figure 1: DDR3 Part Numbers Example Part Number: MT41J512M8RH-125:E MT41J Configuration Package Speed Revision - : Configuration 1 Gig x 4 512 Meg x 8 256 Meg x 16 1G4 512M8 256M16 Package 78-ball 9mm x 10.5mm FBGA 96-ball 9mm x 14mm FBGA Rev. Mark E E RH HA { :E Revision Temperatu re Commercial Industrial temperature None IT Speed Grade tCK = 0.938ns, CL = 14 tCK = 1.071ns, CL = 13 tCK = 1.25ns, CL = 11 tCK = 1.5ns, CL = 9 tCK = 1.87ns, CL = E -093 -107 -125 -15E -187E Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Industrial Temperature ............................................................................................................................... 12 General Notes ............................................................................................................................................ 12 Functional Block Diagrams ............................................................................................................................. 14 Ball Assignments and Descriptions ................................................................................................................. 16 Package Dimensions ....................................................................................................................................... 22 Electrical Specifications .................................................................................................................................. 26 Absolute Ratings ......................................................................................................................................... 26 Input/Output Capacitance .......................................................................................................................... 27 Thermal Characteristics .................................................................................................................................. 28 Electrical Specifications – IDD Specifications and Conditions ............................................................................ 29 Electrical Characteristics – IDD Specifications .................................................................................................. 40 Electrical Specifications – DC and AC .............................................................................................................. 44 DC Operating Conditions ........................................................................................................................... 44 Input Operating Conditions ........................................................................................................................ 44 AC Overshoot/Undershoot Specification ..................................................................................................... 48 Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 51 Slew Rate Definitions for Differential Input Signals ...................................................................................... 53 ODT Characteristics ....................................................................................................................................... 54 ODT Resistors ............................................................................................................................................ 55 ODT Sensitivity .......................................................................................................................................... 56 ODT Timing Definitions ............................................................................................................................. 56 Output Driver Impedance ............................................................................................................................... 60 34 Ohm Output Driver Impedance .............................................................................................................. 61 34 Ohm Driver ............................................................................................................................................ 62 34 Ohm Output Driver Sensitivity ................................................................................................................ 63 Alternative 40 Ohm Driver .......................................................................................................................... 64 40 Ohm Output Driver Sensitivity ................................................................................................................ 64 Output Characteristics and Operating Conditions ............................................................................................ 66 Reference Output Load ............................................................................................................................... 68 Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 69 Slew Rate Definitions for Differential Output Signals .................................................................................... 70 Speed Bin Tables ............................................................................................................................................ 71 Electrical Characteristics and AC Operating Conditions ................................................................................... 76 Command and Address Setup, Hold, and Derating ........................................................................................... 96 Data Setup, Hold, and Derating ...................................................................................................................... 104 Commands – Truth Tables ............................................................................................................................. 113 Commands ................................................................................................................................................... 116 DESELECT ................................................................................................................................................ 116 NO OPERATION ........................................................................................................................................ 116 ZQ CALIBRATION LONG ........................................................................................................................... 116 ZQ CALIBRATION SHORT .......................................................................................................................... 116 ACTIVATE ................................................................................................................................................. 116 READ ........................................................................................................................................................ 116 WRITE ...................................................................................................................................................... 117 PRECHARGE ............................................................................................................................................. 118 REFRESH .................................................................................................................................................. 118 SELF REFRESH .......................................................................................................................................... 119 DLL Disable Mode ..................................................................................................................................... 120 PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features Input Clock Frequency Change ...................................................................................................................... 124 Write Leveling ............................................................................................................................................... 126 Write Leveling Procedure ........................................................................................................................... 128 Write Leveling Mode Exit Procedure ........................................................................................................... 130 Initialization ................................................................................................................................................. 131 Mode Registers .............................................................................................................................................. 133 Mode Register 0 (MR0) ................................................................................................................................... 134 Burst Length ............................................................................................................................................. 134 Burst Type ................................................................................................................................................. 135 DLL RESET ................................................................................................................................................ 136 Write Recovery .......................................................................................................................................... 136 Precharge Power-Down (Precharge PD) ...................................................................................................... 137 CAS Latency (CL) ....................................................................................................................................... 137 Mode Register 1 (MR1) ................................................................................................................................... 138 DLL Enable/DLL Disable ........................................................................................................................... 138 Output Drive Strength ............................................................................................................................... 139 OUTPUT ENABLE/DISABLE ...................................................................................................................... 139 TDQS Enable ............................................................................................................................................. 139 On-Die Termination .................................................................................................................................. 140 WRITE LEVELING ..................................................................................................................................... 140 POSTED CAS ADDITIVE Latency ................................................................................................................ 140 Mode Register 2 (MR2) ................................................................................................................................... 141 CAS Write Latency (CWL) ........................................................................................................................... 142 AUTO SELF REFRESH (ASR) ....................................................................................................................... 142 SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 143 SRT vs. ASR ............................................................................................................................................... 143 DYNAMIC ODT ......................................................................................................................................... 143 Mode Register 3 (MR3) ................................................................................................................................... 144 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144 MPR Functional Description ...................................................................................................................... 145 MPR Register Address Definitions and Bursting Order ................................................................................. 146 MPR Read Predefined Pattern .................................................................................................................... 152 MODE REGISTER SET (MRS) Command ........................................................................................................ 152 ZQ CALIBRATION Operation ......................................................................................................................... 153 ACTIVATE Operation ..................................................................................................................................... 154 READ Operation ............................................................................................................................................ 156 WRITE Operation .......................................................................................................................................... 167 DQ Input Timing ....................................................................................................................................... 175 PRECHARGE Operation ................................................................................................................................. 177 SELF REFRESH Operation .............................................................................................................................. 177 Extended Temperature Usage ........................................................................................................................ 179 Power-Down Mode ........................................................................................................................................ 180 RESET Operation ........................................................................................................................................... 188 On-Die Termination (ODT) ............................................................................................................................ 190 Functional Representation of ODT ............................................................................................................. 190 Nominal ODT ............................................................................................................................................ 190 Dynamic ODT ............................................................................................................................................... 192 Dynamic ODT Special Use Case ................................................................................................................. 192 Functional Description .............................................................................................................................. 192 Synchronous ODT Mode ................................................................................................................................ 198 ODT Latency and Posted ODT .................................................................................................................... 198 Timing Parameters .................................................................................................................................... 198 PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features ODT Off During READs .............................................................................................................................. 201 Asynchronous ODT Mode .............................................................................................................................. 203 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 205 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 207 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 209 PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features List of Figures Figure 1: DDR3 Part Numbers .......................................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................. 11 Figure 3: 1 Gig x 4 Functional Block Diagram .................................................................................................. 14 Figure 4: 512 Meg x 8 Functional Block Diagram ............................................................................................. 15 Figure 5: 256 Meg x 16 Functional Block Diagram ........................................................................................... 15 Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16 Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17 Figure 8: 78-Ball FBGA – x4, x8 (RA) ................................................................................................................ 22 Figure 9: 78-Ball FBGA – x4, x8 (RH) ............................................................................................................... 23 Figure 10: 96-Ball FBGA – x16 (RE) ................................................................................................................. 24 Figure 11: 96-Ball FBGA – x16 (HA) ................................................................................................................. 25 Figure 12: Thermal Measurement Point ......................................................................................................... 28 Figure 13: Input Signal .................................................................................................................................. 47 Figure 14: Overshoot ..................................................................................................................................... 48 Figure 15: Undershoot ................................................................................................................................... 48 Figure 16: VIX for Differential Signals .............................................................................................................. 49 Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 49 Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 50 Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 52 Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 53 Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 54 Figure 22: ODT Timing Reference Load .......................................................................................................... 57 Figure 23: tAON and tAOF Definitions ............................................................................................................ 58 Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 58 Figure 25: tADC Definition ............................................................................................................................. 59 Figure 26: Output Driver ................................................................................................................................ 60 Figure 27: DQ Output Signal .......................................................................................................................... 67 Figure 28: Differential Output Signal .............................................................................................................. 68 Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 68 Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 69 Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 70 Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 100 Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 101 Figure 34: Tangent Line for tIS (Command and Address – Clock) .................................................................... 102 Figure 35: Tangent Line for tIH (Command and Address – Clock) .................................................................... 103 Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 109 Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 110 Figure 38: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 111 Figure 39: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 112 Figure 40: Refresh Mode ............................................................................................................................... 119 Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 121 Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 122 Figure 43: DLL Disable tDQSCK .................................................................................................................... 123 Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 125 Figure 45: Write Leveling Concept ................................................................................................................. 126 Figure 46: Write Leveling Sequence ............................................................................................................... 129 Figure 47: Write Leveling Exit Procedure ....................................................................................................... 130 Figure 48: Initialization Sequence ................................................................................................................. 132 Figure 49: MRS to MRS Command Timing (tMRD) ......................................................................................... 133 Figure 50: MRS to nonMRS Command Timing (tMOD) .................................................................................. 134 PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features Figure 51: Mode Register 0 (MR0) Definitions ................................................................................................ 135 Figure 52: READ Latency .............................................................................................................................. 137 Figure 53: Mode Register 1 (MR1) Definition ................................................................................................. 138 Figure 54: READ Latency (AL = 5, CL = 6) ....................................................................................................... 141 Figure 55: Mode Register 2 (MR2) Definition ................................................................................................. 142 Figure 56: CAS Write Latency ........................................................................................................................ 142 Figure 57: Mode Register 3 (MR3) Definition ................................................................................................. 144 Figure 58: Multipurpose Register (MPR) Block Diagram ................................................................................. 145 Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 148 Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 149 Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 150 Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 151 Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 153 Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 154 Figure 65: Example: tFAW ............................................................................................................................. 155 Figure 66: READ Latency .............................................................................................................................. 156 Figure 67: Consecutive READ Bursts (BL8) .................................................................................................... 158 Figure 68: Consecutive READ Bursts (BC4) .................................................................................................... 158 Figure 69: Nonconsecutive READ Bursts ....................................................................................................... 159 Figure 70: READ (BL8) to WRITE (BL8) .......................................................................................................... 159 Figure 71: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 160 Figure 72: READ to PRECHARGE (BL8) .......................................................................................................... 160 Figure 73: READ to PRECHARGE (BC4) ......................................................................................................... 161 Figure 74: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 161 Figure 75: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 161 Figure 76: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 163 Figure 77: Data Strobe Timing – READs ......................................................................................................... 164 Figure 78: Method for Calculating tLZ and tHZ ............................................................................................... 165 Figure 79: tRPRE Timing ............................................................................................................................... 165 Figure 80: tRPST Timing ............................................................................................................................... 166 Figure 81: tWPRE Timing .............................................................................................................................. 168 Figure 82: tWPST Timing .............................................................................................................................. 168 Figure 83: WRITE Burst ................................................................................................................................ 169 Figure 84: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 170 Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 170 Figure 86: Nonconsecutive WRITE to WRITE ................................................................................................. 171 Figure 87: WRITE (BL8) to READ (BL8) .......................................................................................................... 171 Figure 88: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 172 Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 173 Figure 90: WRITE (BL8) to PRECHARGE ........................................................................................................ 174 Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 174 Figure 92: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 175 Figure 93: Data Input Timing ........................................................................................................................ 176 Figure 94: Self Refresh Entry/Exit Timing ...................................................................................................... 178 Figure 95: Active Power-Down Entry and Exit ................................................................................................ 182 Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 182 Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 183 Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 183 Figure 99: Power-Down Entry After WRITE .................................................................................................... 184 Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 184 Figure 101: REFRESH to Power-Down Entry .................................................................................................. 185 Figure 102: ACTIVATE to Power-Down Entry ................................................................................................. 185 PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

4Gb: x4, x8, x16 DDR3 SDRAM Features Figure 103: PRECHARGE to Power-Down Entry ............................................................................................. 186 Figure 104: MRS Command to Power-Down Entry ......................................................................................... 186 Figure 105: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 187 Figure 106: RESET Sequence ......................................................................................................................... 189 Figure 107: On-Die Termination ................................................................................................................... 190 Figure 108: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 195 Figure 109: Dynamic ODT: Without WRITE Command .................................................................................. 195 Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 196 Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 197 Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 197 Figure 113: Synchronous ODT ...................................................................................................................... 199 Figure 114: Synchronous ODT (BC4) ............................................................................................................. 200 Figure 115: ODT During READs .................................................................................................................... 202 Figure 116: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 204 Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 206 Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 208 Figure 119: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 210 Figure 120: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 210 PDF: 09005aef8417277b 4Gb_DDR3_SDRAM.pdf - Rev. N 12/14 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.

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