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MT29F16G08ABABA_nandflash.pdf
NAND Flash Memory
Features
Part Numbering Information
Important Notes and Warnings
General Description
Asynchronous and Synchronous Signal Descriptions
Signal Assignments
Package Dimensions
Architecture
Device and Array Organization
Bus Operation – Asynchronous Interface
Asynchronous Enable/Standby
Asynchronous Bus Idle
Asynchronous Pausing Data Input/Output
Asynchronous Commands
Asynchronous Addresses
Asynchronous Data Input
Asynchronous Data Output
Write Protect
Ready/Busy#
Bus Operation – Synchronous Interface
Synchronous Enable/Standby
Synchronous Bus Idle/Driving
Synchronous Pausing Data Input/Output
Synchronous Commands
Synchronous Addresses
Synchronous DDR Data Input
Synchronous DDR Data Output
Write Protect
Ready/Busy#
Device Initialization
Activating Interfaces
Activating the Asynchronous Interface
Activating the Synchronous Interface
Command Definitions
Reset Operations
RESET (FFh)
SYNCHRONOUS RESET (FCh)
Identification Operations
READ ID (90h)
READ ID Parameter Tables
Configuration Operations
SET FEATURES (EFh)
GET FEATURES (EEh)
READ PARAMETER PAGE (ECh)
Parameter Page Data Structure Tables
READ UNIQUE ID (EDh)
Status Operations
READ STATUS (70h)
READ STATUS ENHANCED (78h)
Column Address Operations
CHANGE READ COLUMN (05h-E0h)
CHANGE READ COLUMN ENHANCED (06h-E0h)
CHANGE WRITE COLUMN (85h)
CHANGE ROW ADDRESS (85h)
Read Operations
READ MODE (00h)
READ PAGE (00h-30h)
READ PAGE CACHE SEQUENTIAL (31h)
READ PAGE CACHE RANDOM (00h-31h)
READ PAGE CACHE LAST (3Fh)
READ PAGE MULTI-PLANE (00h-32h)
Program Operations
PROGRAM PAGE (80h-10h)
PROGRAM PAGE CACHE (80h-15h)
PROGRAM PAGE MULTI-PLANE (80h-11h)
Erase Operations
ERASE BLOCK (60h-D0h)
ERASE BLOCK MULTI-PLANE (60h-D1h)
Copyback Operations
COPYBACK READ (00h-35h)
COPYBACK PROGRAM (85h–10h)
COPYBACK READ MULTI-PLANE (00h-32h)
COPYBACK PROGRAM MULTI-PLANE (85h-11h)
One-Time Programmable (OTP) Operations
PROGRAM OTP PAGE (80h-10h)
PROTECT OTP AREA (80h-10h)
READ OTP PAGE (00h-30h)
Multi-Plane Operations
Multi-Plane Addressing
Interleaved Die (Multi-LUN) Operations
Error Management
Output Drive Impedance
AC Overshoot/Undershoot Specifications
Synchronous Input Slew Rate
Output Slew Rate
Electrical Specifications
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous)
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous)
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ)
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous)
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous)
Electrical Specifications – Array Characteristics
Asynchronous Interface Timing Diagrams
Synchronous Interface Timing Diagrams
Revision History
Rev. F, Production – 1/18
Rev. E, Production – 3/10
Rev. D, Production – 1/10
Rev. C – 9/09
Rev. B – 2/09
Rev. A – 1/09
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F16G08ABABA, MT29F32G08AFABA, MT29F64G08A[J/K/M]ABA,
MT29F128G08AUABA, MT29F16G08ABCBB, MT29F32G08AECBB,
MT29F64G08A[K/M]CBB, MT29F128G08AUCBB
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: 10 years
– Endurance: 100,000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
Note:
1. The ONFI 2.1 specification is available at
www.onfi.org.
Features
• Open NAND Flash Interface (ONFI) 2.1-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 128 pages (512K +28K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 16Gb: 4096 blocks;
32Gb: 8192 blocks;
64Gb: 16,384 blocks;
128Gb: 32,768 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 4
– Clock rate: 12ns (DDR)
– Read/write throughput per pin: 166 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 4
– tRC/tWC: 25ns (MIN)
• Array performance
– Read page: 25μs (MAX)
– Program page: 230μs (TYP)
– Erase block: 700μs (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 110).
• RESET (FFh) required as first command after pow-
er-on
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
Products and specifications discussed herein are subject to change by Micron without notice.
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 16G 08 A B A B A WP
ES
:B
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
16G = 16Gb
32G = 32Gb
64G = 64Gb
128G = 128Gb
Device Width
08 = 8 bits
Level
Bit/Cell
A
1-bit
Classification
B
E
F
J
K
M
U
1
2
2
2
2
4
4
Die # of CE# # of R/B# I/O
1
2
2
4
4
4
8
1 Common
2
Separate
2 Common
2 Common
Separate
2
Separate
4
4
Separate
Operating Voltage Range
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V)
Note:
1. Pb-free package.
Design Revision
B = Second revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (synchronous mode only)
-12 = 166 MT/s
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1
WP = 48-pin TSOP1 (CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
B = Second set of device features
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
Contents
Important Notes and Warnings ......................................................................................................................... 9
General Description ....................................................................................................................................... 10
Asynchronous and Synchronous Signal Descriptions ....................................................................................... 10
Signal Assignments ......................................................................................................................................... 12
Package Dimensions ....................................................................................................................................... 16
Architecture ................................................................................................................................................... 21
Device and Array Organization ........................................................................................................................ 22
Bus Operation – Asynchronous Interface ......................................................................................................... 30
Asynchronous Enable/Standby ................................................................................................................... 30
Asynchronous Bus Idle ............................................................................................................................... 30
Asynchronous Pausing Data Input/Output .................................................................................................. 31
Asynchronous Commands .......................................................................................................................... 31
Asynchronous Addresses ............................................................................................................................ 32
Asynchronous Data Input ........................................................................................................................... 33
Asynchronous Data Output ......................................................................................................................... 34
Write Protect .............................................................................................................................................. 35
Ready/Busy# .............................................................................................................................................. 35
Bus Operation – Synchronous Interface ........................................................................................................... 40
Synchronous Enable/Standby ..................................................................................................................... 41
Synchronous Bus Idle/Driving .................................................................................................................... 41
Synchronous Pausing Data Input/Output .................................................................................................... 42
Synchronous Commands ............................................................................................................................ 42
Synchronous Addresses .............................................................................................................................. 43
Synchronous DDR Data Input ..................................................................................................................... 44
Synchronous DDR Data Output .................................................................................................................. 45
Write Protect .............................................................................................................................................. 47
Ready/Busy# .............................................................................................................................................. 47
Device Initialization ....................................................................................................................................... 48
Activating Interfaces ....................................................................................................................................... 50
Activating the Asynchronous Interface ........................................................................................................ 50
Activating the Synchronous Interface .......................................................................................................... 50
Command Definitions .................................................................................................................................... 52
Reset Operations ............................................................................................................................................ 54
RESET (FFh) ............................................................................................................................................... 54
SYNCHRONOUS RESET (FCh) .................................................................................................................... 55
Identification Operations ................................................................................................................................ 56
READ ID (90h) ............................................................................................................................................ 56
READ ID Parameter Tables .............................................................................................................................. 57
Configuration Operations ............................................................................................................................... 58
SET FEATURES (EFh) .................................................................................................................................. 58
GET FEATURES (EEh) ................................................................................................................................. 59
READ PARAMETER PAGE (ECh) ...................................................................................................................... 63
Parameter Page Data Structure Tables ............................................................................................................. 64
READ UNIQUE ID (EDh) ................................................................................................................................ 72
Status Operations ........................................................................................................................................... 74
READ STATUS (70h) ................................................................................................................................... 75
READ STATUS ENHANCED (78h) ................................................................................................................ 76
Column Address Operations ........................................................................................................................... 77
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 77
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 78
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
CHANGE WRITE COLUMN (85h) ................................................................................................................ 79
CHANGE ROW ADDRESS (85h) ................................................................................................................... 80
Read Operations ............................................................................................................................................. 82
READ MODE (00h) ..................................................................................................................................... 84
READ PAGE (00h-30h) ................................................................................................................................ 85
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 86
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 87
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 89
READ PAGE MULTI-PLANE (00h-32h) ......................................................................................................... 90
Program Operations ....................................................................................................................................... 92
PROGRAM PAGE (80h-10h) ......................................................................................................................... 92
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 94
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 96
Erase Operations ............................................................................................................................................ 98
ERASE BLOCK (60h-D0h) ............................................................................................................................ 98
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 99
Copyback Operations .................................................................................................................................... 100
COPYBACK READ (00h-35h) ...................................................................................................................... 101
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 102
COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 102
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 103
One-Time Programmable (OTP) Operations ................................................................................................... 104
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 105
PROTECT OTP AREA (80h-10h) .................................................................................................................. 106
READ OTP PAGE (00h-30h) ........................................................................................................................ 107
Multi-Plane Operations ................................................................................................................................. 108
Multi-Plane Addressing ............................................................................................................................. 108
Interleaved Die (Multi-LUN) Operations ......................................................................................................... 108
Error Management ........................................................................................................................................ 110
Output Drive Impedance ............................................................................................................................... 111
AC Overshoot/Undershoot Specifications ....................................................................................................... 114
Synchronous Input Slew Rate ......................................................................................................................... 115
Output Slew Rate ........................................................................................................................................... 116
Electrical Specifications ................................................................................................................................. 117
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 119
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) ................................... 120
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 120
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 123
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 125
Electrical Specifications – Array Characteristics .............................................................................................. 128
Asynchronous Interface Timing Diagrams ...................................................................................................... 129
Synchronous Interface Timing Diagrams ........................................................................................................ 140
Revision History ............................................................................................................................................ 162
Rev. F, Production – 1/18 ............................................................................................................................ 162
Rev. E, Production – 3/10 ........................................................................................................................... 162
Rev. D, Production – 1/10 ........................................................................................................................... 162
Rev. C – 9/09 .............................................................................................................................................. 162
Rev. B – 2/09 .............................................................................................................................................. 162
Rev. A – 1/09 .............................................................................................................................................. 163
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................ 10
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 29
Table 3: Asynchronous Interface Mode Selection ............................................................................................ 30
Table 4: Synchronous Interface Mode Selection .............................................................................................. 40
Table 5: Command Set .................................................................................................................................. 52
Table 6: Read ID Parameters for Address 00h .................................................................................................. 57
Table 7: Read ID Parameters for Address 20h .................................................................................................. 57
Table 8: Feature Address Definitions .............................................................................................................. 58
Table 9: Feature Address 01h: Timing Mode .................................................................................................... 60
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength .............................................. 60
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 61
Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 61
Table 13: Parameter Page Data Structure ........................................................................................................ 64
Table 14: Status Register Definition ................................................................................................................ 74
Table 15: OTP Area Details ............................................................................................................................ 105
Table 16: Error Management Details ............................................................................................................. 110
Table 17: Output Drive Strength Conditions (VCCQ = 1.7–1.95V) ...................................................................... 111
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) ........................................................... 111
Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 112
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 112
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 113
Table 22: Asynchronous Overshoot/Undershoot Parameters .......................................................................... 114
Table 23: Synchronous Overshoot/Undershoot Parameters ............................................................................ 114
Table 24: Test Conditions for Input Slew Rate ................................................................................................ 115
Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 115
Table 26: Test Conditions for Output Slew Rate .............................................................................................. 116
Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) ............................................................................................... 116
Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 116
Table 29: Absolute Maximum Ratings by Device ............................................................................................ 117
Table 30: Recommended Operating Conditions ............................................................................................. 117
Table 31: Valid Blocks per LUN ...................................................................................................................... 117
Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 118
Table 33: Capacitance: 48-Pin TSOP Package ................................................................................................. 118
Table 34: Capacitance: 52-Pad LGA Package .................................................................................................. 118
Table 35: Test Conditions .............................................................................................................................. 119
Table 36: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 119
Table 37: DC Characteristics and Operating Conditions (Synchronous Interface) ............................................ 120
Table 38: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 120
Table 39: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 122
Table 40: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 123
Table 41: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 125
Table 42: Array Characteristics ...................................................................................................................... 128
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
List of Figures
Figure 1: Part Numbering ................................................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1 (Top View) ........................................................................................................ 12
Figure 3: 52-Pad LGA (Top View) .................................................................................................................... 13
Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 14
Figure 5: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................. 16
Figure 6: 52-Pad VLGA ................................................................................................................................... 17
Figure 7: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) ......................................................................... 18
Figure 8: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) ......................................................................... 19
Figure 9: 100-Ball LBGA – 12mm x 18mm (Package Code: H3) ......................................................................... 20
Figure 10: NAND Flash Die (LUN) Functional Block Diagram .......................................................................... 21
Figure 11: Device Organization for Single-Die Package (TSOP/BGA) ................................................................ 22
Figure 12: Device Organization for Two-Die Package (TSOP) ........................................................................... 23
Figure 13: Device Organization for Two-Die Package (BGA) ............................................................................. 24
Figure 14: Device Organization for Four-Die Package (TSOP) .......................................................................... 25
Figure 15: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) ....................................... 26
Figure 16: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) ................... 27
Figure 17: Device Organization for Eight-Die Package (BGA/LGA) ................................................................... 28
Figure 18: Array Organization per Logical Unit (LUN) ..................................................................................... 29
Figure 19: Asynchronous Command Latch Cycle ............................................................................................ 31
Figure 20: Asynchronous Address Latch Cycle ................................................................................................ 32
Figure 21: Asynchronous Data Input Cycles .................................................................................................... 33
Figure 22: Asynchronous Data Output Cycles ................................................................................................. 34
Figure 23: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 35
Figure 24: READ/BUSY# Open Drain .............................................................................................................. 36
Figure 25: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 37
Figure 26: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 37
Figure 27: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 38
Figure 28: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 38
Figure 29: TC vs Rp ........................................................................................................................................ 39
Figure 30: Synchronous Bus Idle/Driving Behavior ......................................................................................... 42
Figure 31: Synchronous Command Cycle ....................................................................................................... 43
Figure 32: Synchronous Address Cycle ........................................................................................................... 44
Figure 33: Synchronous DDR Data Input Cycles ............................................................................................. 45
Figure 34: Synchronous DDR Data Output Cycles ........................................................................................... 47
Figure 35: R/B# Power-On Behavior ............................................................................................................... 48
Figure 36: Activating the Synchronous Interface ............................................................................................. 51
Figure 37: RESET (FFh) Operation .................................................................................................................. 54
Figure 38: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 55
Figure 39: READ ID (90h) with 00h Address Operation .................................................................................... 56
Figure 40: READ ID (90h) with 20h Address Operation .................................................................................... 56
Figure 41: SET FEATURES (EFh) Operation .................................................................................................... 59
Figure 42: GET FEATURES (EEh) Operation .................................................................................................... 59
Figure 43: READ PARAMETER (ECh) Operation .............................................................................................. 63
Figure 44: READ UNIQUE ID (EDh) Operation ............................................................................................... 73
Figure 45: READ STATUS (70h) Operation ...................................................................................................... 76
Figure 46: READ STATUS ENHANCED (78h) Operation ................................................................................... 76
Figure 47: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 77
Figure 48: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation .......................................................... 78
Figure 49: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 79
Figure 50: CHANGE ROW ADDRESS (85h) Operation ...................................................................................... 81
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
Figure 51: READ PAGE (00h-30h) Operation ................................................................................................... 85
Figure 52: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 86
Figure 53: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 88
Figure 54: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 89
Figure 55: READ PAGE MULTI-PLANE (00h-32h) Operation ............................................................................ 91
Figure 56: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 93
Figure 57: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 95
Figure 58: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 95
Figure 59: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation .................................................................... 97
Figure 60: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 98
Figure 61: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation ....................................................................... 99
Figure 62: COPYBACK READ (00h-35h) Operation ......................................................................................... 101
Figure 63: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation ......................... 101
Figure 64: COPYBACK PROGRAM (85h–10h) Operation ................................................................................. 102
Figure 65: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation ........................ 102
Figure 66: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation .......................................................... 103
Figure 67: PROGRAM OTP PAGE (80h-10h) Operation ................................................................................... 105
Figure 68: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation ......................... 106
Figure 69: PROTECT OTP AREA (80h-10h) Operation ..................................................................................... 107
Figure 70: READ OTP PAGE (00h-30h) Operation ........................................................................................... 107
Figure 71: Overshoot .................................................................................................................................... 114
Figure 72: Undershoot .................................................................................................................................. 114
Figure 73: RESET Operation .......................................................................................................................... 129
Figure 74: READ STATUS Cycle ..................................................................................................................... 129
Figure 75: READ STATUS ENHANCED Cycle .................................................................................................. 130
Figure 76: READ PARAMETER PAGE ............................................................................................................. 131
Figure 77: READ PAGE .................................................................................................................................. 131
Figure 78: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 132
Figure 79: CHANGE READ COLUMN ............................................................................................................ 133
Figure 80: READ PAGE CACHE SEQUENTIAL ................................................................................................ 134
Figure 81: READ PAGE CACHE RANDOM ...................................................................................................... 135
Figure 82: READ ID Operation ...................................................................................................................... 136
Figure 83: PROGRAM PAGE Operation .......................................................................................................... 136
Figure 84: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 137
Figure 85: PROGRAM PAGE Operation with CHANGE WRITE COLUMN ......................................................... 137
Figure 86: PROGRAM PAGE CACHE .............................................................................................................. 138
Figure 87: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 138
Figure 88: COPYBACK .................................................................................................................................. 139
Figure 89: ERASE BLOCK Operation .............................................................................................................. 139
Figure 90: SET FEATURES Operation ............................................................................................................ 140
Figure 91: READ ID Operation ...................................................................................................................... 141
Figure 92: GET FEATURES Operation ............................................................................................................ 142
Figure 93: RESET (FCh) Operation ................................................................................................................ 143
Figure 94: READ STATUS Cycle ..................................................................................................................... 144
Figure 95: READ STATUS ENHANCED Operation .......................................................................................... 145
Figure 96: READ PARAMETER PAGE Operation ............................................................................................. 146
Figure 97: READ PAGE Operation .................................................................................................................. 147
Figure 98: CHANGE READ COLUMN ............................................................................................................ 148
Figure 99: READ PAGE CACHE SEQUENTIAL (1 of 2) ..................................................................................... 149
Figure 100: READ PAGE CACHE SEQUENTIAL (2 of 2) ................................................................................... 150
Figure 101: READ PAGE CACHE RANDOM (1 of 2) ......................................................................................... 151
Figure 102: READ PAGE CACHE RANDOM (2 of 2) ......................................................................................... 151
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
Figure 103: Multi-Plane Read Page (1 of 2) ..................................................................................................... 152
Figure 104: Multi-Plane Read Page (2 of 2) ..................................................................................................... 153
Figure 105: PROGRAM PAGE Operation (1 of 2) ............................................................................................. 154
Figure 106: PROGRAM PAGE Operation (2 of 2) ............................................................................................. 154
Figure 107: CHANGE WRITE COLUMN ......................................................................................................... 155
Figure 108: Multi-Plane Program Page ........................................................................................................... 156
Figure 109: ERASE BLOCK ............................................................................................................................ 157
Figure 110: COPYBACK (1 of 3) ..................................................................................................................... 157
Figure 111: COPYBACK (2 of 3) ..................................................................................................................... 158
Figure 112: COPYBACK (3 of 3) ..................................................................................................................... 158
Figure 113: READ OTP PAGE ......................................................................................................................... 159
Figure 114: PROGRAM OTP PAGE (1 of 2) ...................................................................................................... 160
Figure 115: PROGRAM OTP PAGE (2 of 2) ...................................................................................................... 160
Figure 116: PROTECT OTP AREA ................................................................................................................... 161
PDF: CCM005-816717818-10495
Rev. F 1/18 EN
8
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© 2009 Micron Technology, Inc. All rights reserved.
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