Computer Architecture A Quantitative Approach(4th) 无水印pdf.pdf

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Cover

About the Authors

Foreword

Contents

Preface

Why We Wrote This Book

This Edition

Topic Selection and Organization

An Overview of the Content

Navigating the Text

Chapter Structure

Case Studies with Exercises

Supplemental Materials

Helping Improve This Book

Concluding Remarks

Acknowledgments

Contributors to the Fourth Edition

Contributors to Previous Editions

1 Fundamentals of Computer Design

1.1 Introduction

1.2 Classes of Computers

1.3 Defining Computer Architecture

1.4 Trends in Technology

1.5 Trends in Power in Integrated Circuits

1.6 Trends in Cost

1.7 Dependability

1.8 Measuring, Reporting, and Summarizing Performance

1.9 Quantitative Principles of Computer Design

1.10 Putting It All Together: Performance and Price-Performance

1.11 Fallacies and Pitfalls

1.12 Concluding Remarks

1.13 Historical Perspectives and References

Case Studies with Exercises by Diana Franklin

2 Instruction-Level Parallelism and Its Exploitation

2.1 Instruction-Level Parallelism: Concepts and Challenges

2.2 Basic Compiler Techniques for Exposing ILP

2.3 Reducing Branch Costs with Prediction

2.4 Overcoming Data Hazards with Dynamic Scheduling

2.5 Dynamic Scheduling: Examples and the Algorithm

2.6 Hardware-Based Speculation

2.7 Exploiting ILP Using Multiple Issue and Static Scheduling

2.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation

2.9 Advanced Techniques for Instruction Delivery and Speculation

2.10 Putting It All Together: The Intel Pentium 4

2.11 Fallacies and Pitfalls

2.12 Concluding Remarks

2.13 Historical Perspective and References

Case Studies with Exercises by Robert P. Colwell

3 Limits on Instruction-Level Parallelism

3.1 Introduction

3.2 Studies of the Limitations of ILP

3.3 Limitations on ILP for Realizable Processors

3.4 Crosscutting Issues: Hardware versus Software Speculation

3.5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism

3.6 Putting It All Together: Performance and Efficiency in Advanced Multiple-Issue Processors

3.7 Fallacies and Pitfalls

3.8 Concluding Remarks

3.9 Historical Perspective and References

Case Study with Exercises by Wen-mei W. Hwu and John W. Sias

4 Multiprocessors and Thread-Level Parallelism

4.1 Introduction

4.2 Symmetric Shared-Memory Architectures

4.3 Performance of Symmetric Shared-Memory Multiprocessors

4.4 Distributed Shared Memory and Directory-Based Coherence

4.5 Synchronization: The Basics

4.6 Models of Memory Consistency: An Introduction

4.7 Crosscutting Issues

4.8 Putting It All Together: The Sun T1 Multiprocessor

4.9 Fallacies and Pitfalls

4.10 Concluding Remarks

4.11 Historical Perspective and References

Case Studies with Exercises by David A. Wood

5 Memory Hierarchy Design

5.1 Introduction

5.2 Eleven Advanced Optimizations of Cache Performance

5.3 Memory Technology and Optimizations

5.4 Protection: Virtual Memory and Virtual Machines

5.5 Crosscutting Issues: The Design of Memory Hierarchies

5.6 Putting It All Together: AMD Opteron Memory Hierarchy

5.7 Fallacies and Pitfalls

5.8 Concluding Remarks

5.9 Historical Perspective and References

Case Studies with Exercises by Norman P. Jouppi

6 Storage Systems

6.1 Introduction

6.2 Advanced Topics in Disk Storage

6.3 Definition and Examples of Real Faults and Failures

6.4 I/O Performance, Reliability Measures, and Benchmarks

6.5 A Little Queuing Theory

6.6 Crosscutting Issues

6.7 Designing and Evaluating an I/O System - The Internet Archive Cluster

6.8 Putting It All Together: NetApp FAS6000 Filer

6.9 Fallacies and Pitfalls

6.10 Concluding Remarks

6.11 Historical Perspective and References

Case Studies with Exercises by Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau

A Pipelining: Basic and Intermediate Concepts

A.1 Introduction

A.2 The Major Hurdle of Pipelining - Pipeline Hazards

A.3 How Is Pipelining Implemented?

A.4 What Makes Pipelining Hard to Implement?

A.5 Extending the MIPS Pipeline to Handle Multicycle Operations

A.6 Putting It All Together: The MIPS R4000 Pipeline

A.7 Crosscutting Issues

A.8 Fallacies and Pitfalls

A.9 Concluding Remarks

A.10 Historical Perspective and References

B Instruction Set Principles and Examples

B.1 Introduction

B.2 Classifying Instruction Set Architectures

B.3 Memory Addressing

B.4 Type and Size of Operands

B.5 Operations in the Instruction Set

B.6 Instructions for Control Flow

B.7 Encoding an Instruction Set

B.8 Crosscutting Issues: The Role of Compilers

B.9 Putting It All Together: The MIPS Architecture

B.10 Fallacies and Pitfalls

B.11 Concluding Remarks

B.12 Historical Perspective and References

C Review of Memory Hierarchy

C.1 Introduction

C.2 Cache Performance

C.3 Six Basic Cache Optimizations

C.4 Virtual Memory

C.5 Protection and Examples of Virtual Memory

C.6 Fallacies and Pitfalls

C.7 Concluding Remarks

C.8 Historical Perspective and References

References

Index

About the CD

www.dbeBooks.com - An Ebook Library

In Praise of Fourth Edition Computer Architecture: A Quantitative Approach “The multiprocessor is here and it can no longer be avoided. As we bid farewell to single-core processors and move into the chip multiprocessing age, it is great timing for a new edition of Hennessy and Patterson’s classic. Few books have had as signiﬁcant an impact on the way their discipline is taught, and the current edi- tion will ensure its place at the top for some time to come.” —Luiz André Barroso, Google Inc. “What do the following have in common: Beatles’ tunes, HP calculators, choco- late chip cookies, and ? They are all classics that have stood the test of time.” Computer Architecture —Robert P. Colwell, Intel lead architect “Not only does the book provide an authoritative reference on the concepts that all computer architects should be familiar with, but it is also a good starting point for investigations into emerging areas in the ﬁeld.” —Krisztián Flautner, ARM Ltd. “The best keeps getting better! This new edition is updated and very relevant to the key issues in computer architecture today. Plus, its new exercise paradigm is much more useful for both students and instructors.” —Norman P. Jouppi, HP Labs builds on fundamentals that yielded the RISC revolution, “ Computer Architecture including the enablers for CISC translation. Now, in this new edition, it clearly explains and gives insight into the latest microarchitecture techniques needed for the new generation of multithreaded multicore processors.” —Marc Tremblay, Fellow & VP, Chief Architect, Sun Microsystems “This is a great textbook on all key accounts: pedagogically superb in exposing the ideas and techniques that deﬁne the art of computer organization and design, stimulating to read, and comprehensive in its coverage of topics. The ﬁrst edition set a standard of excellence and relevance; this latest edition does it again.” —Milos˘ Ercegovac, UCLA “They’ve done it again. Hennessy and Patterson emphatically demonstrate why they are the doyens of this deep and shifting ﬁeld. Fallacy: Computer architecture isn’t an essential subject in the information age. Pitfall: You don’t need the 4th edition of ” Computer Architecture. —Michael D. Smith, Harvard University

“Hennessy and Patterson have done it again! The 4th edition is a classic encore that has been adapted beautifully to meet the rapidly changing constraints of ‘late-CMOS-era’ technology. The detailed case studies of real processor products are especially educational, and the text reads so smoothly that it is difﬁcult to put down. This book is a must-read for students and professionals alike!” —Pradip Bose, IBM “This latest edition of is sure to provide students with the architectural framework and foundation they need to become inﬂuential archi- tects of the future.” Computer Architecture — Ravishankar Iyer, Intel Corp. “As technology has advanced, and design opportunities and constraints have changed, so has this book. The 4th edition continues the tradition of presenting the latest in innovations with commercial impact, alongside the foundational con- cepts: advanced processor and memory system design techniques, multithreading and chip multiprocessors, storage systems, virtual machines, and other concepts. This book is an excellent resource for anybody interested in learning the architec- tural concepts underlying real commercial products.” —Gurindar Sohi, University of Wisconsin–Madison “I am very happy to have my students study computer architecture using this fan- tastic book and am a little jealous for not having written it myself.” —Mateo Valero, UPC, Barcelona “Hennessy and Patterson continue to evolve their teaching methods with the changing landscape of computer system design. Students gain unique insight into the factors inﬂuencing the shape of computer architecture design and the poten- tial research directions in the computer systems ﬁeld.” —Dan Connors, University of Colorado at Boulder “With this revision, puter architecture students in the coming decade.” Computer Architecture will remain a must-read for all com- —Wen-mei Hwu, University of Illinois at Urbana–Champaign Computer Architecture “The 4th edition of continues in the tradition of providing a relevant and cutting edge approach that appeals to students, researchers, and designers of computer systems. The lessons that this new edition teaches will continue to be as relevant as ever for its readers.” —David Brooks, Harvard University “With the 4th edition, Hennessy and Patterson have shaped ture back to the lean focus that made the 1st edition an instant classic.” Computer Architec- —Mark D. Hill, University of Wisconsin–Madison

Computer Architecture A Quantitative Approach Fourth Edition

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hen- nessy is a Fellow of the IEEE and ACM, a member of the National Academy of Engineering and the National Academy of Science, and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC tech- nology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neu- mann Award, which he shared with David Patterson. He has also received seven honorary doctorates. In 1981, he started the MIPS project at Stanford with a handful of graduate students. After com- pleting the project in 1984, he took a one-year leave from the university to cofound MIPS Com- puter Systems, which developed one of the ﬁrst commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2006, over 500 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. David A. Patterson has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, where he holds the Pardee Chair of Computer Sci- ence. His teaching has been honored by the Abacus Award from Upsilon Pi Epsilon, the Distin- guished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson re- ceived the IEEE Technical Achievement Award for contributions to RISC and shared the IEEE Johnson Information Storage Award for contributions to RAID. He then shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley En- gineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Com- puting Research Association, and as President of ACM. This record led to a Distinguished Service Award from CRA. At Berkeley, Patterson led the design and implementation of RISC I, likely the ﬁrst VLSI reduced instruction set computer. This research became the foundation of the SPARC architecture, cur- rently used by Sun Microsystems, Fujitsu, and others. He was a leader of the Redundant Arrays of Inexpensive Disks (RAID) project, which led to dependable storage systems from many com- panies. He was also involved in the Network of Workstations (NOW) project, which led to cluster technology used by Internet companies. These projects earned three dissertation awards from the ACM. His current research projects are the RAD Lab, which is inventing technology for reli- able, adaptive, distributed Internet services, and the Research Accelerator for Multiple Proces- sors (RAMP) project, which is developing and distributing low-cost, highly scalable, parallel computers based on FPGAs and open-source hardware and software.

Computer Architecture A Quantitative Approach Fourth Edition John L. Hennessy Stanford University David A. Patterson University of California at Berkeley With Contributions by Andrea C. Arpaci-Dusseau University of Wisconsin–Madison Remzi H. Arpaci-Dusseau University of Wisconsin–Madison Krste Asanovic Massachusetts Institute of Technology Robert P. Colwell R&E Colwell & Associates, Inc. Thomas M. Conte North Carolina State University José Duato Universitat Politècnica de València and Simula Diana Franklin California Polytechnic State University, San Luis Obispo David Goldberg Xerox Palo Alto Research Center Wen-mei W. Hwu University of Illinois at Urbana–Champaign Norman P. Jouppi HP Labs Timothy M. Pinkston University of Southern California John W. Sias University of Illinois at Urbana–Champaign David A. Wood University of Wisconsin–Madison Amsterdam • Boston • Heidelberg • London New York • Oxford • Paris • San Diego San Francisco • Singapore • Sydney • Tokyo

Denise E. M. Penrose Publisher Project Manager In-house Senior Project Manager Developmental Editor Editorial Assistant Cover Design Cover Image Composition Text Design: Technical Illustration Copyeditor Proofreader Indexer Printer Ken Della Penta Jamie Thaman Nancy Ball Dusty Friedman, The Book Company Brandy Lilly Nate McFadden Kimberlee Honjo Elisabeth Beller and Ross Carron Design Richard I’Anson’s Collection: Lonely Planet Images Nancy Logan Rebecca Evans & Associates David Ruppe, Impact Publications Maple-Vail Book Manufacturing Group Morgan Kaufmann Publishers is an Imprint of Elsevier 500 Sansome Street, Suite 400, San Francisco, CA 94111 This book is printed on acid-free paper. © 1990, 1996, 2003, 2007 by Elsevier, Inc. All rights reserved. Published 1990. Fourth edition 2007 Designations used by companies to distinguish their products are often claimed as trademarks or reg- istered trademarks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (+44) 1865 843830, fax: (+44) 1865 853333, e-mail: permissions@elsevier. com. You may also complete your request on-line via the Elsevier Science homepage ( http:// elsevier.com ), by selecting “Customer Support” and then “Obtaining Permissions.” Library of Congress Cataloging-in-Publication Data Hennessy, John L. Computer architecture : a quantitative approach / John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau . . . [et al.]. —4th ed. p.cm. Includes bibliographical references and index. ISBN 13: 978-0-12-370490-0 (pbk. : alk. paper) ISBN 10: 0-12-370490-1 (pbk. : alk. paper) 1. Computer architecture. I. Patterson, David A. II. Arpaci-Dusseau, Andrea C. III. Title. QA76.9.A73P377 2006 004.2'2—dc22 2006024358 For all information on all Morgan Kaufmann publications, visit our website at www.books.elsevier.com www.mkp.com or Printed in the United States of America 06 07 08 09 10 5 4 3 2 1

To Andrea, Linda, and our four sons

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