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stm32zet6芯片手册.pdf
Table 1. Device summary
1 Introduction
2 Description
2.1 Device overview
Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts
Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram
Figure 2. Clock tree
2.2 Full compatibility throughout the family
Table 3. STM32F103xx family
2.3 Overview
2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM
2.3.2 Embedded Flash memory
2.3.3 CRC (cyclic redundancy check) calculation unit
2.3.4 Embedded SRAM
2.3.5 FSMC (flexible static memory controller)
2.3.6 LCD parallel interface
2.3.7 Nested vectored interrupt controller (NVIC)
2.3.8 External interrupt/event controller (EXTI)
2.3.9 Clocks and startup
2.3.10 Boot modes
2.3.11 Power supply schemes
2.3.12 Power supply supervisor
2.3.13 Voltage regulator
2.3.14 Low-power modes
2.3.15 DMA
2.3.16 RTC (real-time clock) and backup registers
2.3.17 Timers and watchdogs
Table 4. High-density timer feature comparison
2.3.18 I²C bus
2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs)
2.3.20 Serial peripheral interface (SPI)
2.3.21 Inter-integrated sound (I2S)
2.3.22 SDIO
2.3.23 Controller area network (CAN)
2.3.24 Universal serial bus (USB)
2.3.25 GPIOs (general-purpose inputs/outputs)
2.3.26 ADC (analog to digital converter)
2.3.27 DAC (digital-to-analog converter)
2.3.28 Temperature sensor
2.3.29 Serial wire JTAG debug port (SWJ-DP)
2.3.30 Embedded Trace Macrocell™
3 Pinouts and pin descriptions
Figure 3. STM32F103xC/D/E BGA144 ballout
Figure 4. STM32F103xC/D/E performance line BGA100 ballout
Figure 5. STM32F103xC/D/E performance line LQFP144 pinout
Figure 6. STM32F103xC/D/E performance line LQFP100 pinout
Figure 7. STM32F103xC/D/E performance line LQFP64 pinout
Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side
Table 5. High-density STM32F103xC/D/E pin definitions
Table 6. FSMC pin definition
4 Memory mapping
Figure 9. Memory map
5 Electrical characteristics
5.1 Parameter conditions
5.1.1 Minimum and maximum values
5.1.2 Typical values
5.1.3 Typical curves
5.1.4 Loading capacitor
5.1.5 Pin input voltage
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
5.1.6 Power supply scheme
Figure 12. Power supply scheme
5.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
5.2 Absolute maximum ratings
Table 7. Voltage characteristics
Table 8. Current characteristics
Table 9. Thermal characteristics
5.3 Operating conditions
5.3.1 General operating conditions
Table 10. General operating conditions
5.3.2 Operating conditions at power-up / power-down
Table 11. Operating conditions at power-up / power-down
5.3.3 Embedded reset and power control block characteristics
Table 12. Embedded reset and power control block characteristics
5.3.4 Embedded reference voltage
Table 13. Embedded internal reference voltage
5.3.5 Supply current characteristics
Table 14. Maximum current consumption in Run mode, code with data processing running from Flash
Table 15. Maximum current consumption in Run mode, code with data processing running from RAM
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)- code with data processing running from RAM, peripherals disabled
Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM
Table 17. Typical and maximum current consumptions in Stop and Standby modes
Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values
Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values
Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values
Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values
Table 18. Typical current consumption in Run mode, code with data processing running from Flash
Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM
Table 20. Peripheral current consumption
5.3.6 External clock source characteristics
Table 21. High-speed external user clock characteristics
Table 22. Low-speed external user clock characteristics
Figure 20. High-speed external clock source AC timing diagram
Figure 21. Low-speed external clock source AC timing diagram
Table 23. HSE 4-16 MHz oscillator characteristics
Figure 22. Typical application with an 8 MHz crystal
Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz)
Figure 23. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
Table 25. HSI oscillator characteristics
Table 26. LSI oscillator characteristics
Table 27. Low-power mode wakeup timings
5.3.8 PLL characteristics
Table 28. PLL characteristics
5.3.9 Memory characteristics
Table 29. Flash memory characteristics
Table 30. Flash memory endurance and data retention
5.3.10 FSMC characteristics
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 33. Asynchronous multiplexed PSRAM/NOR read timings
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 34. Asynchronous multiplexed PSRAM/NOR write timings
Figure 28. Synchronous multiplexed NOR/PSRAM read timings
Table 35. Synchronous multiplexed NOR/PSRAM read timings
Figure 29. Synchronous multiplexed PSRAM write timings
Table 36. Synchronous multiplexed PSRAM write timings
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings
Table 37. Synchronous non-multiplexed NOR/PSRAM read timings
Figure 31. Synchronous non-multiplexed PSRAM write timings
Table 38. Synchronous non-multiplexed PSRAM write timings
Figure 32. PC Card/CompactFlash controller waveforms for common memory read access
Figure 33. PC Card/CompactFlash controller waveforms for common memory write access
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access
Table 39. Switching characteristics for PC Card/CF read and write cycles
Figure 38. NAND controller waveforms for read access
Figure 39. NAND controller waveforms for write access
Figure 40. NAND controller waveforms for common memory read access
Figure 41. NAND controller waveforms for common memory write access
Table 40. Switching characteristics for NAND Flash read and write cycles
5.3.11 EMC characteristics
Table 41. EMS characteristics
Table 42. EMI characteristics
5.3.12 Absolute maximum ratings (electrical sensitivity)
Table 43. ESD absolute maximum ratings
Table 44. Electrical sensitivities
5.3.13 I/O current injection characteristics
Table 45. I/O current injection susceptibility
5.3.14 I/O port characteristics
Table 46. I/O static characteristics
Figure 42. Standard I/O input characteristics - CMOS port
Figure 43. Standard I/O input characteristics - TTL port
Figure 44. 5 V tolerant I/O input characteristics - CMOS port
Figure 45. 5 V tolerant I/O input characteristics - TTL port
Table 47. Output voltage characteristics
Table 48. I/O AC characteristics
Figure 46. I/O AC characteristics definition
5.3.15 NRST pin characteristics
Table 49. NRST pin characteristics
Figure 47. Recommended NRST pin protection
5.3.16 TIM timer characteristics
Table 50. TIMx characteristics
5.3.17 Communications interfaces
Table 51. I2C characteristics
Figure 48. I2C bus AC waveforms and measurement circuit
Table 52. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V)
Table 53. SPI characteristics
Figure 49. SPI timing diagram - slave mode and CPHA = 0
Figure 50. SPI timing diagram - slave mode and CPHA = 1(1)
Figure 51. SPI timing diagram - master mode(1)
Table 54. I2S characteristics
Figure 52. I2S slave timing diagram (Philips protocol)(1)
Figure 53. I2S master timing diagram (Philips protocol)(1)
Figure 54. SDIO high-speed mode
Figure 55. SD default mode
Table 55. SD / MMC characteristics
Table 56. USB startup time
Table 57. USB DC electrical characteristics
Figure 56. USB timings: definition of data signal rise and fall time
Table 58. USB: full-speed electrical characteristics
5.3.18 CAN (controller area network) interface
5.3.19 12-bit ADC characteristics
Table 59. ADC characteristics
Table 60. RAIN max for fADC = 14 MHz
Table 61. ADC accuracy - limited test conditions
Table 62. ADC accuracy
Figure 57. ADC accuracy characteristics
Figure 58. Typical connection diagram using the ADC
Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA)
5.3.20 DAC electrical specifications
Table 63. DAC characteristics
Figure 61. 12-bit buffered /non-buffered DAC
5.3.21 Temperature sensor characteristics
Table 64. TS characteristics
6 Package information
6.1 LFBGA144 package information
Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline
Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data
Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint
Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA)
Figure 64. LFBGA144 marking example (package top view)
6.2 LFBGA100 package information
Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline
Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data
Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprintoutline
Table 68. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA)
Figure 67. LFBGA100 marking example (package top view)
6.3 WLCSP64 package information
Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline
Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data
Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale package recommended footprint
Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch)
6.4 LQFP144 package information
Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline
Table 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data
Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint
Figure 72. LQFP144 marking example (package top view)
6.5 LQFP100 package information
Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline
Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Figure 74. LQFP100 recommended footprint
Figure 75. LQFP100 marking example (package top view)
6.6 LQFP64 package information
Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
Figure 78. LQFP64 marking example (package top view)
6.7 Thermal characteristics
Table 74. Package thermal characteristics
6.7.1 Reference document
6.7.2 Selecting the product temperature range
Figure 79. LQFP100 PD max vs. TA
7 Part numbering
Table 75. Ordering information scheme
8 Revision history
STM32F103xC, STM32F103xD,
STM32F103xE
High-density performance line ARM®-based 32-bit MCU with 256 to 512KB
Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
Datasheet − production data
Features
• Core: ARM® 32-bit Cortex®-M3 CPU
– 72 MHz maximum frequency, 1.25 DMIPS/MHz
(Dhrystone 2.1) performance at 0 wait state
memory access
– Single-cycle multiplication and hardware
division
• Memories
– 256 to 512 Kbytes of Flash memory
– up to 64 Kbytes of SRAM
– Flexible static memory controller with 4 Chip
Select. Supports Compact Flash, SRAM,
PSRAM, NOR and NAND memories
– LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage detector
(PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• 3 × 12-bit, 1 µs A/D converters (up to 21
channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor
• 2 × 12-bit D/A converters
• DMA: 12-channel DMA controller
– Supported peripherals: timers, ADCs, DAC,
SDIO, I2Ss, SPIs, I2Cs and USARTs
• Debug mode
– Serial wire debug (SWD) & JTAG interfaces
– Cortex®-M3 Embedded Trace Macrocell™
• Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
WLCSP64
LFBGA100 10 × 10 mm
LFBGA144 10 × 10 mm
LQFP64 10 × 10 mm,
LQFP100 14 × 14 mm,
LQFP144 20 × 20 mm
• Up to 11 timers
– Up to four 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
– 2 × 16-bit motor control PWM timers with dead-
time generation and emergency stop
– 2 × watchdog timers (Independent and Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC
• Up to 13 communication interfaces
– Up to 2 × I2C interfaces (SMBus/PMBus)
– Up to 5 USARTs (ISO 7816 interface, LIN, IrDA
capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I2S interface
multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface
• CRC calculation unit, 96-bit unique ID
• ECOPACK® packages
Table 1.Device summary
Reference
Part number
STM32F103xC STM32F103RC STM32F103VC
STM32F103ZC
STM32F103xD STM32F103RD STM32F103VD
STM32F103ZD
STM32F103xE STM32F103RE STM32F103ZE
STM32F103VE
November 2015
This is information on a product in full production.
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Contents
Contents
STM32F103xC, STM32F103xD, STM32F103xE
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 15
2.3.1
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.2
2.3.3
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.4
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.5
2.3.6
LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
2.3.7
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.8
2.3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.10
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.11
2.3.12
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.13
2.3.14
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.15
RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18
2.3.16
2.3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.18
Universal synchronous/asynchronous receiver transmitters (USARTs) 21
2.3.19
2.3.20
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.21
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.22
2.3.23
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.24
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.26
ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.27
2.3.28
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Contents
3
4
5
2.3.29
2.3.30
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2
5.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.1
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.2
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.4
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1.5
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 45
5.3.2
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 45
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.4
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.6
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.7
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.9
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.10
5.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 88
5.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.13
5.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.3.16
5.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.18
5.3.19
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Contents
STM32F103xC, STM32F103xD, STM32F103xE
5.3.20
5.3.21
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.1
LFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.2
LFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.4
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.5
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.6
6.7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.7.1
6.7.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 134
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6
7
8
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List of tables
List of tables
Table 1.
Table 2.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F103xC, STM32F103xD and STM32F103xE features
and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.
High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4.
High-density STM32F103xC/D/E pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5.
FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 6.
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7.
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 8.
Table 9.
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12.
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 13.
Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 14. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. Maximum current consumption in Run mode, code with data processing
Table 19.
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 49
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 50
Table 17.
Table 18.
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 67
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 68
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 76
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 82
Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 86
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
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Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 44.
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 45.
Table 46.
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 48.
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 49.
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 50.
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 51.
SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 52.
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 53.
I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 54.
Table 55.
SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 56.
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 57.
USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 58.
Table 59.
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 60.
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 61.
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 62.
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 63.
Table 64.
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
Table 65.
0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LFBGA144 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 116
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 119
Table 68.
Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
Table 66.
Table 67.
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 122
Table 71.
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 130
Table 73.
Table 74.
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 75. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 72.
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List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STM32F103xC/D/E BGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F103xC/D/E performance line BGA100 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM32F103xC/D/E performance line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F103xC/D/E performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM32F103xC/D/E performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM32F103xC/D/E performance line
WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9.
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 48
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)-
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 48
Figure 16. Typical current consumption on VBAT with RTC on vs. temperature
at different VBAT values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. Typical current consumption in Stop mode with regulator in run mode
versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. Typical current consumption in Stop mode with regulator in low-power
mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 19. Typical current consumption in Standby mode versus temperature at
different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 21.
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 66
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 67
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 78
Figure 33. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 79
Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 81
Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 82
Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 85
Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 86
Figure 42. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 43. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 44.
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 45.
Figure 46.
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 48.
Figure 49. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 51. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 52.
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 53.
Figure 54. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 55. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 56. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 57. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 58. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 110
Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 111
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 61.
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
Figure 62.
0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm,
0.8 mm pitch, package recommended footprintoutline . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 67.
Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale
Figure 66.
Figure 63.
Figure 64.
Figure 65.
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 69. WLCSP64 - 64-ball, 4.4757 x 4.4049 mm, 0.5 mm pitch wafer level chip scale
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 123
LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline . . . . . . . . . . . . . . 127
LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 130
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 131
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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