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gmiitorgmii.pdf
GMII to RGMII v4.0
Table of Contents
IP Facts
Ch. 1: Overview
Feature Summary
Applications
Unsupported Features
Licensing and Ordering
Ch. 2: Product Specification
Standards
Performance
Maximum Frequencies
Latency
Transmit Path
Receive Path
Throughput
Power
Resource Utilization
Port Descriptions
Internal Encrypted Hierarchy of the Core Level Ports
Input/Output Signals
Interfaces
Block Hierarchy Level Ports
Input/Output Signals
MDIO Management System
MDIO Bus System
MDIO Transactions
Write Transaction
Read Transaction
MDIO Addressing
Physical Address
Register Address
Connecting the MDIO to an Internally Integrated STA
Connecting the MDIO to an External PHY Device
Register Space
Control Register
Ch. 3: Designing with the Core
General Design Guidelines
Shared Logic
Clocking
Free Running Clock
GMII Transmit Clock
RGMII Transmit Clock to the External PHY Device
RGMII Receive Clock from the External PHY Device
Using Multiple Instances of the Core
Resets
Protocols
GMII Transmission
Normal Frame Transmission
Error Propagation
GMII Reception
Normal Frame Reception
Frame Reception with Errors
MII Transmission – 10/100 Mb/s Frame
MII Reception – 10/100 Mb/s Frame
RGMII Interface Protocols
RGMII Transmission and Reception
Ch. 4: Design Flow Steps
Customizing and Generating the Core
Shared Logic Options
User Parameters
Output Generation
Constraining the Core
Required Constraints
Vivado Design Suite
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Ch. 5: Example Design
External Clocking
Internal Clocking
Top-Level Example Design HDL
Ch. 6: Test Bench
Demonstration Test Bench
Customizing the Test Bench
Changing Frame Data
Changing Frame Error Status
Appx. A: Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Shared Logic
Parameter Changes from v3.0 to v4.0
Port Changes from v3.0 to v4.0
Parameter Changes from v2.0 to v3.0
Port Changes from v2.0 to v3.0
Appx. B: Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Simulation Debug
Hardware Debug
General Checks
Problems with the MDIO
Problems with Data Reception or Transmission
Problems with High Bit Error Rates
Appx. C: Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices
GMII to RGMII v4.0
LogiCORE IP Product Guide
Vivado Design Suite
PG160 June 6, 2018
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MDIO Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Protocols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 5: Example Design
External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Internal Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Top-Level Example Design HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Chapter 6: Test Bench
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Customizing the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Appendix A: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Introduction
The Xilinx® LogiCORE™ IP Gigabit Media
Independent Interface (GMII) to Reduced
Gigabit Media Independent Interface (RGMII)
core provides the RGMII between
RGMII-compliant Ethernet physical media
devices (PHY) and the Gigabit Ethernet
controller (GEM) in the Zynq®-7000 SoCs and
Zynq® UltraScale+™ MP SoCs. This core can be
used in all three modes of operation
(10/100/1000 Mb/s). The Management Data
Input/Output (MDIO) interface is used to
determine the speed of operation. This core can
switch dynamically between the three different
speed modes.
Features
•
•
• MDIO interface to set operating speed and
Tri-speed (10/100/1000 Mb/s) operation
Full-duplex operation
duplex mode by MAC
IP Facts
G
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family(1)
Supported User
Interfaces
Resources
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
S/W Driver
Design Entry
Simulation
Synthesis
Zynq® UltraScale+™ MP SoC,
Zynq®-7000 SoC
GMII
Performance and Resource Utilization web page
Provided with Core
Encrypted RTL
GMII to RGMII with internally
generated GMII clock
GMII to RGMII with externally
generated GMII clock
Demonstration Test Bench
XDC
Not Provided
N/A
Tested Design Flows(2)
Vivado® Design Suite
Vivado
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
IP catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
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Product Specification
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Chapter 1
Overview
The GMII to RGMII IP core provides the Reduced Gigabit Media Independent Interface
(RGMII) between Ethernet physical media devices and the Gigabit Ethernet controller in
Zynq®-7000 SoCs and Zynq® UltraScale+™ MP SoCs. This core can switch dynamically
between the three different speed modes of operation (10/100/1000 Mb/s).
Feature Summary
•
Tri-speed operation (10/100/1000 Mb/s)
The line speed can be changed dynamically (for example, during run time) by
programming the speed bits in the control register.
Full-duplex operation
•
• MDIO interface to set operating speed by Ethernet MAC
Speed settings are contained in the control register implemented within the core. MDIO
transactions are used to program this control register.
Applications
The GMII to RGMII IP core is designed for use with the Gigabit Ethernet embedded blocks
in the Zynq-7000 SoC and Zynq® UltraScale+™ MP SoC devices. The Gigabit Ethernet MAC
embedded blocks present in the Zynq-7000 SoC or Zynq® UltraScale+™ MP SoC device
would provide an RGMII interface through the Multiplexed I/O pins (MIO) and a GMII
interface through the EMIO interface to route through the Programmable Logic (PL). The
GMII to RGMII IP can be used to provide an RGMII interface using the PL. For more
information on the device specific Gigabit Ethernet Controller, see the Xilinx Zynq-7000 SoC
Technical Reference Manual [Ref 1] and Zynq UltraScale+ MPSoC Technical Reference Manual
[Ref 11].
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Chapter 1: Overview
Unsupported Features
There are no unsupported features for this core.
Licensing and Ordering
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
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Chapter 2
Product Specification
Figure 2-1 illustrates the connection of the Gigabit Ethernet Controller in the Zynq®-7000
SoC to the GMII to RGMII core. The same connection is applicable for Zynq® UltraScale+™
MP SoC too.
X-Ref Target - Figure 2-1
Zynq-7000
Gigabit Ethernet
Controller
gmii_txd(7:0)
gmii_tx_en
gmii_tx_er
gmii_tx_clk
gmii_rxd(7:0)
gmii_rx_dv
gmii_rx_er
gmii_rx_clk
gmii_crs
gmii_col
mdio_gem_mdc
mdio_gem_i
mdio_gem_o
mdio_gem_t
LogiCORE
GMII to RGMII
IP
rgmii_txd(3:0)
rgmii_tx_ctl
rgmii_txc
rgmii_rxd(3:0)
rgmii_rx_ctl
rgmii_rxc
mdio_phy_mdc
mdio_phy_i
mdio_phy_o
mdio_phy_t
BI-DI
IO
mdio
External
PHY
Device
Figure 2-1: GMII to RGMII Core Ports and Interfaces
IMPORTANT: The MDIO interface is necessary for the operation of the core because the
auto-negotiated speed of operation from the PHY is communicated to the Ethernet MAC through MDIO.
The clock input is 200 MHz for Zynq-7000 and 375 MHz for Zynq UltraScale+ MPSoC. It is
used as a reference clock for the IDELAYCTRL elements and input for the management
modules.
If the GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0), this 200/375 MHz clock is
the input clock to the MMCM from which the TX clocks for all line rates (125/12.5/2.5 MHz
for 1000/100/10 Mb/s, respectively) are generated.
Standards
•
•
Ethernet standard IEEE 802.3-2012 Clauses 22 and 35 [Ref 2]
Reduced Gigabit Media Independent Interface (RGMII) V2.0 [Ref 4]
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Chapter 2: Product Specification
Performance
This section describes the performance of the GMII to RGMII core.
Maximum Frequencies
The GMII to RGMII core operates at 125 MHz. The Management module operates at 200/
375 MHz.
Latency
The following measurements are for the core only and do not include any IOB registers.
Transmit Path
As measured from a data octet input into gmii_txd[7:0] of the transmitter side of GMII
interface until that data appears on the rgmii_txd[3:0] on the RGMII interface, the
latency through the core through the transmit direction is one clock period of
gmii_tx_clk_int.
Receive Path
Measured from a data octet input into rgmii_rxd[3:0] of the receiver side of the RGMII
interface until that data appears on the gmii_rxd[7:0] on the GMII interface, the latency
through the core through the receive direction is one clock period of rgmii_rx_clk, plus
the additional delay equal to the fixed delay specified on the IDELAY component.
Throughput
The GMII to RGMII core operates at full line rates of 10/100/1000 Mb/s.
Power
No information is currently provided for this core.
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