Panasonic Corporation
SanDisk Corporation
Toshiba Corporation
Revision History
Release of SD Simplified Specification
Conditions for publication
Publisher and Copyright Holder:
Notes:
Disclaimers:
Conventions Used in This Document
Naming Conventions
Numbers and Number Bases
Key Words
Application Notes
1. General Description
2. System Features
3. SD Memory Card System Concept
3.1 Read-Write Property
3.2 Supply Voltage
3.3 Card Capacity
3.3.1 User Area and Protected Area
3.3.2 Card Capacity Classification
3.4 Speed Class
3.5 Bus Topology
3.6 Bus Protocol
3.6.1 SD Bus Protocol
3.6.2 SPI Bus Protocol
3.6.3 UHS-II Bus Protocol
3.7 SD Memory Card–Pins and Registers
3.7.1 SD Bus Pin Assignment
3.7.2 UHS-II Pin Assignment
3.8 ROM Card
3.8.1 Register Setting Requirements
3.8.2 Unsupported Commands
3.8.3 Optional Commands
3.8.4 WP Switch
3.9 Ultra High Speed Phase I (UHS-I) Card
3.9.1 UHS-I Card Operation Modes
3.9.2 UHS-I Card Types
3.9.3 UHS-I Host and Card Combination
3.9.4 UHS-I Bus Speed Modes Selection Sequence
3.9.5 UHS-I System Block Diagram
3.9.6 Summary of Bus Speed Mode for UHS-I Card
3.10 Ultra High Speed Phase II (UHS-II) Card
3.10.1 UHS-II Card Operation Modes
3.10.2 UHS-II Card Type
3.10.3 UHS-II Host and Card Combination
3.10.4 UHS-II Interface Selection Sequence
3.10.5 Summary of Bus Speed Mode for UHS-II Card
4. SD Memory Card Functional Description
4.1 General
4.2 Card Identification Mode
4.2.1 Card Reset
4.2.2 Operating Condition Validation
4.2.3 Card Initialization and Identification Process
4.2.3.1 Initialization Command (ACMD41)
4.2.4 Bus Signal Voltage Switch Sequence
4.2.4.1 Initialization Sequence for UHS-I
4.2.4.2 Timing to Switch Signal Voltage
4.2.4.3 Timing of Voltage Switch Error Detection
4.2.4.4 Voltage Switch Command
4.2.4.5 Tuning Command
4.2.4.6 An Example of UHS-I System Block Diagram
4.3 Data Transfer Mode
4.3.1 Wide Bus Selection/Deselection
4.3.2 2 GByte Card
4.3.3 Data Read
4.3.4 Data Write
4.3.5 Erase
4.3.6 Write Protect Management
4.3.7 Card Lock/Unlock Operation
4.3.7.1 General
4.3.7.2 Parameter and the Result of CMD42
4.3.7.3 Forcing Erase
4.3.7.3.1 Force Erase Function to the Locked Card
4.3.7.4 Relation Between ACMD6 and Lock/Unlock State
4.3.7.5 Commands Accepted for Locked Card
4.3.7.6 Two Types of Lock/Unlock Card
4.3.8 Content Protection
4.3.9 Application-Specific Commands
4.3.9.1 Application-Specific Command – APP_CMD (CMD55)
4.3.9.2 General Command - GEN_CMD (CMD56)
4.3.10 Switch Function Command
4.3.10.1 General
4.3.10.2 Mode 0 Operation - Check Function
4.3.10.3 Mode 1 Operation - Set Function
4.3.10.4 Switch Function Status
4.3.10.4.1 Busy Status Indication for Functions
4.3.10.4.2 Data Structure Version
4.3.10.4.3 Function Table of Switch Command
4.3.10.5 Relationship between CMD6 Data and Other Commands
4.3.10.6 Switch Function Flow Example
4.3.10.7 Example of Checking
4.3.10.8 Example of Switching
4.3.11 High-Speed Mode (25 MB/sec interface speed)
4.3.12 Command System
4.3.13 Send Interface Condition Command (CMD8)
4.3.14 Command Functional Difference in Card Capacity Types
4.4 Clock Control
4.5 Cyclic Redundancy Code (CRC)
4.6 Error Conditions
4.6.1 CRC and Illegal Command
4.6.2 Read, Write and Erase Timeout Conditions
4.6.2.1 Read
4.6.2.2 Write
4.6.2.3 Erase
4.7 Commands
4.7.1 Command Types
4.7.2 Command Format
4.7.3 Command Classes
4.7.4 Detailed Command Description
4.7.5 Difference of SD Commands Definition in UHS-II
4.8 Card State Transition Table
4.9 Responses
4.9.1 R1 (normal response command):
4.9.2 R1b
4.9.3 R2 (CID, CSD register)
4.9.4 R3 (OCR register)
4.9.5 R6 (Published RCA response)
4.9.6 R7 (Card interface condition)
4.10 Two Status Information of SD Memory Card
4.10.1 Card Status
4.10.2 SD Status
4.11 Memory Array Partitioning
4.12 Timings
4.13 Speed Class Specification
4.13.1 Speed Class Specification for SDSC and SDHC
4.13.1.1 Allocation Unit (AU)
4.13.1.2 Recording Unit (RU)
4.13.1.3 Write Performance
4.13.1.4 Read Performance
4.13.1.5 Performance Curve Definition
4.13.1.6 Speed Class Definition
4.13.1.7 Consideration for Inserting FAT Update during Recording
4.13.1.7.1 Measurement Condition to determine Average TFw
4.13.1.7.2 Maximum FAT Write Time
4.13.1.8 Measurement Conditions and Requirements of the Speed Class
4.13.1.8.1 Measurement Conditions
4.13.1.8.2 Requirements of the Performance Parameters for Each Speed Class
4.13.1.8.3 Requirements of SD File System
4.13.1.9 CMD20 Support
4.13.2 Speed Class Specification for SDXC
4.13.2.1 Speed Class Parameters
4.13.2.1.1 AU
4.13.2.1.2 RU
4.13.2.2 Write Performance
4.13.2.2.1 Measurement of Pw
4.13.2.2.2 Performance Move
4.13.2.3 Read Performance
4.13.2.4 FAT Update
4.13.2.5 CI (Continuous Information) Update
4.13.2.6 Distinction of Data Type
4.13.2.7 Measurement Conditions and Requirements of the Speed Class for SDXC
4.13.2.7.1 Measurement Conditions
4.13.2.7.2 Requirements of the Performance Parameters for Each Speed Class
4.13.2.7.3 Requirements of SD File System
4.13.2.8 Speed Class Control Command (CMD20)
4.13.2.8.1 Definition of Each Function
4.13.2.8.2 Requirements for Speed Class Host
4.13.2.9 Example of Speed Class Recording Sequence
4.13.3 Speed Grade Specification for UHS-I and UHS-II
4.13.3.1 Speed Grade Parameters
4.13.3.1.1 UHS Speed Grade
4.13.3.1.2 AU (Allocation Unit)
4.13.3.1.3 RU (Recording Unit)
4.13.3.1.4 Pw (Write Performance)
4.13.3.1.5 Pm (Performance Move)
4.13.3.1.6 Pr and TFR(4KB) (Read Performance)
4.13.3.1.7 UHS-II Parameters
4.13.3.2 Support of Speed Class Control Command (CMD20)
4.13.3.3 Speed Grade Measurement Conditions
4.13.3.4 Notes for Preparation Time of UHS-I and UHS-II Card
4.13.3.5 Host Operating Frequency
4.14 Erase Timeout Calculation
4.14.1 Erase Unit
4.14.2 Case Analysis of Erase Time Characteristics
4.14.3 Method for Erase Large Areas
4.14.4 Calculation of Erase Timeout Value Using the Parameter Registers
4.15 Set Block Count Command
5. Card Registers
5.1 OCR register
5.2 CID register
5.3 CSD Register
5.3.1 CSD_STRUCTURE
5.3.2 CSD Register (CSD Version 1.0)
5.3.3 CSD Register (CSD Version 2.0)
5.4 RCA register
5.5 DSR register (Optional)
5.6 SCR register
5.7 Function Extension Specification
5.7.1 Extension Register Space
5.7.2 Extension Register Commands
5.7.2.1 Extension Register Read Command (Single Block)
5.7.2.2 Extension Register Write Command (Single Block)
5.7.2.3 Multiple Block Data Transfer
5.7.2.4 Extension Register Read Command (Multi-Block)
5.7.2.5 Extension Register Write Command (Multi-Block)
5.7.2.6 Error Status Indication
5.7.3 General Information
5.7.3.1 Common Header Fields
5.7.3.1.1 Structure Revision (2-byte)
5.7.3.1.2 General Information Length (2-byte)
5.7.3.1.3 Number of Extensions (1-byte)
5.7.3.2 Function Fields per Function
5.7.3.2.1 Standard Function Code (SFC 2-byte)
5.7.3.2.2 Function Capability Code (FCC 2-byte)
5.7.3.2.3 Function Manufacturer Code (FMC 2-byte)
5.7.3.2.4 Function Manufacturer Name (FMN 16-byte)
5.7.3.2.5 Particular Function Code (PFC 2-byte)
5.7.3.2.6 Function Name (FN 16-byte)
5.7.3.2.7 Pointer to Next Extension (2-byte)
5.7.3.2.8 Number of Register Sets (1-byte)
5.7.3.2.9 Extension Register Set Address (4-byte for each)
5.7.4 Revision Management
5.8 Application Specification on Function Extension
5.8.1 Power Management Function
5.8.1.1 Abstract of Power Management Function
(1) Features of Power Off Notification
(2) Features of Power Sustenance
(3) Features of Power Down Mode
5.8.1.2 Extension Register Set for Power Management
5.8.1.3 Power Off Notification
5.8.1.4 Power Sustenance
5.8.1.5 Power Down Mode
5.8.1.6 General Information of Power Management Function
6. SD Memory Card Hardware Interface
6.1 Hot Insertion and Removal
6.2 Card Detection (Insertion/Removal)
6.3 Power Protection (Insertion/Removal)
6.4 Power Scheme
6.4.1 Power Up Sequence for SD Bus Interface
6.4.1.1 Power Up Time of Card
6.4.1.2 Power Up Time of Host
6.4.1.3 Power On or Power Cycle
6.4.1.4 Power Supply Ramp Up
6.4.1.5 Power Down and Power Cycle
6.4.2 Power Up Sequence for UHS-II Interface
6.4.2.1 Power Up Sequence of UHS-II Card
6.4.2.2 Power Up Sequence of UHS-II Host
6.5 Programmable Card Output Driver (3.3V Single End) (Optional)
6.6 Bus Operating Conditions for 3.3V Signaling
6.7 Driver Strength and Bus Timing for 1.8V Signaling
6.8 Electrical Static Discharge (ESD) Requirement
7. SPI Mode
7.1 Introduction
7.2 SPI Bus Protocol
7.2.1 Mode Selection and Initialization
7.2.2 Bus Transfer Protection
7.2.3 Data Read
7.2.4 Data Write
7.2.5 Erase & Write Protect Management
7.2.6 Read CID/CSD Registers
7.2.7 Reset Sequence
7.2.8 Error Conditions
7.2.9 Memory Array Partitioning
7.2.10 Card Lock/Unlock
7.2.11 Application Specific Commands
7.2.12 Content Protection Command
7.2.13 Switch Function Command
7.2.14 High Speed Mode
7.2.15 Speed Class Specification
7.3 SPI Mode Transaction Packets
7.3.1 Command Tokens
7.3.1.1 Command Format
7.3.1.2 Command Classes
7.3.1.3 Detailed Command Description
7.3.1.4 Card Operation for CMD8 in SPI mode
7.3.2 Responses
7.3.2.1 Format R1
7.3.2.2 Format R1b
7.3.2.3 Format R2
7.3.2.4 Format R3
7.3.2.5 Formats R4 & R5
7.3.2.6 Format R7
7.3.3 Control Tokens
7.3.3.1 Data Response Token
7.3.3.2 Start Block Tokens and Stop Tran Token
7.3.3.3 Data Error Token
7.3.4 Clearing Status Bits
7.4 Card Registers
7.5 SPI Bus Timing Diagrams
7.6 SPI Electrical Interface
7.7 SPI Bus Operating Conditions
7.8 Bus Timing
8. Sections Effective to SD I/F Mode and UHS-II Mode
Appendix A (Normative) : Reference
A.1 Related Documentation
Appendix B (Normative) : Special Terms
B.1 Terminology
B.2 Abbreviations
Appendix C (Informative) : Examples for Fixed Delay UHS-I Host Design
Appendix D : UHS-I Tuning Procedure
Appendix E : Host Power Delivery Network (PDN) Design Guide
Appendix F : Application Notes of Extension Function
F.1 Identification of Function Driver