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VESA组织的DVI标准.pdf
Title Page
Acknowledgement
TOC
1. Introduction
1.1. Scope and Motivation
1.2. Performance Scalability
1.2.1. Bandwidth Estimation
1.2.2. Conversion to Selective Refresh
1.3. Related Documents
1.3.1. VESA Display Data Channel (DDC) Specification
1.3.2. VESA Extended Display Identification Data (EDID) Specification
1.3.3. VESA Video Signal Standard (VSIS) Specification
1.3.4. VESA Monitor Timing Specifications (DMT)
1.3.5. VESA Generalized Timing Formula Specification (GTF)
1.3.6. VESA Timing Definition for LCD Monitors Specification
1.3.7. Compatibility with Other T.M.D.S. Based Implementations.
2. Architectural Requirements
2.1. T.M.D.S. Overview
2.2. Plug and Play Specification
2.2.1. Overview
2.2.2. T.M.D.S. Link Usage Model
2.2.3. High Color Depth Support
2.2.4. Low Pixel Format Support
2.2.5. EDID
2.2.6. DDC
2.2.7. Gamma
2.2.8. Scaling
2.2.9. Hot Plugging
2.2.10. HSync, VSync and Data Enable Required
2.2.11. Data Formats
2.2.12. Interoperability with Other T.M.D.S. Based Specifications
2.3. Bandwidth
2.3.1. Minimum Frequency Supported
2.3.2. Alternate Media
2.4. Digital Monitor Power Management
2.4.1. Link Inactivity Definition
2.4.2. System Power Management Requirements
2.4.3. Monitor Power Management Requirements
2.5. Analog
2.5.1. Analog Signal Quality
2.5.2. HSync and VSync Required
2.5.3. Analog Timings
2.5.4. Analog Power Management
2.6. Signal List
3. T.M.D.S. Protocol Specification
3.1 Overview
3.1.1 Link Architecture
3.1.2 Clocking
3.1.3 Synchronization
3.1.4 Encoding
3.1.5 Dual-Link Architecture
3.2 Encoder Specification
3.2.1 Channel Mapping
3.2.2 Encode Algorithm
3.2.3 Serialization
3.3 Decoder Specification
3.3.1 Clock Recovery
3.3.2 Data Synchronization
3.3.3 Decode Algorithm
3.3.4 Channel Mapping
3.3.5 Error Handling
3.4 Link Timing Requirements
4. T.M.D.S. Electrical Specification
4.1. Overview
4.2. System Ratings and Operating Conditions
4.3. Transmitter Electrical Specifications
4.4. Receiver Electrical Specifications
4.5. Cable Assembly Specifications
4.6. Jitter Specifications
4.7. Electrical Measurement Procedures
4.7.1. Test Patterns
4.7.2. Normalized Amplitudes
4.7.3. Clock Recovery
4.7.4. Transmitter Rise/Fall Time
4.7.5. Transmitter Skew Measurement
4.7.6. Transmitter Eye
4.7.7. Jitter Measurement
4.7.8. Receiver Eye
4.7.9. Receiver Skew Measurement
4.7.10. Differential TDR Measurement Procedure
5. Physical Interconnect Specification
5.1. Overview
5.2. Mechanical Characteristics
5.2.1. Signal Pin Assignments
5.2.2. Contact Sequence
5.2.3. Digital-Only Receptacle Connectors
5.2.4. Combined Analog and Digital Receptacle Connectors
5.2.5. Digital Plug Connectors
5.2.6. Analog Plug Connectors
5.2.7. Recommended Panel Cutout
5.2.8. Mechanical Performance
5.3. Electrical Characteristics
5.3.1. Connector Electrical Performance
5.3.2. Cable Electrical Performance
5.4. Environmental Characteristics
5.5. Test Sequences
5.5.1. Group 1: Mated Environmental
5.5.2. Group II: Mated Mechanical
5.5.3. Group III: Mechanical Mate/Unmate Forces
5.5.4. Group IV: Insulator Integrity
5.5.5. Group V: Cable Flexing
5.5.6. Group VI: Electrostatic Discharge
Appendix A. Glossary of Terms
Appendix B. Contact Geometry
Appendix C. Digital Monitor Power States
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Digital Visual Interface
DVI
Revision 1.0
02 April 1999
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The Digital Display Working Group Promoters (“DDWG Promoters”) are Intel Corporation, Silicon Image, Inc.,
Compaq Computer Corporation, Fujitsu Limited, Hewlett-Packard Company, International Business
Machines Corporation, and NEC Corporation
THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY
WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR
PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR
SAMPLE.
The DDWG Promoters disclaim all liability, including liability for infringement of any proprietary rights, relating to use
of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
The DDWG Promoters may have patents and/or patent applications related to the Digital Visual Interface Specification.
The DDWG Promoters intend to make available to the industry an Adopter’s Agreement that will include a limited,
reciprocal, royalty-free license to the electrical interfaces, mechanical interfaces, signals, signaling and coding protocols,
and bus protocols described in, and required by, the Digital Visual Interface Specification Revision 1.0 finalized and
published by the DDWG Promoters. To encourage early adoption, Adopters will be required to return their executed
copy of the Adopter's Agreement during an “Adoption Period” which is within one year after the DVI Specification
Revision 1.0 is first published or within one year after the Adopter first sells products that comply with that
specification, whichever is later. This Adoption Period requirement will give parties ample time to understand the
benefits of becoming an Adopter and encourage them to remember this important step.
Copyright © DDWG Promoters 1999.
*Third-party brands and names are the property of their respective owners.
Acknowledgement
The DDWG acknowledges the concerted efforts of employees of Silicon Image, Inc.
and Molex Inc., who authored major portions of this specification. Both companies
have made a significant contribution by developing and licensing to the industry the
core technologies upon which this industry specification is based; transition
minimized differential signaling (T.M.D.S.) technology from Silicon Image, and
connector technology from Molex.
REVISION HISTORY
02 Apr 99 - 1.0 Initial Specification Release
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Digital Visual Interface
Revision 1.0
1.1.
1.2.
1.3.
2.
2.1.
2.2.
1.2.1.
1.2.2.
1.3.1.
1.3.2.
1.3.3.
1.3.4.
1.3.5.
1.3.6.
1.3.7.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.2.6.
2.2.7.
2.2.8.
2.2.9.
2.2.10.
2.2.11.
2.2.12.
Acknowledgement......................................................................................................2
REVISION HISTORY ...................................................................................................2
1.
Introduction................................................................................................ 5
Scope and Motivation .......................................................................................5
Performance Scalability ....................................................................................6
Bandwidth Estimation.................................................................................... 7
Conversion to Selective Refresh................................................................... 8
Related Documents ..........................................................................................8
VESA Display Data Channel (DDC) Specification ........................................ 8
VESA Extended Display Identification Data (EDID) Specification ................ 8
VESA Video Signal Standard (VSIS) Specification....................................... 8
VESA Monitor Timing Specifications (DMT) ................................................. 9
VESA Generalized Timing Formula Specification (GTF) .............................. 9
VESA Timing Definition for LCD Monitors Specification ............................... 9
Compatibility with Other T.M.D.S. Based Implementations. ......................... 9
Architectural Requirements...................................................................10
T.M.D.S. Overview ..........................................................................................10
Plug and Play Specification ............................................................................10
Overview...................................................................................................... 10
T.M.D.S. Link Usage Model ........................................................................ 11
High Color Depth Support ........................................................................... 13
Low Pixel Format Support ........................................................................... 14
EDID ............................................................................................................ 14
DDC............................................................................................................. 15
Gamma........................................................................................................ 15
Scaling......................................................................................................... 15
Hot Plugging................................................................................................ 16
HSync, VSync and Data Enable Required.................................................. 17
Data Formats............................................................................................... 18
Interoperability with Other T.M.D.S. Based Specifications ......................... 18
Bandwidth ....................................................................................................... 18
Minimum Frequency Supported .................................................................. 18
Alternate Media ........................................................................................... 19
Digital Monitor Power Management................................................................19
Link Inactivity Definition............................................................................... 21
System Power Management Requirements................................................ 21
Monitor Power Management Requirements................................................ 21
Analog.............................................................................................................22
Analog Signal Quality .................................................................................. 22
HSync and VSync Required........................................................................ 22
Analog Timings............................................................................................ 22
Analog Power Management ........................................................................ 23
Signal List........................................................................................................ 23
T.M.D.S. Protocol Specification............................................................. 24
Overview .........................................................................................................24
Link Architecture.......................................................................................... 24
Clocking....................................................................................................... 24
Synchronization........................................................................................... 25
Encoding...................................................................................................... 25
Dual-Link Architecture ................................................................................. 25
Encoder Specification .....................................................................................26
Channel Mapping ........................................................................................ 26
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2.1
3.
3.1
2.3.1.
2.3.2.
2.4.1.
2.4.2.
2.4.3.
2.5.1.
2.5.2.
2.5.3.
2.5.4.
2.6.
2.3.
2.4.
2.5.
3.2
Page 3 of 76
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3.3
4.
3.4
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
3.2.2
3.2.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Encode Algorithm........................................................................................28
Serialization.................................................................................................30
Decoder Specification .....................................................................................30
Clock Recovery............................................................................................30
Data Synchronization...................................................................................30
Decode Algorithm........................................................................................31
Channel Mapping.........................................................................................31
Error Handling..............................................................................................31
Link Timing Requirements ..............................................................................32
T.M.D.S. Electrical Specification............................................................33
Overview..........................................................................................................33
System Ratings and Operating Conditions .....................................................35
Transmitter Electrical Specifications ...............................................................35
Receiver Electrical Specifications ...................................................................38
Cable Assembly Specifications .......................................................................39
Jitter Specifications .........................................................................................39
Electrical Measurement Procedures ...............................................................40
Test Patterns...............................................................................................40
4.7.1.
4.7.2. Normalized Amplitudes................................................................................40
4.7.3. Clock Recovery............................................................................................40
Transmitter Rise/Fall Time...........................................................................41
4.7.4.
4.7.5.
Transmitter Skew Measurement..................................................................41
Transmitter Eye...........................................................................................41
4.7.6.
4.7.7.
Jitter Measurement......................................................................................42
4.7.8. Receiver Eye...............................................................................................42
4.7.9. Receiver Skew Measurement......................................................................42
4.7.10. Differential TDR Measurement Procedure..................................................42
Physical Interconnect Specification......................................................43
Overview..........................................................................................................43
Mechanical Characteristics .............................................................................43
5.2.1. Signal Pin Assignments...............................................................................43
5.2.2. Contact Sequence.......................................................................................44
5.2.3. Digital-Only Receptacle Connectors............................................................45
5.2.4. Combined Analog and Digital Receptacle Connectors...............................46
5.2.5. Digital Plug Connectors...............................................................................47
5.2.6. Analog Plug Connectors..............................................................................47
5.2.7. Recommended Panel Cutout......................................................................48
5.2.8. Mechanical Performance.............................................................................49
Electrical Characteristics.................................................................................50
5.3.1. Connector Electrical Performance...............................................................50
5.3.2. Cable Electrical Performance......................................................................52
Environmental Characteristics ........................................................................53
Test Sequences ..............................................................................................54
5.5.1. Group 1: Mated Environmental....................................................................54
5.5.2. Group II: Mated Mechanical........................................................................55
5.5.3. Group III: Mechanical Mate/Unmate Forces................................................56
5.5.4. Group IV: Insulator Integrity.........................................................................57
5.5.5. Group V: Cable Flexing...............................................................................58
5.5.6. Group VI: Electrostatic Discharge...............................................................58
Appendix A. Glossary of Terms ............................................................................59
Appendix B. Contact Geometry ........................................................................61
Appendix C. Digital Monitor Power State - State Diagram..............................76
5.
5.1.
5.2.
5.3.
5.4.
5.5.
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1. Introduction
The Digital Visual Interface (hereinafter DVI) specification provides a high-speed digital
connection for visual data types that is display technology independent. The interface is
primarily focused at providing a connection between a computer and its display device. The
DVI specification meets the needs of all segments of the PC industry (workstation, desktop,
laptop, etc) and will enable these different segments to unite around one monitor interface
specification.
The DVI interface enables:
1. Content to remain in the lossless digital domain from creation to consumption
2. Display technology independence
3. Plug and play through hot plug detection, EDID and DDC2B
4. Digital and Analog support in a single connector
This interface specification is organized as follows:
Chapter 1 provides motivation, scope, and direction of the specification.
Chapter 2 provides a technical overview and the specific system and display architectural
and programming requirements that must be met in order to create an inter-operable
context for the DVI interface.
Chapter 3 provides a detailed description of the transition minimized differential
signaling (hereinafter T.M.D.S.) protocol and encoding algorithm.
Chapter 4 provides a detailed description of the electrical requirements of T.M.D.S..
Chapter 5 contains the connector mechanical description and the electrical characteristics
of the connector, including signal placement.
Appendix A is a glossary.
Appendix B details the connector contact geometry
Appendix C enlarged digital monitor power state diagram
1.1. Scope and Motivation
The purpose of this interface specification is to provide an industry specification for a digital
interface between a personal computing device and a display device. This specification
provides for a simple low-cost implementation on both the host and monitor while allowing
for monitor manufacturers and system providers to add feature rich values as appropriate for
their specific application.
The DDWG has worked to address the various business models and requirements of the
industry by delivering a transition methodology that addresses the needs of those various
requirements. This is accomplished by specifying two connectors with identical mechanical
characteristics: one that is digital only and one that is digital and analog. The combined
digital and analog connector is designed to meet the needs of systems with special form factor
or performance requirements. Having support for the analog and digital interfaces for the
computer to monitor interconnect will allow the end user to simply plug the display into the
DVI connector regardless of the display technology.
The digital only DVI connector is designed to coexist with the standard VGA connector.
With the combined connector or the digital only connector the opportunity exists for the
removal of the legacy VGA connector. The removal of the legacy VGA connector is
anticipated to be driven strictly by business demands.
A digital interface for the computer to monitor interconnect has several benefits over the
standard VGA connector. A digital interface ensures all content transferred over this interface
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remains in the lossless digital domain from creation to consumption. The digital interface is
developed with no assumption made as to the attached display technology.
This specification completely describes the interface so that one could implement a complete
transmission and interconnect solution or any portion of the interface. The T.M.D.S. protocol
and associated electrical signaling as developed by Silicon Image is described in detail. The
mechanical specification of the connector and the signal placement within the connector are
described.
A device that is compliant with this specification is should be interoperable with other
compliant devices through the plug and play configuration and implementation provided for
in this specification. The plug and play interface provides for hot plug detection and monitor
feature detection. Additionally, this specification describes the number of T.M.D.S. links
available to the display device and the method for configuring the T.M.D.S. links.
The bandwidth and pixel formats that are anticipated and supported by this specification are
described. This specification describes the signal quality characteristics required by the cable
to support the high data rates required by large pixel format displays. Additionally the DVI
specification provides for alternate media implementations. Power management and plug and
play configuration management are both fully described. To ensure baseline functionality,
low-pixel format requirements are included.
As appropriate, this interface makes use of existing VESA specifications to allow for simple
low-cost implementations. Specifically VESA Extended Display Identification Data (EDID)
and Display Data Channel (DDC) specifications are referenced for monitor identification and
the VESA Monitor Timing Specification (DMT) is referenced for the monitor timings.
1.2. Performance Scalability
The amount of raw bandwidth that is required to support a display type is technology specific.
For example a typical CRT allocates a blanking interval time. This blanking interval
requirement is technology specific and forces the data transfer to occur in a limited time slot.
This limited time slot increases the bandwidth requirement of the data active window while
mandating long data inactive time periods to allow for the blanking to complete. A blanking
period is display technology specific and should not be forced on all display types. Reduced
blanking periods provide more of the actual interconnect bandwidth to the display device. It
is anticipated that display technology will continue to advance such that blanking period
overheads will be decreased and will eventually be eliminated thus providing the maximum
bandwidth of the interface to the display device. As displays advance even beyond the
capabilities of the copper physical layer it is anticipated display interfaces will migrate toward
providing only changed data to the display. This limited update architecture is an expectation
only, not a requirement.
3DJHRI
Digital Visual Interface
Revision 1.0
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Pixel Bandwidth [MPix/sec]
60 Hz LCD
5% blanking
60 Hz CRT
GTF blanking
75 Hz CRT
GTF blanking
85 Hz CRT
GTF blanking
Legend:
Proposed Spec
Future Architecture
VGA (640x480)
SVGA (800x600)
XGA (1024x768)
SXGA (1280x1024)
UXGA (1600x1200)
HDTV (1920x1080)
QXGA (2048x1536)
Figure 1-1. Available Link Bandwidth
Figure 1-1. Available Link Bandwidth. represents the raw bandwidth available from each
T.M.D.S. link. The three horizontal axes across the bottom of the figure represent the
different overhead requirements of the various display technologies. To determine the
number of links required for a specific application simply use the legend on the right to select
the pixel format, then find the pixel format on the horizontal axis that represents the display
technology of interest. Once the pixel format has been identified draw a vertical line to
intersect the T.M.D.S. bandwidth curve, this is the bandwidth required for the pixel format
and display technology selected.
1.2.1. Bandwidth Estimation
The bandwidth that is required over a physical medium is easy to estimate. Data required as
input are Horizontal Pixels, Vertical Pixels, Refresh Frequency (Hz), Bandwidth Overhead
(loosely defined as blanking). An equation to quickly estimate the bandwidth required is:
+
1
%
Overhead
100
=œ
Pixels
Second
#
Horizontal
Pixels
#
VerticalPi
xels
Rate
Equation 1-1. Pixels per Second.
Where overhead is defined as
Overhead
=
Blanking
1
Blanking
Equation 1-2. Overhead.
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Digital Visual Interface
Revision 1.0
To measure the link bandwidth in pixels per second assumes each of the three channels is
transmitting an R-pel, G-pel, and B-pel data in unison.
A pel is a pixel element, i.e. the singular red value or green value or blue value of an RGB
pixel. Pixels per second can be converted to bits per second by multiplying the pixels per
second value by the number of bits per pixel. Using Equation 1-1 and the T.M.D.S. signaling
protocol, pixels per second equals the T.M.D.S. clock link frequency.
1.2.2. Conversion to Selective Refresh
It is anticipated that in the future the refreshing of the screen will become a function of the
monitor. Only when data has changed will the data be sent to the monitor. A monitor would
have to employ an addressable memory space to enable this feature. With a selective refresh
interface, the high refresh rates required to keep a monitor ergonomically pleasing can be
maintained while not requiring an artificially high data rate between the graphics controller
and the monitor. The DVI specification does nothing to preclude this potential migration.
1.3. Related Documents
The DVI specification references other VESA specifications to enable low cost
implementations. Additionally, the DVI specification references the VESA specifications to
help enable plug and play interoperability.
1.3.1. VESA Display Data Channel (DDC) Specification
This specification incorporates a subset of the Display Data Channel for operation between a
DDC compliant host and DDC compliant monitor. The DDC level support required in this
specification is DDC2B. Compatibility with earlier DDC versions is not supported. It is
anticipated that the DVI specification will require support for the Enhanced-DDC
specification within 12 months of VESA adoption. Refer to VESA DDC Specification
Version 3.0 for more information.
1.3.2. VESA Extended Display Identification Data (EDID) Specification
Both DVI compliant systems and monitors must support the EDID data structure. EDID 1.2
and 2.0 are recommended for interim support for systems. Complete requirements are
detailed in section 2.2.5. The system is required to read the EDID data structure to determine
the capabilities supported by the monitor. It is anticipated that the DVI specification will
require support for the EDID 1.3 data structure support within 12 months of VESA adoption.
Refer to VESA EDID Specification Version 3.0 for more information.
1.3.3. VESA Video Signal Standard (VSIS) Specification
Systems implementing the analog portion of the DVI specification must be in compliance
with the VESA VSIS specification within 12 months of VESA adoption. Refer to VESA
VSIS Specification Version 1.6p for more information.
Page 8 of 76
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