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SSD2858 内部版规格书,Datasheet.pdf
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD2858
Product Preview
Dual MIPI DSI Tx for WQXGA
with Frame Buffer
This document contains information on a product under development. Solomon Systech reserves the right to change
or discontinue this product without notice.
http://www.solomon-systech.com
SSD2858
Rev 0.10
P 1/214
Aug 2013
Copyright © 2013 Solomon Systech Limited
Version
0.10
Appendix 1: IC Revision history of SSD2858 Specification
1st Release 09-Aug-13
Change Items
Effective Date
SSD2858
Rev 0.10
P 2/214
Aug 2013
Solomon Systech
CONTENTS
1 DEVICE OVERVIEW............................................................................................................... 10
INTRODUCTION................................................................................................................................................................10
FEATURES........................................................................................................................................................................10
OVERVIEW.......................................................................................................................................................................11
DESCRIPTION...................................................................................................................................................................12
MIPI DSI RX (MIPIRX)..............................................................................................................................................12
Video Timing Control Module (VTCM) ......................................................................................................................12
Video Compression Unit (VCU) .................................................................................................................................12
MIPI DSI TX (MIPITX) ..............................................................................................................................................12
Clock Controller, Oscillator, and Phase Locked Loop (SCM) ...................................................................................12
OTP Controller (OTPC) .............................................................................................................................................13
Charge Pump ..............................................................................................................................................................13
2 SYSTEM MAP ........................................................................................................................... 14
INTRODUCTION................................................................................................................................................................14
MEMORY MAP.................................................................................................................................................................15
COMMAND RETRANSMISSION (SPECIAL GENERIC PACKET WITH PARAMETER 0 = 0XFF)................................................15
TEST MODES ...................................................................................................................................................................16
3 PACKAGE AND PIN DESCRIPTION.................................................................................... 17
INTRODUCTION................................................................................................................................................................17
PIN FUNCTION .................................................................................................................................................................17
SSD2858QL9 PIN ASSIGNMENT .....................................................................................................................................20
PIN ASSIGNMENT TABLE .................................................................................................................................................21
DIMENSION FOR SSD2858...............................................................................................................................................23
MARKING FOR SSD2858 .................................................................................................................................................24
4 POWER MANAGEMENT........................................................................................................ 25
INTRODUCTION................................................................................................................................................................25
POWER UP SEQUENCE......................................................................................................................................................26
RESET SEQUENCE ............................................................................................................................................................27
POWER DOWN SEQUENCE ................................................................................................................................................27
5 SYSTEM CONTROL MODULE (SCM)................................................................................. 28
FEATURES........................................................................................................................................................................28
PROGRAMMING MODEL...................................................................................................................................................29
REGISTER DESCRIPTION.......................................................................................................................................30
1.1
SCM Control Register.................................................................................................................................................30
SCM PLL Register ......................................................................................................................................................31
SCM Clock Control Register ......................................................................................................................................33
SCM Miscellaneous Control 1 Register......................................................................................................................34
SCM Miscellaneous Control 2 Register......................................................................................................................35
SCM OTP Control Register ........................................................................................................................................37
SCM MIPIRX PHY Control Register..........................................................................................................................38
SCM Analog Control 1 Register .................................................................................................................................39
SCM Analog Control 2 Register .................................................................................................................................42
SCM Scratch Register.................................................................................................................................................43
SCM GAP1 Register ...................................................................................................................................................44
SCM GAP2 Register ...................................................................................................................................................45
6 MIPI DSI RX (MIPIRX) ........................................................................................................... 46
FEATURES........................................................................................................................................................................46
REFERENCES....................................................................................................................................................................46
DEFINITIONS....................................................................................................................................................................46
ARCHITECTURE ...............................................................................................................................................................47
Overview.....................................................................................................................................................................47
SSD2858
Rev 0.10
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Aug 2013
Solomon Systech
DETAILED DESCRIPTION..................................................................................................................................................48
D-PHY controller........................................................................................................................................................48
Parallel Interface........................................................................................................................................................48
Protocol Control Unit (PCU) .....................................................................................................................................48
Packet Processing Unit (PPU) ...................................................................................................................................49
Error Correction Code/ Cyclic Redundancy Check (ECC/CRC) ...............................................................................49
Analog Transceiver.....................................................................................................................................................49
PROGRAMMING MODEL...................................................................................................................................................50
REGISTER DESCRIPTION.......................................................................................................................................51
1.2
Configuration Control Register ..................................................................................................................................51
Delay Configuration Register.....................................................................................................................................52
HS RX Timer Register.................................................................................................................................................53
LP TX Timer Register .................................................................................................................................................54
SOT Count Register ....................................................................................................................................................55
Phy Error Register......................................................................................................................................................56
Analog Control Register 1 ..........................................................................................................................................58
Analog Control Register 2 ..........................................................................................................................................59
Initialization Register .................................................................................................................................................60
Power Cut Register.....................................................................................................................................................61
DSI Error Register......................................................................................................................................................62
Error Count Register ..................................................................................................................................................64
OPERATING MODES.........................................................................................................................................................65
End of Transmission (EOT) ........................................................................................................................................65
Contention Detection and Timer.................................................................................................................................65
Error Report ...............................................................................................................................................................66
D-PHY operation ........................................................................................................................................................66
Data Bit Operation .....................................................................................................................................................67
7 VIDEO TIMING CONTROL MODULE (VTCM) ................................................................ 70
PROGRAMMING MODEL...................................................................................................................................................71
REGISTER DESCRIPTION ..................................................................................................................................................73
DCS Command Support............................................................................................................................................109
Qualcomm Compression Command Support............................................................................................................110
OPERATING MODES.......................................................................................................................................................115
Tearing......................................................................................................................................................................115
Address Mode ...........................................................................................................................................................118
Rotation 90o ..............................................................................................................................................................119
Partial Display..........................................................................................................................................................120
HSCA ........................................................................................................................................................................121
VSCA.........................................................................................................................................................................122
VPPHD Scaling Algorithm .......................................................................................................................................124
VPPHD Cubic Interpolation.....................................................................................................................................126
8 VIDEO COMPRESSION UNIT (VCU)................................................................................. 127
PROGRAMMING MODEL.................................................................................................................................................127
REGISTER DESCRIPTION ................................................................................................................................................128
VCU Device Identification Register..........................................................................................................................128
VCU Capabilities Register........................................................................................................................................129
VCU Horizontal Display Configuration Register.....................................................................................................130
VCU Qualcomm FBC Control Register....................................................................................................................131
VCU Qualcomm FBC Size Register..........................................................................................................................133
VCU Qualcomm FBC Configuration Register..........................................................................................................134
VCU Qualcomm FBC Control 2 Register.................................................................................................................136
VCU Qualcomm FBC Control 3 Register.................................................................................................................137
VCU Qualcomm FBC Status Register ......................................................................................................................138
9 GENERAL PURPOSE I/O (GPIO)........................................................................................ 139
REFERENCES................................................................................................................................ 139
SSD2858
Rev 0.10
P 4/214
Aug 2013
Solomon Systech
INTRODUCTION..............................................................................................................................................................139
FEATURES......................................................................................................................................................................139
ARCHITECTURE .............................................................................................................................................................140
Overview...................................................................................................................................................................140
PROGRAMMING MODEL.................................................................................................................................................141
Register Description .................................................................................................................................................144
10 MIPI DSI TX (MIPITX) ...................................................................................................... 163
FEATURES......................................................................................................................................................................163
REFERENCES..................................................................................................................................................................163
DEFINITIONS..................................................................................................................................................................163
DETAILED DESCRIPTIONS ..............................................................................................................................................164
Multiple DSI Output (Video and Command) ............................................................................................................164
PROGRAMMING MODEL.................................................................................................................................................165
REGISTER DESCRIPTIONS...............................................................................................................................................166
Device Identification Register...................................................................................................................................166
Capability Register ...................................................................................................................................................167
Control Register........................................................................................................................................................168
Video Timing Control 1 Register ..............................................................................................................................170
Video Timing Control 2 Register ..............................................................................................................................172
Video Configuration Register ...................................................................................................................................173
Trimming Control Register.......................................................................................................................................176
Watermark Register ..................................................................................................................................................177
Partition Register......................................................................................................................................................178
HS Transmit Timer Register .....................................................................................................................................179
LP Receive Timer Register........................................................................................................................................180
Delay Adjustment 1 Register.....................................................................................................................................181
Delay Adjustment 2 Register.....................................................................................................................................182
Delay Adjustment 3 Register.....................................................................................................................................183
Analog Control Register ...........................................................................................................................................184
Video Bist 1 Register.................................................................................................................................................186
Video Bist 2 Register.................................................................................................................................................187
DSIn Control Register(where n = 0 to 2) .................................................................................................................188
DSIn Video Register..................................................................................................................................................191
DSIn Ack Resp Register ............................................................................................................................................192
DSIn Status Register .................................................................................................................................................193
DSIn Delay Control 1 Register .................................................................................................................................195
DSIn Delay Control 2 Register .................................................................................................................................196
11 OTP CONTROLLER (OTPC) ............................................................................................ 197
DETAILED DESCRIPTIONS ..............................................................................................................................................197
Memory Organization...............................................................................................................................................197
OTPC State Diagram................................................................................................................................................198
Timing Diagram of on-chip E-fuse ...........................................................................................................................199
PROGRAMMING MODEL.................................................................................................................................................201
REGISTER DESCRIPTION ................................................................................................................................................202
APB Registers ...........................................................................................................................................................202
OPERATING MODES.......................................................................................................................................................208
OTP Program ...........................................................................................................................................................208
OTP Manual Read Initialization...............................................................................................................................208
OTP Manual Read ....................................................................................................................................................208
12 ELECTRICAL CHARACTERISTICS .............................................................................. 209
MAXIMUM RATINGS................................................................................................................................................209
RECOMMENDED OPERATING CONDITIONS.......................................................................................................210
DC CHARACTERISTICS ..................................................................................................................................................211
13 AC CHARACTERISTICS................................................................................................... 212
RESET TIMING .............................................................................................................................................................213
SSD2858
Rev 0.10
P 5/214
Aug 2013
Solomon Systech
TABLES
TABLE 2-1: REGISTER ACCESS GENERIC LONG PACKET......................................................................................................14
TABLE 2-2: SYSTEM MEMORY MAP ....................................................................................................................................15
TABLE 2-3: MODE SETTING MAP.........................................................................................................................................16
TABLE 3-1: PIN DESCRIPTION..............................................................................................................................................17
TABLE 3-2: PIN ASSIGNMENT...............................................................................................................................................21
TABLE 5–1: SCM REGISTER SUMMARY ..............................................................................................................................29
TABLE 5-2: SCM CONTROL DESCRIPTION...........................................................................................................................30
TABLE 5-3: SCM PLL REGISTER DESCRIPTION...................................................................................................................31
TABLE 5-4: SCM CLOCK CONTROL REGISTER DESCRIPTION ..............................................................................................33
TABLE 5-5: SCM MISCELLANEOUS CONTROL 1 REGISTER DESCRIPTION............................................................................34
TABLE 5-6: SCM MISCELLANEOUS CONTROL 2 DESCRIPTION............................................................................................35
TABLE 5-7: SCM OTP CONTROL REGISTER DESCRIPTION..................................................................................................37
TABLE 5-8: SCM MIPIRX PHY CONTROL REGISTER DESCRIPTION...................................................................................38
TABLE 5-9: SCM ANALOG CONTROL 1 REGISTER DESCRIPTION.........................................................................................39
TABLE 5-10: SCM ANALOG CONTROL 1 REGISTER DESCRIPTION.......................................................................................42
TABLE 5-11: SCM SCRATCH 0 REGISTER DESCRIPTION......................................................................................................43
TABLE 5-12: SCM GAP1 REGISTER DESCRIPTION..............................................................................................................44
TABLE 5-13: SCM GAP2 REGISTER DESCRIPTION..............................................................................................................45
TABLE 6-1: CONFIGURATION CONTROL REGISTER DESCRIPTION ........................................................................................51
TABLE 6-2: DELAY CONFIGURATION REGISTER DESCRIPTION ............................................................................................52
TABLE 6-3: HS RX TIMER REGISTER DESCRIPTION ............................................................................................................53
TABLE 6-4: LP TX TIMER REGISTER DESCRIPTION .............................................................................................................54
TABLE 6-5: SOT COUNT REGISTER DESCRIPTION ...............................................................................................................55
TABLE 6-6: PHY ERROR REGISTER DESCRIPTION ................................................................................................................56
TABLE 6-7: ANALOG CONTROL REGISTER 1 DESCRIPTION..................................................................................................58
TABLE 6-8: ANALOG CONTROL REGISTER 2 DESCRIPTION..................................................................................................59
TABLE 6-9: INITIALIZATION REGISTER DESCRIPTION ..........................................................................................................60
TABLE 6-10: POWER CUT REGISTER DESCRIPTION..............................................................................................................61
TABLE 6-11: DSI ERROR REGISTER DESCRIPTION...............................................................................................................62
TABLE 6-12: ERROR COUNT REGISTER DESCRIPTION..........................................................................................................64
TABLE 7–1: VTCM REGISTER SUMMARY ...........................................................................................................................71
TABLE 7-2: VTCM DEVICE IDENTIFICATION REGISTER DESCRIPTION ................................................................................73
TABLE 7-3: VTCM CAPABILITIES REGISTER DESCRIPTION.................................................................................................74
TABLE 7-4: VTCM CONTROL REGISTER DESCRIPTION .......................................................................................................76
TABLE 7-5: VTCM CONFIGURATION REGISTER DESCRIPTION ............................................................................................77
TABLE 7-6: VTCM PIXEL CLOCK FREQUENCY RATIO REGISTER DESCRIPTION..................................................................79
TABLE 7-7: VTCM DISPLAY HORIZONTAL CONFIGURATION REGISTER DESCRIPTION .......................................................80
TABLE 7-8: VTCM VERTICAL DISPLAY CONFIGURATION REGISTER DESCRIPTION ............................................................81
TABLE 7-9: VTCM MEMORY SIZE REGISTER DESCRIPTION................................................................................................82
TABLE 7-10: VTCM DISPLAY SIZE REGISTER DESCRIPTION...............................................................................................83
TABLE 7-11: VTCM PANEL SIZE REGISTER DESCRIPTION ..................................................................................................84
TABLE 7-12: VTCM IDLE FRAME & URAM CONFIGURATION REGISTER DESCRIPTION .....................................................85
TABLE 7-13: VTCM IDLE FRAME COUNT REGISTER DESCRIPTION.....................................................................................87
TABLE 7-14: VTCM URAM CONTROL REGISTER DESCRIPTION ........................................................................................88
TABLE 7-15: VTCM PANEL OFFSET START REGISTER DESCRIPTION..................................................................................89
TABLE 7-16: VTCM PANEL OFFSET END REGISTER DESCRIPTION .....................................................................................90
TABLE 7-17: VTCM IMAGE SIZE REGISTER DESCRIPTION ..................................................................................................91
TABLE 7-18: VTCM VERTICAL SCALER CONTROL 1 REGISTER DESCRIPTION....................................................................92
TABLE 7-19: VTCM VERTICAL SCALER CONTROL 2 REGISTER DESCRIPTION....................................................................93
TABLE 7-20: VTCM VERTICAL SCALER LOW REGISTER DESCRIPTION ......................................................................94
TABLE 7-21: VTCM VERTICAL SCALER HIGH REGISTER DESCRIPTION......................................................................95
TABLE 7-22: VTCM HORIZONTAL SCALER CONTROL 1 REGISTER DESCRIPTION ...............................................................96
TABLE 7-23: VTCM HORIZONTAL SCALER CONTROL 2 REGISTER DESCRIPTION ...............................................................97
TABLE 7-24: VTCM HORIZONTAL SCALER LOW REGISTER DESCRIPTION..................................................................98
TABLE 7-25: VTCM HORIZONTAL SCALER HIGH REGISTER DESCRIPTION.................................................................99
TABLE 7-26: VTCM QUALCOMM FBC CONTROL REGISTER DESCRIPTION.......................................................................100
TABLE 7-27: VTCM QUALCOMM FBC SIZE REGISTER DESCRIPTION ...............................................................................102
TABLE 7-28: VTCM QUALCOMM FBC CONFIGURATION REGISTER DESCRIPTION............................................................103
TABLE 7-29: VTCM QUALCOMM FBC CONTROL 2 REGISTER DESCRIPTION....................................................................105
SSD2858
Solomon Systech
Rev 0.10
P 6/214
Aug 2013
TABLE 7-30: VTCM QUALCOMM FBC CONTROL 3 REGISTER DESCRIPTION....................................................................106
TABLE 7-31: VTCM QUALCOMM FBC STATUS REGISTER DESCRIPTION..........................................................................107
TABLE 7-32: VTCM TEST REGISTER DESCRIPTION...........................................................................................................108
TABLE 7-33: BITPLANE FOR CAPABILITY EXCHANGE.........................................................................................................110
TABLE 7-34: BITPLANE FOR PROFILE ID BYTE..................................................................................................................111
TABLE 7-35: DSI VIDEO MODE PACKET FORMATS ...........................................................................................................113
TABLE 7–36: HSCA CONFIGURATION PARAMETERS.........................................................................................................121
TABLE 7–37: VSCA CONFIGURATION PARAMETERS.........................................................................................................122
TABLE 7–38: SCALING TERMS...........................................................................................................................................125
TABLE 7–39: LUT ORGANIZATION....................................................................................................................................126
TABLE 7–40: LUT PROGRAMMING VIEW ..........................................................................................................................126
TABLE 8–1: VCU APB REGISTER SUMMARY....................................................................................................................127
TABLE 8-2: VCU DEVICE IDENTIFICATION REGISTER DESCRIPTION .................................................................................128
TABLE 8-3: VCU CAPABILITIES REGISTER DESCRIPTION..................................................................................................129
TABLE 8-4: VCU DISPLAY HORIZONTAL CONFIGURATION REGISTER DESCRIPTION.........................................................130
TABLE 8-5: VCU QUALCOMM FBC CONTROL REGISTER DESCRIPTION............................................................................131
TABLE 8-6: VCU QUALCOMM FBC SIZE REGISTER DESCRIPTION ....................................................................................133
TABLE 8-7: VCU QUALCOMM FBC CONFIGURATION REGISTER DESCRIPTION.................................................................134
TABLE 8-8: VCU QUALCOMM FBC CONTROL 2 REGISTER DESCRIPTION.........................................................................136
TABLE 8-9: VCU QUALCOMM FBC CONTROL 3 REGISTER DESCRIPTION.........................................................................137
TABLE 8-10: VCU QUALCOMM FBC STATUS REGISTER DESCRIPTION.............................................................................138
TABLE 9-1: GPIO REGISTER SUMMARY ............................................................................................................................141
TABLE 9-2: GPIO DEVICE IDENTIFICATION REGISTER DESCRIPTION ................................................................................144
TABLE 9-3: GPIO CAPABILITIES REGISTER DESCRIPTION .................................................................................................145
TABLE 9-4: GPIO CONTROL REGISTER DESCRIPTION .......................................................................................................146
TABLE 9-5: GPIO FUNCTION REGISTER DESCRIPTION ......................................................................................................147
TABLE 9-6: GPIO MODE REGISTER DESCRIPTION.............................................................................................................148
TABLE 9-7: GPIO PULL REGISTER DESCRIPTION...............................................................................................................149
TABLE 9-8: GPIO DATA DIRECTION REGISTER DESCRIPTION ...........................................................................................150
TABLE 9-9: GPIO OUTPUT SOURCE SELECT REGISTER 1 DESCRIPTION ............................................................................151
TABLE 9-10: GPIO OUTPUT SOURCE SELECT REGISTER 2 DESCRIPTION ..........................................................................152
TABLE 9-11: GPIO INPUT CONFIGURATION A REGISTER 1 DESCRIPTION .........................................................................153
TABLE 9-12: GPIO INPUT SOURCE SELECT A REGISTER 2 DESCRIPTION ..........................................................................154
TABLE 9-13: GPIO INPUT SOURCE SELECT B REGISTER 1 DESCRIPTION ..........................................................................155
TABLE 9-14: GPIO INPUT SOURCE SELECT B REGISTER 2 DESCRIPTION ..........................................................................156
TABLE 9-15: GPIO DATA REGISTER DESCRIPTION............................................................................................................157
TABLE 9-16: GPIO INTERRUPT CONFIGURATION REGISTER 1 DESCRIPTION.....................................................................158
TABLE 9-17: GPIO INTERRUPT CONFIGURATION REGISTER 2 DESCRIPTION.....................................................................159
TABLE 9-18: GPIO INTERRUPT ENABLE REGISTER DESCRIPTION .....................................................................................160
TABLE 9-19: GPIO INTERRUPT STATUS REGISTER DESCRIPTION......................................................................................161
TABLE 9-20: GPIO INTERRUPT ENABLE REGISTER DESCRIPTION .....................................................................................162
TABLE 10-1: DSITX REGISTER SUMMARY.......................................................................................................................165
TABLE 10-2: DEVICE IDENTIFICATION REGISTER DESCRIPTION ........................................................................................166
TABLE 10-3: CAPABILITY REGISTER DESCRIPTION............................................................................................................167
TABLE 10-4: CONTROL REGISTER DESCRIPTION ...............................................................................................................168
TABLE 10-5: VIDEO TIMING CONTROL 1 REGISTER DESCRIPTION.....................................................................................170
TABLE 10-6: VIDEO TIMING CONTROL 2 REGISTER DESCRIPTION.....................................................................................172
TABLE 10-7: VIDEO CONFIGURATION REGISTER DESCRIPTION .........................................................................................173
TABLE 10-8: TRIMMING CONTROL REGISTER DESCRIPTION..............................................................................................176
TABLE 10-9: WATERMARK REGISTER DESCRIPTION .........................................................................................................177
TABLE 10-10: PARTITION REGISTER DESCRIPTION............................................................................................................178
TABLE 10-11: HS TRANSMIT TIMER REGISTER DESCRIPTION ...........................................................................................179
TABLE 10-12: LP RECEIVE TIMER REGISTER DESCRIPTION ..............................................................................................180
TABLE 10-13: DELAY ADJUSTMENT 1 REGISTER DESCRIPTION.........................................................................................181
TABLE 10-14: DELAY ADJUSTMENT 2 REGISTER DESCRIPTION.........................................................................................182
TABLE 10-15: DELAY ADJUSTMENT 3 REGISTER DESCRIPTION.........................................................................................183
TABLE 10-16: ANALOG CONTROL REGISTER DESCRIPTION...............................................................................................184
TABLE 10-17: VIDEO BIST 1 REGISTER DESCRIPTION........................................................................................................186
TABLE 10-18: VIDEO BIST 2 REGISTER DESCRIPTION........................................................................................................187
TABLE 10-19: DSIN CONTROL REGISTER DESCRIPTION....................................................................................................188
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Solomon Systech
TABLE 10-20: DSIN VIDEO REGISTER DESCRIPTION .........................................................................................................191
TABLE 10-21: DSIN ACK RESP REGISTER DESCRIPTION ...................................................................................................192
TABLE 10-22: DSIN STATUS REGISTER DESCRIPTION .......................................................................................................193
TABLE 10-23: DSIN DELAY CONTROL 1 REGISTER DESCRIPTION .....................................................................................195
TABLE 10-24: DSIN DELAY CONTROL 2 REGISTER DESCRIPTION .....................................................................................196
TABLE 11–1: OTP APB REGISTER SUMMARY...................................................................................................................201
TABLE 11-2: VTCM DEVICE IDENTIFICATION REGISTER DESCRIPTION ............................................................................202
TABLE 11-3: OTPC CONFIGURATION REGISTER DESCRIPTION .........................................................................................203
TABLE 11-4: OTPC CONTROL REGISTER DESCRIPTION ....................................................................................................204
TABLE 11-5: OTPC PROGRAM REGISTER DESCRIPTION....................................................................................................205
TABLE 11-6: OTPC READ DATA REGISTER DESCRIPTION.................................................................................................206
TABLE 11-7: OTPC STATUS REGISTER DESCRIPTION........................................................................................................207
TABLE 12-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS).................................................................................209
TABLE 12-2: RECOMMENDED OPERATING CONDITIONS....................................................................................................210
TABLE 12-3: DC CHARACTERISTICS..................................................................................................................................211
TABLE 13-1: RESET TIMING.............................................................................................................................................213
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Aug 2013
Solomon Systech
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