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AURIXTC3XX_ts_part1_V2.5.1.pdf
About this document
Table of Contents
1 Introduction
1.1 About this Document
1.1.1 Related Documentations
1.1.2 Text Conventions
1.1.3 Family Specification and Appendix
1.1.4 Register and Memory Address Documentation
1.1.5 Reserved, Undefined, and Unimplemented Terminology
1.1.6 Register Access Modes
1.1.7 Register Reset Documentation
1.1.8 Abbreviations and Acronyms
1.2 System Architecture of the AURIX™ TC3xx Platform
1.2.1 AURIX™ TC3xx Platform High End – TC39xED
1.2.1.1 TC39xED Lead Product (A-step device only)
1.2.2 AURIX™ TC3xx Platform - Family Overview
1.2.2.1 TC38x Block Diagram
1.2.2.2 TC37xED Block Diagram
1.2.2.3 TC37x Block Diagram
1.2.2.4 TC36x Block Diagram
1.2.2.5 TC35x Block Diagram
1.2.2.6 TC33xED Block Diagram
1.2.2.7 TC33x Block Diagram
1.2.3 Variants
1.2.3.1 Encoding of the Product Name
1.2.3.2 TC32x
1.2.3.3 TC39xPD
1.2.4 Revision History
1.3 Emulation Device (ED)
1.3.1 Block Diagram
1.3.2 Feature List
1.3.3 Comparison to AURIX Emulation Devices
1.3.4 Trace Source Multiplexer
1.3.4.1 TMUX Setting Options
1.3.4.2 Trace Source Multiplexer in CPU Subsystem (TCMUX)
1.3.4.3 Parallel Trace Use Cases
1.3.5 DAP ED Interface (DAPE)
1.3.6 Revision History
1.4 Software over the Air (SOTA)
1.4.1 Overview
1.4.2 Functional Description
1.4.2.1 Performance considerations
1.4.2.2 Configuring for SOTA
1.4.2.2.1 Configuration parameters
1.4.2.2.2 Initial device configuration for SOTA
1.4.2.2.3 Runtime SWAP configuration
1.4.3 Safety
1.4.4 Security
1.4.5 Revision History
2 Memory Maps (MEMMAP)
2.1 Feature List
2.2 Overview
2.3 Functional Description
2.3.1 Segments
2.3.2 Address Map of the On Chip Bus System
2.3.2.1 Segments 0 to 14
2.3.2.2 Segment 15
2.3.3 Memory Accesses
2.4 Revision History
3 AURIX™ TC3xx Platform Firmware
3.1 Functional description
3.1.1 Startup Software
3.1.1.1 Events triggering SSW execution
3.1.1.1.1 Cold (initial) power-on reset
3.1.1.1.2 System reset
3.1.1.1.3 Application reset
3.1.1.2 Clock system during start-up
3.1.1.3 RAM overwrite during start-up
3.1.1.4 Stand-by controller handling during start-up
3.1.1.5 Boot Options Summary
3.1.1.6 Boot Mode evaluation sequence
3.1.1.6.1 Evaluation of Boot Mode Headers
3.1.1.6.2 Alternate Boot Mode evaluation
3.1.1.6.3 Processing in case no valid BMHD found
3.1.1.6.4 Processing in case no Boot Mode configured by SSW
3.1.1.7 Startup Software Main Flow
3.1.1.7.1 Flash ramp-up
3.1.1.7.2 Device Configuration
3.1.1.7.3 RAM Initialization
3.1.1.7.4 Select and execute Startup Modes
3.1.1.7.5 LBIST execution
3.1.1.7.6 Lockstep configuration
3.1.1.7.7 Debug System handling
3.1.1.7.8 ESR0 pin handling
3.1.1.7.9 Ending the SSW and Starting the User Code
3.1.2 Checker Software
3.1.2.1 CHSW execution flow
3.1.2.2 Checks performed by CHSW and exit information
3.1.2.3 Checker Software exit information for ALL CHECKS PASSED
3.1.3 Bootstrap Loaders
3.1.3.1 ASC Bootstrap loader
3.1.3.2 CAN Bootstrap loader
3.1.3.2.1 CAN BSL summary
3.1.3.2.2 Clock system during CAN BSL
3.1.3.2.3 CAN BSL usage after application reset
3.1.3.2.4 Supported CAN features
3.1.3.2.5 CAN BSL flow
3.1.4 Support for Software over the Air (SOTA)
3.1.5 Shutdown request handler
3.1.6 Power Supply Friendly Debug Monitor
3.2 Registers
3.2.1 Firmware specific usage of device registers
3.2.1.1 Registers providing information on the boot selections
3.2.1.2 Registers providing information on the Checker Software activity
3.3 Revision History
4 On-Chip System Connectivity {and Bridges}
4.1 Feature List
4.1.1 What is new in the SRI Fabric
4.2 Overview
4.3 Functional Description
4.3.1 Operational Overview
4.3.1.1 Master Connection Interface (MCI)
4.3.1.2 Slave Connection Interface (SCI)
4.3.1.3 Slave Arbiter
4.3.1.4 Default Slave
4.3.1.5 OnLine Data Acquisition (OLDA)
4.3.1.6 Control and Status Register Access Protection
4.3.2 Arbitration Details
4.3.2.1 Master Request Arbitration
4.3.3 SRI Errors
4.3.3.1 SRI Protocol Errors
4.3.3.2 SRI Transaction ID Errors
4.3.3.3 SRI EDC Errors
4.3.3.4 Error Handling
4.3.3.5 Error Tracking Capability
4.3.3.6 Indication Event Interactions
4.3.3.7 Releasing the lock from registers ERR and ERRADD
4.3.4 Implementation of the SRI Fabric
4.3.4.1 Mapping of SRI Masters to Domain 0 Master Interfaces
4.3.4.2 Mapping of SRI Slaves to Domain 0 Slave Interfaces
4.3.4.3 Mapping of SRI Masters to Domain 1 Master Interfaces
4.3.4.4 Mapping of SRI Slaves to Domain 1 Slave Interfaces
4.3.4.5 Mapping of SRI Masters to Domain 2 Master Interfaces
4.3.4.6 Mapping of SRI Slaves to Domain 2 Slave Interfaces
4.4 Registers
4.4.1 Domain Common Registers
4.4.2 SCI Control Registers
4.5 S2S Bridge
4.5.1 EDC Errors
4.5.2 Protocol Errors
4.5.3 Transaction ID Errors
4.5.4 Transaction Errors for Writes via S2S Bridge
4.6 SFI_F2S Bridge
4.6.1 Functional Overview
4.7 SFI_S2F Bridge
4.7.1 Functional Overview
4.8 Resource Access Times
4.9 Revision History
4.10 FPI Interconnect
4.10.1 Feature List
4.10.1.1 Delta to TC2xx
4.10.2 Overview
4.10.2.1 Bus Transaction Types
4.10.2.2 Reaction of a Busy Slave
4.10.2.3 Address Alignment Rules
4.10.2.4 FPI Bus Basic Operations
4.10.3 Functional Description (SBCU, EBCU)
4.10.3.1 FPI Bus Arbitration
4.10.3.1.1 Arbitration on the System Peripheral Bus
4.10.3.1.2 Default Master
4.10.3.1.3 Arbitration Algorithms
4.10.3.2 FPI Bus Error Handling
4.10.4 FPI Bus Integrity Support
4.10.4.1 Safety Support
4.10.4.2 FPI EDC Overview
4.10.4.3 Error Injection
4.10.4.4 SPB: Mapping of ALARM signals to SBCU_ALSTATx and SBCU_ALCLRx registers
4.10.4.5 BBB: Mapping of ALARM signals to EBCU_ALSTATx and EBCU_ALCLRx registers
4.10.5 Debug
4.10.5.1 Address Trigger
4.10.5.2 Signal Status Trigger
4.10.5.3 Grant Trigger
4.10.5.4 Combination of Trigger Events
4.10.5.5 BCU Breakpoint Generation Examples
4.10.6 Registers
4.10.6.1 Registers Description
4.10.6.2 System Registers
4.10.6.3 Register Access Protection (ACCEN1/0)
4.10.6.4 Kernel Reset Registers (KRST1/0, KRSTCLR)
4.10.6.5 Clock Control Register (CLC)
4.10.6.6 OCDS Control and Status Register (OCS)
4.10.7 On Chip Bus Master TAG Assignments
4.10.8 Revision History
5 CPU Subsystem
5.1 Feature List
5.2 Overview
5.2.1 CPU Diagram
5.2.2 Instruction Fetch Unit
5.2.3 Execution Unit
5.2.4 General Purpose Register File
5.3 Functional Description
5.3.1 Summary of functional changes from AURIX
5.3.2 Summary of changes from TC39x A-Step
5.3.3 AURIXTM Family CPU configurations
5.3.4 CPU Implementation-Specific Features
5.3.4.1 Context Save Areas / Context Operations
5.3.4.2 Program Counter (PC) Register
5.3.4.3 Store Buffers
5.3.4.4 Interrupt System
5.3.4.5 Trap System
5.3.4.6 WAIT Instruction
5.3.4.7 Invalid Opcode
5.3.4.8 Speculation extent
5.3.4.9 Instruction Memory Range Limitations
5.3.4.10 Atomicity of Data Accesses
5.3.4.11 A11 usage
5.3.4.12 Independent Core Kernel Reset
5.3.4.12.1 Kernel Reset Registers
5.3.4.13 CPU Clock Control
5.3.4.14 CPU Core Special Function Registers (CSFR)
5.3.4.14.1 Registers
5.3.4.15 CPU General Purpose Registers
5.3.4.16 FPU Registers
5.3.4.17 CPU Memory Protection Registers
5.3.4.18 Temporal Protection Registers
5.3.4.19 Exception Timer
5.3.4.19.1 Exception Timers Registers
5.3.4.20 Memory Integrity Registers
5.3.4.20.1 Register Descriptions
5.3.4.21 CPU Core Debug and Performance Counter Registers
5.3.4.21.1 Counter Source Details
5.3.4.22 CPU Subsystem Register Summary
5.3.4.22.1 Summary of CSFR Reset Values and Access Modes
5.3.4.22.2 Summary of SFR Reset Values and Access modes
5.3.5 CPU Instruction Timing
5.3.5.1 Integer-Pipeline Instructions
5.3.5.1.1 Simple Arithmetic Instruction Timings
5.3.5.1.2 Multiply Instruction Timings
5.3.5.1.3 Multiply Accumulate (MAC) Instruction Timing
5.3.5.1.4 Control Flow Instruction Timing
5.3.5.2 Load-Store Pipeline Instructions
5.3.5.2.1 Address Arithmetic Timing
5.3.5.2.2 CSA Control Flow Instruction Timing
5.3.5.2.3 Load Instruction Timing
5.3.5.2.4 Store Instruction Timing
5.3.5.3 Floating Point Pipeline Timing
5.3.6 Local Memory Details
5.3.6.1 Memory Addressing
5.3.6.1.1 Local and Global Addressing
5.3.6.1.2 CSFR and SFR base Locations
5.3.6.1.3 Cache Memory Access
5.3.6.1.4 Customer-ID Numbering
5.3.6.2 Memory Integrity Error Handling
5.3.6.2.1 Program Side Memories
5.3.6.2.2 Data Side Memories
5.3.6.2.3 Memory Initialisation
5.3.6.3 Program Memory Interface (PMI)
5.3.6.3.1 TC1.6.2P PMI Description
5.3.6.3.2 PMI Registers
5.3.6.4 Data Memory Interface (DMI)
5.3.6.4.1 DMI Description
5.3.6.4.2 Distributed LMU (DLMU)
5.3.6.4.3 DMI Trap Generation
5.3.6.4.4 DMI Registers
5.3.7 Miscellaneous
5.3.7.1 Boot Halt
5.3.7.2 SSH usage recommendations
5.3.7.3 Debug restrictions
5.3.7.4 Local Pflash Bank Configuration Registers
5.3.7.4.1 Registers
5.3.8 Lockstep Comparator Logic (LCL)
5.3.8.1 Feature List
5.3.8.2 Lockstep Control
5.3.8.3 Lockstep Monitoring
5.3.8.4 Lockstep Self Test
5.3.8.5 Lockstep Failure Signalling Test
5.3.8.6 Functional Redundancy
5.3.9 Data Access Overlay (OVC)
5.3.9.1 Data Access Redirection
5.3.9.2 Target Memories
5.3.9.2.1 Online Data Acquisition (OLDA) Space
5.3.9.3 Overlay Memories
5.3.9.3.1 Local Memory
5.3.9.3.2 External Memory
5.3.9.3.3 DSPR & PSPR Memory
5.3.9.4 Global Overlay Control
5.3.9.4.1 Global Overlay Control Synchronisation
5.3.9.5 Overlay Configuration Change
5.3.9.6 Access Protection, Attributes, Concurrent Matches
5.3.9.7 Overlay Control Registers
5.3.9.7.1 Block control registers
5.3.9.8 Global overlay control registers
5.3.10 CPU Architecture registers
5.4 Safety Measures
5.4.1 SRI Bus Master Address Phase Error Injection
5.4.2 SRI Bus Master Write Phase Error Injection
5.4.3 SRI bus Slave Read Phase Error Injection
5.4.4 SRI Error Capture
5.4.5 SRI Safe Data Master tag
5.4.6 Safety Protection System
5.4.6.1 Bus MPU
5.4.6.2 Register Access Enable Protection
5.4.7 Registers Implementing Safety Features
5.4.7.1 SRI safety registers
5.4.7.2 Safety Protection registers
5.5 IO Interfaces
5.6 Revision History
6 Non Volatile Memory (NVM) Subsystem
6.1 Overview
6.2 Functional Description
6.2.1 Definition of Terms
6.2.2 Major changes from Aurix to AURIXTC3XX
6.2.3 Flash Structure
6.2.3.1 Program Flash Banks
6.2.3.1.1 PFLASH Tuning Protection (TP) and HSM Support
6.2.3.1.2 Erase Counters
6.2.3.2 EEPROM Emulation with DFLASH
6.2.3.2.1 DFLASH Emulation Modes
6.2.3.2.2 Robust EEPROM Emulation
6.2.3.3 Data Flash Bank DFLASH0
6.2.3.4 Data Flash Bank DFLASH1
6.2.4 Program Flash (PFLASH) Features
6.2.5 Data Flash (DFLASH) Features
6.2.6 Boot ROM (BROM) Features
6.3 Safety Measures
6.3.1 Safety Endinit protection
6.3.2 Access Control
6.3.3 Data Reliability and Integrity
6.3.3.1 PFLASH ECC
6.3.3.2 DFLASH ECC
6.3.4 Integrity of PFlash read data wait cycles
6.3.5 Alarms
6.3.5.1 SRI Access Address Phase Error
6.3.5.2 SRI Access Write Data Phase Error
6.4 Revision History
6.5 Data Memory Unit (DMU)
6.5.1 Overview
6.5.2 Functional Description
6.5.2.1 Flash Read Access
6.5.2.1.1 Transaction Types
6.5.2.1.2 Configuring Flash Read Access Cycles
6.5.2.2 Flash Operations
6.5.2.2.1 Page Mode
6.5.2.2.2 Command Sequences
6.5.2.2.3 Command Sequence Definitions
6.5.2.2.4 Protection for Verify Command Sequences
6.5.2.2.5 DMU Commands
6.5.2.2.6 Suspend and Resume Operations
6.5.2.2.7 Programming Voltage Selection
6.5.2.2.8 Performing Flash Operations
6.5.2.3 Traps
6.5.2.4 Interrupts
6.5.2.4.1 Host Command Interface
6.5.2.4.2 HSM Command Interface
6.5.2.5 Error Handling
6.5.2.5.1 Handling Errors During Startup
6.5.2.5.2 Handling Errors During Operation
6.5.2.6 DMU Modes
6.5.2.6.1 Operation Mode
6.5.2.6.2 Error Mode
6.5.2.6.3 Power modes
6.5.2.7 Internal Connections
6.5.2.7.1 Clocks
6.5.2.7.2 Interrupts and Service Requests
6.5.2.7.3 Cross Triggers
6.5.2.8 Power Modes
6.5.2.8.1 Flash Prefetch Buffers
6.5.2.8.2 Demand Mode
6.5.2.8.3 Dynamic Idle Mode
6.5.2.8.4 Sleep Mode
6.5.2.8.5 Cranking Mode
6.5.2.8.6 Standby Mode
6.5.2.9 Boot ROM (BROM)
6.5.2.9.1 Read Accesses
6.5.2.9.2 Data Integrity
6.5.3 Registers
6.5.3.1 Flash ID and BootROM Registers (PMU)
6.5.3.1.1 PMU Identification
6.5.3.2 DMU Registers
6.5.3.2.1 DMU Identification
6.5.3.2.2 Host Command Interface
6.5.3.2.3 Flash Error Registers
6.5.3.2.4 Data Flash Bank 0 ECC Registers
6.5.3.2.5 Data Flash Bank 0 Mode Control Registers
6.5.3.2.6 Power Mode Registers
6.5.3.2.7 PFLASH Protection Configuration
6.5.3.2.8 Tuning Protection Configuration
6.5.3.2.9 DFLASH Protection Configuration
6.5.3.2.10 Suspend
6.5.3.2.11 Margin Check Control
6.5.3.2.12 Access Protection Registers
6.5.3.2.13 Protection Configuration
6.5.3.2.14 HSM Command Interface
6.5.3.2.15 HSM Flash Error Registers
6.5.3.2.16 Data Flash Bank 1 ECC Registers
6.5.3.2.17 Data Flash Bank 1 Mode Control Registers
6.5.3.2.18 HSM Suspend
6.5.3.2.19 Margin Check Control
6.5.3.2.20 HSM OTP Protection Configuration
6.5.3.2.21 HSM Interface Protection Configuration
6.5.4 Security
6.5.4.1 Effective Flash Read Protection
6.5.4.1.1 PFLASH Read Protection
6.5.4.1.2 DFLASH Read Protection
6.5.4.2 Effective Flash Write Protection
6.5.4.2.1 PFLASH Write Protection
6.5.4.2.2 DFLASH Write Protection
6.5.4.3 Configuring Protection in the UCB
6.5.4.3.1 UCB Confirmation
6.5.4.3.2 UCB_BMHDx_ORIG and UCB_BMHDx_COPY (x = 0-3)
6.5.4.3.3 UCB_SSW
6.5.4.3.4 UCB_USER
6.5.4.3.5 UCB_TEST
6.5.4.3.6 UCB_HSMCFG
6.5.4.3.7 UCB_REDSEC
6.5.4.3.8 UCB_PFLASH_ORIG and UCB_PFLASH_COPY
6.5.4.3.9 UCB_DFLASH_ORIG and UCB_DFLASH_COPY
6.5.4.3.10 UCB_DBG_ORIG and UCB_DBG_COPY
6.5.4.3.11 UCB_HSM_ORIG and UCB_HSM_COPY
6.5.4.3.12 UCB_HSMCOTP0/1_ORIG and UCB_HSMCOTP0/1_COPY
6.5.4.3.13 UCB_ECPRIO_ORIG and UCB_ECPRIO_COPY
6.5.4.3.14 UCB_SWAP_ORIG and UCB_SWAP_COPY
6.5.4.3.15 UCB_OTPy_ORIG and UCB_OTPy_COPY (y = 0-7)
6.5.4.3.16 Spare UCB
6.5.4.4 System Wide Effects of Flash Protection
6.5.4.4.1 HSM Booting
6.5.4.4.2 Destructive Debug Entry
6.5.5 Revision History
6.6 Program Flash Interface (PFI)
6.6.1 Overview
6.6.2 Functional Description
6.6.2.1 Demand Path
6.6.2.2 Data Read Line Buffer (DRLB)
6.6.2.3 Flash Prefetch Buffer (FPB)
6.6.3 Erase Counter and Register Accesses
6.6.3.1 Erase Counter
6.6.3.2 User Registers
6.6.4 Safety Measures
6.6.4.1 Access Enable
6.6.4.2 ECC encoding of read data to CPU
6.6.4.3 ECC error detection of wait cycle configuration from DMU
6.6.4.4 PFI Partial Lockstep (PPL)
6.6.4.5 Busy checker
6.6.5 Revision History
6.7 Non Volatile Memory (NVM)
6.7.1 Overview
6.7.2 Functional Desription of the Flash Standard Interface (FSI)
6.7.2.1 FSI ROM
6.7.2.2 FSI SFR
6.7.2.2.1 FSI SFR Access Control
6.7.2.3 Communication with FSI
6.7.2.3.1 DMU Command Sequences
6.7.3 Registers
6.7.3.1 FSI Registers
6.7.3.1.1 Status register
6.7.3.2 PFRWB (PFI) Registers
6.7.3.2.1 PFI ECC Registers
6.7.3.2.2 PFI Corrected Single Bits Address Buffer (SBAB)
6.7.3.2.3 PFI Corrected Double Bits Address Buffer (DBAB)
6.7.3.2.4 PFI Uncorrected Multi Bits Address Buffer (MBAB)
6.7.3.2.5 PFI Uncorrected All Zeros Bits Address Buffer (ZBAB)
6.7.4 Revision History
6.8 User Configuration Block (UCB)
6.8.1 Overview
6.8.2 UCB Address Map
6.8.2.1 List of Defined UCBs
6.8.2.2 UCB_BMHDx_ORIG and UCB_BMHDx_COPY (x = 0 - 3)
6.8.2.3 UCB_SSW
6.8.2.4 UCB_USER
6.8.2.5 UCB_RETEST
6.8.2.6 UCB_PFLASH_ORIG and UCB_PFLASH_COPY
6.8.2.7 UCB_DFLASH_ORIG and UCB_DFLASH_COPY
6.8.2.8 UCB_DBG_ORIG and UCB_DBG_COPY
6.8.2.9 UCB_HSM_ORIG and UCB_HSM_COPY
6.8.2.10 UCB_HSMCOTP0/1_ORIG and UCB_HSMCOTP0/1_COPY
6.8.2.11 UCB_ECPRIO_ORIG and UCB_ECPRIO_COPY
6.8.2.12 UCB_SWAP_ORIG and UCB_SWAP_COPY
6.8.2.13 UCB_OTPy_ORIG and UCB_OTPy_COPY (y = 0 - 7)
6.8.2.14 UCB_REDSEC
6.8.3 UCB Entries
6.8.3.1 UCB_USER
6.8.3.2 UCB_SWAP_ORIG and UCB_SWAP_COPY
6.8.3.3 UCB_REDSEC
6.8.4 Revision History
7 Local Memory Unit (LMU)
7.1 Feature List
7.2 Functional Description
7.2.1 Local Memory (LMU SRAM)
7.2.2 Memory Protection
7.2.3 LMU Register Protection
7.2.4 Error Detection and Signalling
7.2.4.1 SRI access address phase error
7.2.4.2 SRI write access data phase error
7.2.4.3 Uncorrected ECC Error
7.2.4.4 SRAM Data Correction ECC failure
7.2.4.5 Internal Data Transfer ECC Error
7.2.4.6 Access Protection Violation
7.2.4.7 Internal SRAM Read Error
7.2.4.8 Control Logic Failure
7.2.5 SRAM Data Correction ECC failure
7.2.6 Internal Data Transfer ECC Error
7.2.7 Internal SRAM Read Error
7.2.8 Clock Control
7.3 LMURegisters
7.4 IO Interfaces
7.5 Revision History
8 On-Chip Debug Support (OCDS)
8.1 Introduction
8.2 Functional Description
8.2.1 OCDS System Components
8.2.2 OCDS System Control Unit (OSCU)
8.2.2.1 OCDS Enabling
8.2.2.2 OCDS Reset Concept
8.2.2.3 Halt After Reset
8.2.2.4 Watchdog Timer Control
8.2.2.5 System Security
8.2.2.6 System Safety Aspects
8.2.3 OCDS Trigger Switch (OTGS)
8.2.3.1 Introduction
8.2.3.2 Trigger Line Properties
8.2.3.3 Trigger Line Signal Processing (TLSP)
8.2.3.4 Trigger Pins
8.2.3.5 Trigger to Host (TRIG) Support
8.2.3.6 Processor Core Signals
8.2.3.7 Suspend Generation
8.2.4 OCDS Trigger Mux (OTGM)
8.2.4.1 Introduction
8.2.4.2 OCDS Trigger Bus (OTGB)
8.2.4.3 Single Signal Interface (SSI)
8.2.4.4 IRQ MUX
8.2.4.5 Interrupt System Trace
8.2.4.6 MCDS I/F
8.2.5 Trigger to Host (TRIG)
8.2.5.1 Introduction
8.2.5.2 Watch Point Integration
8.2.6 Injector for Faults and Stress (IFS)
8.2.6.1 Fault Injection
8.2.6.2 Stress Injection
8.2.6.3 Operation
8.2.7 IOClient
8.2.7.1 IO Client Operation Modes
8.2.7.2 IO Client Instructions
8.2.7.3 Shift Core Protocol
8.2.7.4 Configurable Minimum Busy Time (CMBT)
8.2.7.5 Read/Write Mode (RW Mode)
8.2.7.6 Communication Mode (COM Mode)
8.2.7.7 Triggered Transfers
8.2.7.8 Internal Mode
8.2.7.8.1 Internal Communication Mode (Monitor Mode)
8.2.7.8.2 Internally Controlled Triggered Transfer Mode
8.2.7.9 Error Handling
8.2.7.10 Reset Behavior
8.2.8 Tool Interface Options
8.2.8.1 Tool Interface Overview and Enabling
8.2.8.1.1 Comparison of DAP, DXCPL and DXCM
8.2.8.1.2 Enabling of JTAG, DAP, DXCPL or DXCM
8.2.8.2 DAP, JTAG and Trigger Pins
8.2.8.3 DAP over CAN Physical Layer (DXCPL)
8.2.8.3.1 Enabling and Pins
8.2.8.3.2 SPD Parameters
8.2.8.3.3 Halt After Reset Request (HARR)
8.2.8.4 SPD Protocol Overview
8.2.8.5 DAP over CAN Messages (DXCM)
8.2.8.5.1 Introduction
8.2.8.5.2 Operational Overview
8.2.8.6 User Interfaces
8.2.8.7 Device Access Server (DAS)
8.2.9 Device Access Port (DAP)
8.2.9.1 DAP Protocol Versions
8.2.9.1.1 Deprecated features in AURIX TC3xx
8.2.9.1.2 Changes from AURIX to AURIX TC3xx
8.2.9.1.3 Changes from AUDO MAX to AURIX
8.2.9.2 Basic Interface Modes
8.2.9.2.1 DAP Module Reset
8.2.9.2.2 Locked Mode
8.2.9.2.3 Enabled Mode
8.2.9.2.4 Active Mode
8.2.9.2.5 JTAG Mode (DAP Bypass)
8.2.9.3 Detailed Startup Behavior
8.2.9.3.1 Startup without Tool Access
8.2.9.3.2 Startup for Tool Access
8.2.9.4 Robust Tool Behavior
8.2.9.4.1 DAP Attach Sequence
8.2.9.4.2 Recovery from any Error State
8.2.9.4.3 Hot Attach of a Tool
8.2.9.5 DAP Protocol
8.2.9.6 DAP Modes and Options
8.2.9.6.1 Wide Mode (WM)
8.2.9.6.2 DAP over LVDS
8.2.9.6.3 Reply with CRC6 (RC6)
8.2.9.6.4 Trigger in Protocol (TGIP)
8.2.9.7 DAP Control Registers
8.2.9.7.1 DAPISC Initialization, Status and Control Register
8.2.9.8 DAP Telegram Format
8.2.9.8.1 Telegrams from Tool to Device
8.2.9.8.2 Telegrams from Device to Tool
8.2.9.8.3 Checksum Algorithm
8.2.9.8.4 Block CRC
8.2.9.9 DAP Telegram Catalog
8.2.9.9.1 dapisc - DAP initialization, status and control
8.2.9.9.2 sync - request synchronization pattern
8.2.9.9.3 turn_off - shut down DAP or switch to JTAG
8.2.9.9.4 poll - get the current service request
8.2.9.9.5 get_CRCdown
8.2.9.9.6 get_CRCup
8.2.9.9.7 jtag_reset - reset the TAP controller
8.2.9.9.8 jtag_setIR - write the TAP’s INSTRUCTION register
8.2.9.9.9 jtag_setDR - write the current JTAG data register
8.2.9.9.10 jtag_swapDR - write and read the current JTAG data register
8.2.9.9.11 jtag_moreDR - write and read part of a long JTAG data register
8.2.9.9.12 client_set - define the current IOClient
8.2.9.9.13 client_reset - reset the current IOClient
8.2.9.9.14 client_read - read from the current IOClient
8.2.9.9.15 client_blockread - read from the current IOClient
8.2.9.9.16 client_write - write to the current IOClient
8.2.9.9.17 client_blockwrite - write multiple words to current client
8.2.9.9.18 client_readwrite - combined read/write current client
8.2.9.9.19 ssc_reset - reset the SSCM logic
8.2.9.9.20 ssc_shift - shift data through the Single Scan Chain
8.2.9.9.21 ssc_capture - sample the logic into the Single Scan Chain
8.2.9.10 Request/reply structure in block transfers
8.2.9.10.1 Client_read telegram with IO_BLOCKREAD instruction
8.2.9.10.2 Client_blockread telegram
8.2.9.10.3 Client_blockwrite telegram
8.2.9.11 IO Interfaces
8.2.9.12 Revision History DAP
8.2.10 JTAG Interface
8.2.10.1 JTAG Basics
8.2.10.2 Programmer’s Model
8.2.10.3 Boundary Scan
8.2.10.3.1 Initialization of Boundary-Scan
8.2.10.3.2 Assignment of Pin Functions to Boundary-Scan Bits
8.2.10.4 Single Scan Chain Mode (SSCM)
8.2.10.5 IO Interfaces
8.2.10.6 Revision History JTAG
8.2.11 Cerberus Bus Interfaces
8.2.11.1 Master Interface (MIF)
8.2.11.2 Slave Interface (SIF)
8.3 Registers
8.3.1 Address Map
8.3.2 BPI Registers
8.3.2.1 ACCEN Registers
8.3.3 OSCU Registers
8.3.3.1 OCDS System Control Unit Status Register
8.3.3.2 OCDS Enable Control
8.3.3.3 OCDS System Control Unit Control Register
8.3.3.4 OCDS Interface Mode Control
8.3.3.5 Module Identification Register
8.3.3.6 JTAG Device Identification Register
8.3.4 TRIG Registers
8.3.4.1 Trigger To Host Register
8.3.4.2 Set Trigger To Host Register
8.3.4.3 Read and Clear Trigger To Host Register
8.3.5 IFS Registers
8.3.5.1 IFS Control Register
8.3.5.2 IFS Address Register
8.3.6 OTGS Registers
8.3.6.1 Trigger Line State and Control
8.3.6.2 Suspend Generation with Capture and Hold
8.3.6.3 Trigger Status and Capture
8.3.6.4 Trigger Routing for CPUs
8.3.6.5 Trigger Pins Control
8.3.6.6 Trigger Routing for OTGB0/1
8.3.6.7 Trigger Routing for MCDS
8.3.6.8 Trigger Routing for Special Signals
8.3.7 OTGM Registers
8.3.8 IOClient Registers
8.3.8.1 IOClient Configuration Register
8.3.8.2 IOClient Status and Control Register
8.3.8.3 IOClient Info and Error Status Register
8.3.8.4 IOClient System Control Register
8.3.8.5 IOClient Read/Write Address Register
8.3.8.6 IOClient Read/Write Data Register
8.3.8.7 Communication Mode Data Register
8.3.8.8 Triggered Transfer Destination Address Register
8.3.8.9 Client Type Identification Register
8.3.8.10 Internal Mode Registers
8.3.9 JTAG only Registers
8.3.9.1 JTAG Instruction Register
8.3.9.2 JTAG Device Identification Register
8.3.9.3 JTAG Bypass Register
8.3.9.4 JTAG IOClient Selection Register
8.4 Use Cases
8.4.1 OSCU Use Cases
8.4.1.1 Hot Attach
8.4.1.2 Halt after PORST
8.4.1.3 Halt after PORST with DAP
8.4.1.4 Halt after Reset
8.4.1.5 Key Exchange
8.4.2 IOClient Use Cases
8.4.2.1 Failed Read
8.4.2.2 Write Block
8.4.2.3 Simple Trace
8.4.2.4 Triggered Transfer
8.4.2.5 Debug Monitor
8.4.2.6 No-wire Debug
8.4.3 OTGS Use Cases
8.4.3.1 Routing the CPUs HALT State to IOINFO
8.4.3.2 Synchronous Start and Stop
8.4.3.3 Time-Stepping on System Level
8.4.3.4 Single-Stepping on System Level
8.4.3.5 Generating Interrupts
8.4.3.6 Counting Events and Measuring Times
8.4.4 OTGM Use Cases
8.4.4.1 Detecting Missed Interrupt Requests
8.4.4.2 Measuring Interrupt Response Times
8.4.5 TRIG Use Cases
8.4.5.1 Data Logging
8.4.5.2 Rapid Prototyping (External Bypass)
8.5 JTAG IDs
8.6 IO Interfaces
8.7 Revision History
8.8 Changes from AURIX and TC39x A-Step
8.8.1 Changes from AURIX in TC39x A-Step
8.8.1.1 OSCU
8.8.1.2 OTGS
8.8.1.3 OTGM
8.8.1.4 TRIG
8.8.1.5 Tool Interface Options
8.8.1.6 DAP
8.8.1.7 JTAG
8.8.1.8 SPD
8.8.2 Changes from TC39x A-Step to AURIX TC3xx
8.8.2.1 OSCU
8.8.2.2 OTGS
8.8.2.3 OTGM
8.8.2.4 TRIG
8.8.2.5 IFS
8.8.2.6 Tool Interface Options
8.8.2.7 OCDS miscellaneous
9 Multi-Core Debug Solution (MINIMCDS)
9.1 Feature List
9.2 Overview
9.2.1 Trace Multiplexer (TMux)
9.2.2 Trace Memory
9.2.3 Observation Blocks
9.2.3.1 Processor Observation Block (POB)
9.2.4 Multi Core Cross-Connect (MCX)
9.2.4.1 Time Base
9.2.4.2 Global Trace Qualification
9.2.5 Debug Memory Controller (DMC)
9.2.6 Trace Units
9.2.7 Register File
9.3 Functional Description
9.3.1 Interface Format
9.3.2 Message Format
9.3.3 Trigger Logic
9.3.3.1 Magnitude Comparators
9.3.3.2 Fan Comparator
9.3.3.3 Data Comparators
9.3.3.4 Masked Data Comparator
9.3.4 Event Logic
9.3.5 Sequential Event Logic
9.3.6 Performance Counter
9.3.7 Action Logic
9.3.8 Program Trace Unit (PTU)
9.3.9 Data Trace Unit (DTU)
9.3.10 Duplex Data Trace Unit (DTU²)
9.3.11 Watch-point Trace Unit (WTU)
9.3.12 Debug Status and Control Trace Unit (DCU)
9.3.13 Trace Qualifier Unit (TQU)
9.3.14 Time Stamp Unit (TSU)
9.3.15 Debug Memory Controller (DMC)
9.3.15.1 Message Sorting
9.3.15.2 Buffer RAM Organization
9.3.15.3 Buffer RAM Usage
9.3.15.4 Trace Address Trigger
9.3.15.5 Buffer Memory Control
9.3.16 Processor Adaptation Logic (PAL)
9.3.17 Bus Adaptation Logic for the SPB (BAL_FPI)
9.4 Register and Implementation Description
9.4.1 Address Map
9.4.2 Trace Message Encodings
9.4.3 Observation Block for TriCore (POB_TC)
9.4.3.1 Processor Adaptation Logic for TriCore (PAL_TCX)
9.4.3.2 TriCore Program Trace (PTU_TC)
9.4.3.3 TriCore Data Trace Unit (DTU_TC)
9.4.3.4 TriCore Debug/Status Trace (DCU_TC)
9.4.3.5 TriCore Trace Qualifier Unit (TQU_TC)
9.4.4 Multi Core Cross-connect (MCX)
9.4.4.1 Time Stamp Unit (TSU)
9.4.4.2 Cross-connect Watch-point Trace (WTU_MCX)
9.4.4.3 Central Trace Qualifier Unit (TQU_MCX)
9.4.4.4 OCDS contributions
9.4.5 Buffer Memory Control
9.4.6 General Registers
9.4.6.1 Module Identification Register
9.4.6.2 Clock Control Register
9.4.6.3 Suspend Control
9.4.6.4 Signal Source Control Register
9.4.6.5 MCDS Control Register
9.5 IO Interfaces
9.6 Revision History
9.7 Changes from AURIX to TC39x A-Step
10 Default Application Memory (LMU_DAM)
10.1 Feature List
10.2 Functional Description
10.2.1 Local Memory (LMU_DAM SRAM)
10.2.2 Memory Protection
10.2.3 LMU_DAM Register Protection
10.2.4 Error Detection and Signalling
10.2.4.1 SRI access address phase error
10.2.4.2 SRI write access data phase error
10.2.4.3 Uncorrected ECC Error
10.2.4.4 Access Protection Violation
10.2.5 Clock Control
10.3 Registers
10.4 Revision History
11 System Control Units (SCU)
11.1 Reset Control Unit (RCU)
11.1.1 Feature List
11.1.1.1 Delta to AURIX
11.1.2 Overview
11.1.2.1 Reset Triggers
11.1.2.2 Reset Types
11.1.2.3 Reset Sources Overview
11.1.2.4 Warm and Cold Resets
11.1.2.5 EVR Resets and PORST
11.1.2.6 Module Reset Behavior
11.1.3 Reset Controller Functional Description
11.1.3.1 Reset Generation
11.1.3.2 Shutdown and Reset Delay Timeout Counter (TOUTCNT)
11.1.3.3 Reset Triggers
11.1.3.3.1 Specific Reset Triggers
11.1.3.3.2 Configurable Reset Triggers
11.1.3.3.3 Prevention of Double SMU Resets
11.1.3.4 Debug Reset Specific Behavior
11.1.3.5 Module Resets
11.1.3.5.1 CPU Module Resets
11.1.3.6 Reset Controller Registers
11.1.3.6.1 Status Registers
11.1.3.6.2 Reset Configuration Registers
11.1.4 External Reset Sources and Indications
11.1.4.1 External Service Requests (ESRx)
11.1.4.1.1 ESRx as Reset Request Trigger
11.1.4.1.2 ESRx as Reset Output
11.1.4.1.3 ESR Registers
11.1.5 Boot Software Interface
11.1.5.1 Configuration done with Start-up
11.1.5.2 Start-up Configuration Options
11.1.5.3 Boot Software Registers
11.1.5.3.1 Start-up Status Registers
11.2 Trap Generation (TR)
11.2.1 Feature List
11.2.1.1 Delta to AURIX
11.2.2 Trap Handling
11.2.3 Trap Registers
11.3 System Register Unit (SRU)
11.3.1 Feature List
11.3.1.1 Delta to AURIX
11.3.2 Lockstep Comparator Logic Configuration
11.3.2.1 Lockstep Comparator Logic Control Registers
11.3.3 LBIST Support
11.3.3.1 Introduction
11.3.3.1.1 Functional Description
11.3.3.2 LBIST Control Register
11.3.4 Clock System Control registers
11.3.5 Global Overlay Controls
11.3.5.1 Global Overlay Control
11.3.6 Miscellaneous System Control
11.3.6.1 System Control Register
11.3.6.2 Identification Registers
11.3.6.3 Start-up Software Memory Registers
11.3.6.4 SCU Access Restriction Registers
11.3.6.5 Alternate Address Control
11.4 Watchdog Timers (WDT)
11.4.1 Feature List
11.4.1.1 Changes to AURIX TM Family
11.4.1.2 Changes from TC39x A-Step to AURIX TC3xx
11.4.2 Watchdog Timers Overview
11.4.2.1 Safety Watchdog
11.4.2.2 CPU Watchdogs
11.4.3 Features of the Watchdog Timers
11.4.4 The Endinit Functions
11.4.4.1 Password Access to WDTxCON0
11.4.4.1.1 Static Password
11.4.4.1.2 Automatic Password Sequencing
11.4.4.1.3 Time-Independent Password
11.4.4.1.4 Time Check Password
11.4.4.2 Check Access to WDTxCON0
11.4.4.3 Modify Access to WDTxCON0
11.4.4.4 Access to Endinit-Protected Registers
11.4.4.4.1 Access to Endinit-Protected Registers using WDT
11.4.4.4.2 Access to Endinit-Protected Registers without using WDT
11.4.5 Timer Operation
11.4.5.1 Timer Modes
11.4.5.2 WDT Alarm Request
11.4.5.3 WDT Operation During Power-Saving Modes
11.4.5.4 Suspend Mode Support
11.4.6 Watchdog Timer Registers
11.5 External Request Unit (ERU)
11.5.1 Feature List
11.5.1.1 Delta to AURIX
11.5.2 Introduction
11.5.3 REQxy Digital PORT Input Glitch Filter (FILT)
11.5.4 External Request Selector Unit (ERS)
11.5.5 Event Trigger Logic (ETL)
11.5.6 Connecting Matrix
11.5.7 Output Gating Unit (OGU)
11.5.7.1 Trigger Combination
11.5.7.2 Pattern Detection
11.5.7.3 Triggering SMU alarms
11.5.8 External Request Unit Registers
11.6 Emergency Stop (ES)
11.6.1 Feature List
11.6.2 Delta to AURIX
11.6.3 Port Triggered Emergency Stop
11.6.4 SMU Event Triggered Emergency Stop
11.6.5 Emergency Stop Register
11.7 Power Management Control Registers (PMC)
11.8 Registers
11.9 IO Interfaces
11.10 Revision History
11.10.1 SCU Complete Revision History
12 Clocking System
12.1 Overview
12.2 Clocking System Registers Overview
12.3 Clock Sources
12.3.1 Oscillator Circuit (OSC)
12.3.1.1 External Input Clock Mode
12.3.1.2 External Crystal / Ceramic Resonator Mode
12.3.1.3 Oscillator Circuit Control Register
12.3.1.4 Configuration of the Oscillator
12.3.1.5 Oscillator Watchdog
12.3.2 Back-up Clock
12.4 Clock Speed Up-Scaling (PLLs)
12.4.1 System Phase-Locked Loop (System PLL) Module
12.4.1.1 Features
12.4.1.2 System PLL Functional Description
12.4.1.3 System PLL Registers
12.4.2 Peripheral Phase-Locked Loop (Peripheral PLL) Module
12.4.2.1 Features
12.4.2.2 Peripheral PLL Functional Description
12.4.2.3 Peripheral PLL Registers
12.5 Clock Distribution (CCU)
12.5.1 Clock Control Unit
12.5.1.1 Basic Clock System Mechanisms
12.5.1.2 Clock Divider Limitations
12.5.1.3 CCU Registers
12.6 Clock Emergency Behavior
12.7 External Clock Output
12.7.1 Programmable Frequency Output for EXTCLK0
12.7.1.1 Fractional Divider Operating Modes
12.7.2 Programmable Frequency Output for EXTCLK1
12.7.3 Clock Output Control Register
12.8 Clock Generation Unit
12.9 Safety Measures
12.9.1 Clock Monitoring
12.9.1.1 Clock Monitor Registers
12.10 Use Cases
12.11 Revision History
13 Power Management System (PMS)
13.1 Overview
13.2 Functional Description
13.2.1 Power Supply Infrastructure and Supply Start-up
13.2.1.1 Supply Mode Selection
13.2.1.2 Supply Ramp-up and Ramp-down Behavior
13.2.1.2.1 Single Supply mode (a)
13.2.1.2.2 Single Supply mode (e)
13.2.1.2.3 External Supply mode (d)
13.2.1.2.4 External Supply mode (h)
13.2.1.2.5 HWCFG, P32.1 / VGATE1P, P32.0 / VGATE1N behavior during Start-up
13.2.1.3 PMS Infrastructure Components
13.2.1.3.1 Independent VEVRSB & VDDPD Supply domain and EVR Pre-Regulator (EVRPR)
13.2.1.3.2 Reference Voltage Generation : Secondary Bandgap Reference (SHPBG)
13.2.1.3.3 100 MHz Back-up Clock Source (fBACK)
13.2.1.4 Die Temperature Measurement
13.2.2 Power Supply Generation and Monitoring
13.2.2.1 Linear Regulator Mode (EVR33)
13.2.2.2 Step-down Regulator (EVRC)
13.2.2.2.1 EVRC Frequency and Phase Synchronization to CCU6/GTM Input
13.2.2.3 Components and Layout
13.2.2.4 External Supply Modes
13.2.2.5 Supply Voltage Monitoring
13.2.2.5.1 Primary under-voltage monitors and Cold PORST
13.2.2.5.2 Secondary over- and under-voltage monitors and alarm generation
13.2.2.5.3 Power Built In Self Test at Start-up (PBIST)
13.2.2.5.4 Secondary Monitor and Standby SMU Built in Self Test (MONBIST)
13.2.2.6 Interrupts
13.2.2.7 OCDS Trigger Bus (OTGB) Interface
13.2.2.7.1 ADC Monitor and Voltage Trigger Sets
13.2.2.7.2 EVR Control output Trigger Sets
13.2.3 Power Management
13.2.3.1 Power Management Overview
13.2.3.2 Idle Mode
13.2.3.2.1 Entering Idle Mode :
13.2.3.2.2 State during Idle mode
13.2.3.2.3 Exiting Idle mode
13.2.3.3 Sleep Mode
13.2.3.3.1 Entering Sleep Mode
13.2.3.3.2 State during Sleep Mode
13.2.3.3.3 Exiting Sleep Mode
13.2.3.4 Standby Mode
13.2.3.4.1 Standby Mode with only VEVRSB domain supplied and VEXT domain switched off
13.2.3.4.2 Standby Mode with both VEXT and VEVRSB supplied via common supply rail.
13.2.3.4.3 Standby RAM
13.2.3.4.4 VEXT Supply Monitor
13.2.3.4.5 Pin Wake-up Unit
13.2.3.4.6 Standby ControlleR (SCR) Interface
13.2.3.4.7 Wake-up Timer (WUT)
13.2.3.4.8 Entering Standby Mode (only VEVRSB domain supplied)
13.2.3.4.9 Entering Standby Mode (both VEVRSB and VEXT domain supplied)
13.2.3.4.10 State during Standby Mode
13.2.3.4.11 Exiting Standby Mode - Wake-up event
13.2.3.4.12 Exiting Standby Mode - Power Fail or Reset event
13.2.3.5 Load Jump Sequencing and Voltage Droop
13.3 Registers
13.3.1 Power Management Control Registers (PMS)
13.3.1.1 Power Supply Generation and Monitoring Control Registers
13.3.1.2 Die Temperature Sensor Registers
13.3.1.3 Standby and Wake-up Control Registers
13.3.1.4 OCDS Trigger Bus Configuration Registers (OTGB)
13.3.1.5 SMU_STDBY Registers
13.3.2 Power Management Control Registers (SCU)
13.3.2.1 Power Management Control and Status Registers
13.4 IO Interfaces
13.5 Revision History
13.5.1 Changes from AURIX 2G PMS V2.2.19 to V2.2.24
14 Power Management System for Low-End (PMSLE)
15 Memory Test Unit (MTU)
15.1 Feature List
15.2 Overview
15.3 Functional Description
15.3.1 Major Functional Changes from TC39xA-Step to TC39XB-Step / TC38XA-Step
15.3.2 SRAM Support Hardware (SSH)
15.3.3 Control and Status Interfaces
15.3.3.1 Interface to the CPU
15.3.4 Enabling the SRAM Support Hardware (SSH)
15.3.4.1 Security-Sensitive Memories and AutoInitialization
15.3.4.1.1 Security Applications
15.3.4.1.2 Non-Security Applications
15.3.4.2 Memory Map selection
15.3.5 SRAM Support Hardware (SSH) Operation
15.3.5.1 Memory Testing and Initialization
15.3.5.1.1 Starting a Memory Test Sequence
15.3.5.1.2 Memory Test Done Interrupt
15.3.5.1.3 Getting Detailed Memory Test Results
15.3.5.1.4 Filling a Memory with Defined Contents
15.3.5.1.5 Initializing SRAMs
15.3.5.1.6 Reading a Single Memory Location
15.3.5.1.7 Writing to a Single Memory Location
15.3.6 Resets and Clocks in the MTU, SSH & SRAM
15.3.6.1 Clock Domains
15.3.6.2 Reset Domains
15.3.6.2.1 Alarm Handling after Reset
15.3.7 SRAM Addressing and Scrambling
15.3.8 MBIST Algorithms
15.3.8.1 Non-Destructive Test (NDT)
15.3.8.2 Other Memory Test Algorithms supported in the SSH
15.3.8.2.1 Introduction
15.3.8.2.2 Simple Algorithms
15.4 Registers
15.4.1 Registers Overview
15.4.2 Register Description
15.4.2.1 System Registers
15.4.2.2 MTU Configuration Registers
15.4.2.3 SRAM Support Hardware (SSH) Registers
15.5 Safety Measures
15.5.1 Safety Features
15.5.1.1 SRAM Error Detection & Correction (EDC/ECC)
15.5.1.2 Address Error Monitor
15.5.1.3 SRAM Mux Factor
15.5.1.4 Error Tracking Registers
15.5.1.5 Safety Flip-Flops
15.5.2 Safety Notifications
15.5.2.1 Alarm Handling
15.5.2.1.1 Alarms after startup
15.5.2.1.2 Diagnostics
15.5.2.1.3 Error Mapping
15.5.2.1.4 Error Injection and Alarm Triggering
15.6 Revision History
16 General Purpose I/O Ports and Peripheral I/O Lines (Ports)
16.1 Feature List
16.2 Overview
16.3 Functional Description
16.3.1 System Connectivity of Ports
16.4 Registers
16.4.1 Module Identification Register
16.4.2 Port Input/Output Control Registers
16.4.3 Pad Driver Mode Register
16.4.4 LVDS Pad Control Register
16.4.5 Pin Function Decision Control Register
16.4.6 Pin Controller Select Register
16.4.7 Port Output Register
16.4.8 Port Output Modification Register
16.4.9 Port Output Modification Set Register
16.4.10 Port Output Modification Set Registers
16.4.11 Port Output Modification Clear Register
16.4.12 Port Output Modification Clear Registers
16.4.13 Emergency Stop Register
16.4.14 Port Input Register
16.4.15 Access Protection Registers
16.5 Revision History
17 Safety Management Unit (SMU)
17.1 Feature List
17.2 Overview
17.2.1 Architecture
17.2.2 SMU_core
17.2.3 SMU_stdby
17.3 Functional Description
17.3.1 SMU_core
17.3.1.1 Reset Types
17.3.1.2 Interfaces Overview
17.3.1.2.1 Interfaces to SCU
17.3.1.2.2 Interfaces to the Interrupt Router
17.3.1.2.3 Interface to the Ports (ErrorPin)
17.3.1.2.4 Interface to the Register Monitor
17.3.1.2.5 Interface to SMU_stdby
17.3.1.3 SMU_core Integration Guidelines
17.3.1.4 Alarm Mapping
17.3.1.4.1 SMU_core Internal Alarms
17.3.1.5 Alarm Handling
17.3.1.5.1 Alarm protocol
17.3.1.5.2 Alarm Configuration
17.3.1.5.3 Alarm operation
17.3.1.5.4 Alarm Status Registers
17.3.1.5.5 Alarm Diagnosis Registers
17.3.1.5.6 Port Emergency Stop
17.3.1.5.7 Recovery Timer
17.3.1.5.8 Watchdog Alarms
17.3.1.6 SMU_core Control Interface
17.3.1.7 SMU_core State Machine
17.3.1.8 Fault Signaling Protocol (FSP)
17.3.1.8.1 Introduction
17.3.1.8.2 Bi-stable fault signaling protocol
17.3.1.8.3 Timed dual rail
17.3.1.8.4 Time switching protocol
17.3.1.8.5 FSP Fault State
17.3.1.8.6 FSP and SMU_core START State
17.3.1.9 OCDS Trigger Bus (OTGB) Interface
17.3.1.10 Register Properties
17.3.1.10.1 Register Write Protection
17.3.1.10.2 Safety Flip-flops
17.3.2 SMU_stdby
17.3.2.1 Reset Types
17.3.2.2 Interfaces Overview
17.3.2.2.1 Interface to the Pads (ErrorPin)
17.3.2.3 Alarm Mapping
17.3.2.3.1 SMU_stdby Internal Alarms
17.3.2.4 Alarm Handling
17.3.2.4.1 Alarm protocol
17.3.2.4.2 Alarm Configuration
17.3.2.5 Register Properties
17.3.2.5.1 Register Write Protection
17.3.2.5.2 Safety Flip-flops
17.3.2.6 SMU_stdby Built-In Self Test
17.3.3 Interdependency Between SMU_core and SMU_stdby
17.4 Registers
17.4.1 SMU_core Module Registers
17.4.1.1 System Registers description
17.4.1.2 SMU_core Configuration Registers
17.4.1.3 SMU_core Alarm Configuration Registers
17.4.1.4 SMU_core Alarm Configuration Registers (Fault Signaling Protocol)
17.4.1.5 SMU_core Alarm Status Registers
17.4.1.6 SMU_core Alarm Diagnosis Registers
17.4.1.7 SMU_core Special Safety Registers: Register Monitor
17.4.2 SMU_stdby Module Registers
17.4.2.1 SMU_stdby Command Register
17.4.2.2 SMU_stdby Alarm Configuration Register (Fault Signaling Protocol)
17.4.2.3 SMU_stdby Alarm Status Register
17.4.2.4 SMU_stdby BIST Control Register
17.4.2.5 SMU_stdby BIST Status Register
17.5 Revision History
18 Interrupt Router (IR)
18.1 Feature List
18.2 Delta to TC2xx
18.3 Overview
18.4 Service Request Nodes (SRN)
18.4.1 Service Request Control Registers
18.4.1.1 General Service Request Control Register Format
18.4.1.1.1 Service Request Control Register (SRC)
18.4.1.2 Changing the SRN configuration
18.4.1.3 Protection of the SRC Registers
18.4.1.4 Request Set and Clear Bits (SETR, CLRR)
18.4.1.5 Enable Bit (SRE)
18.4.1.6 Service Request Flag (SRR)
18.4.1.7 Type-Of-Service Control (TOS)
18.4.1.8 Service Request Priority Number (SRPN)
18.4.1.9 ECC Encoding (ECC)
18.4.1.10 Interrupt Trigger Overflow Bit (IOV)
18.4.1.11 Interrupt Trigger Overflow Clear Bit (IOVCLR)
18.4.1.12 SW Sticky Bit (SWS)
18.4.1.13 SW Sticky Clear Bit (SWSCLR)
18.5 Mapping of Module Interrupt Request Triggers to SRNs
18.5.1 SRC Index Number
18.5.2 Interrupts related to the Debug Reset
18.5.3 Timing characteristics of Service Request Trigger Signals
18.6 Interrupt Control Unit (ICU)
18.6.1 ICU Interface to ISP
18.6.2 ICU Control Registers
18.6.2.1 Latest Winning Service Request Register (LWSR)
18.6.2.2 Last Acknowledged Service Request Register (LASR)
18.6.2.3 Error Capture Register (ECR)
18.7 General Purpose Service Requests, Service Request Broadcast
18.7.1 General Purpose Service Requests (GPSRxy)
18.7.2 Service Request Broadcast Registers (SRBx)
18.7.3 Access protection of SRBx registers (ACCEN_SRBx)
18.8 System Registers
18.8.1 Write Protection of Interrupt Router registers
18.8.2 Kernel Reset Registers (KRST1/0, KRSTCLR)
18.8.3 Clock Control Register (CLC)
18.8.4 OCDS Control and Status Register (OCS)
18.9 Arbitration Process
18.9.1 Number of Clock Cycles per Arbitration Process
18.9.2 Service Request Valid
18.9.3 Service Request Enter
18.9.4 Service Request Acknowledge
18.9.5 Handling of detected ECC Errors
18.10 Usage of the Interrupt System
18.10.1 CPU to ICU Interface
18.10.2 DMA to ICU Interface
18.10.3 Software-Initiated Interrupts
18.10.4 External Interrupts
18.11 Use Case Examples
18.11.1 Use Case Example Interrupt Handler
18.12 Module Implementation
18.12.1 Characteristics of the Interrupt Router Module
18.13 Interrupt Router System and Module Registers
18.13.1 System and ICU Control Registers
18.14 OTGM Registers
18.14.1 Status and Control
18.14.2 IRQ MUX Control
18.14.3 Interrupt System Trace
18.14.4 MCDS Interface
18.15 Revision History
19 Flexible CRC Engine (FCE)
19.1 Feature List
19.2 Overview
19.2.1 Application Mapping
19.2.2 Block Diagram
19.3 Functional Description
19.3.1 Initialization
19.3.2 Basic Operation
19.3.3 Automatic Signature Check
19.3.4 Register protection and monitoring methods
19.3.5 Power, Reset and Clock
19.3.6 Properties of CRC code
19.3.7 Service Request Generation
19.4 Registers
19.4.1 System Registers description
19.4.2 FCE Common Registers
19.4.3 CRC Channel Control/Status Registers
19.5 Debug
19.6 IO Interfaces
19.7 Revision History
20 Direct Memory Access (DMA)
20.1 Feature List
20.2 Overview
20.3 Functional Description
20.3.1 Configuration Interface
20.3.2 Resource Partitions
20.3.2.1 Access Enable
20.3.2.2 DMA Moves
20.3.2.3 DMA RP Error Interrupt Service Request
20.3.3 DMA Channels
20.3.3.1 DMA Channel Request Control
20.3.3.1.1 DMA Channel States
20.3.3.1.2 Reset Request Only After Transaction (RROAT)
20.3.3.2 DMA Software Request
20.3.3.3 DMA Hardware Request
20.3.3.4 Combined DMA Software Request and DMA Hardware Request
20.3.3.5 DMA Daisy Chain Request
20.3.3.6 DMA Channel Transaction Request Lost Interrupt Service Request
20.3.3.7 DMA Service Requests
20.3.3.8 DMA Request Arbitration
20.3.3.9 DMA Channel Reset
20.3.3.10 DMA Channel Halt
20.3.4 DMA Random Access Memory
20.3.4.1 DMA Channel Operation
20.3.4.2 DMA Channel Updates
20.3.4.2.1 Shadow Operations
20.3.4.2.2 Double Buffering Operations
20.3.4.3 DMA Channel Reconfiguration
20.3.4.4 Move Operation
20.3.4.4.1 Address Generation
20.3.4.4.2 Address Calculation Examples
20.3.4.4.3 Circular Buffer
20.3.4.4.4 Address Alignment
20.3.4.4.5 Address Counter
20.3.4.4.6 DMA Address Checksum
20.3.4.4.7 DMA Channel Interrupt Service Request
20.3.4.4.8 DMA Channel Transfer Interrupt Service Request
20.3.4.4.9 DMA Channel Pattern Match Interrupt Service Request
20.3.4.4.10 DMA Channel Wrap Buffer Interrupt Service Request
20.3.4.5 Shadow Operation
20.3.4.5.1 Application of Shadow Operation
20.3.4.5.2 Shadowed Address Register
20.3.4.5.3 Read Only Mode
20.3.4.5.4 Direct Write Mode
20.3.4.5.5 Error Conditions
20.3.4.5.6 Transfer Count Update
20.3.4.6 DMA Timestamp
20.3.4.6.1 Generation of DMA Timestamp
20.3.4.6.2 Appendage of DMA Timestamp to Non Destination Circular Buffer
20.3.4.6.3 Appendage of DMA Timestamp to Destination Circular Buffer
20.3.4.6.4 Application of DMA Timestamp
20.3.4.7 Pattern Detection
20.3.4.7.1 Pattern Compare Logic
20.3.4.7.2 Pattern Detection for 8-bit Channel Data Width
20.3.4.7.3 Pattern Detection for 16-bit Channel Data Width
20.3.4.7.4 Pattern Detection for 32-bit Channel Data Width
20.3.4.8 Double Buffering Operations
20.3.4.8.1 DMA Double Source Buffering
20.3.4.8.2 DMA Double Destination Buffering
20.3.4.8.3 Size of Buffer
20.3.4.8.4 Buffer Switch
20.3.4.8.5 Software Switch
20.3.4.8.6 Automatic Hardware Switch
20.3.4.8.7 Application of Double Buffering
20.3.4.9 Linked List Operations
20.3.4.9.1 DMA Auto Start Request
20.3.4.9.2 Non Linked List Operation
20.3.4.9.3 Last DMA Transaction
20.3.4.9.4 Circular Linked List Operations
20.3.4.9.5 DMA Linked List (DMALL)
20.3.4.9.6 Accumulated Linked List (ACCLL)
20.3.4.9.7 Safe Linked List (SAFLL)
20.3.4.9.8 Conditional Linked List (CONLL)
20.3.4.10 DMA Data Checksum
20.3.4.11 DMARAM Initialization
20.3.5 Move Engine
20.3.5.1 ME Read Buffer
20.3.5.1.1 DMA Address Checksum
20.3.5.2 ME Error Conditions
20.3.5.3 Error Interrupt Service Request
20.3.5.3.1 DMARAM Integrity Error Interrupt Service Request
20.3.5.3.2 Source and Destination Error Interrupt Service Request
20.3.5.3.3 Linked List Operation TCS Error Interrupt Service Request
20.3.5.3.4 SAFLL DMA Address Checksum Error Interrupt Service Request
20.3.6 DMA On Chip Bus
20.3.6.1 DMA On Chip Bus Switch
20.3.6.1.1 SRI Master Interfaces
20.3.6.1.2 DMA On Chip Bus Switch Arbitration
20.3.6.2 On Chip Bus Master Interfaces
20.3.6.3 SRI Alarm
20.3.7 Power Modes
20.3.7.1 Sleep Mode
20.4 Register
20.4.1 Register
20.4.2 DMA Resource Partition Registers
20.4.3 DMA Channel Registers
20.4.4 DMARAM Channel Registers
20.4.5 ME Registers
20.5 Debug
20.5.1 DMA Channel Suspend
20.5.2 Software Activation of DMA Channel Interrupt Service Requests
20.5.3 Software Activation of DMA RP Error Interrupt Service Requests
20.5.4 OCDS Trigger Bus (OTGB) Interface
20.5.5 MCDS Trace Interface
20.6 Use Cases
20.6.1 Move Operation
20.6.1.1 Step Description to Initialize and Trigger a DMA Transaction
20.6.2 Error Handler
20.6.3 Data Communication
20.7 Revision History
21 Signal Processing Unit (SPU)
21.1 Feature List
21.2 Overview
21.2.1 Glossary of Terms
21.2.2 Processing Flow
21.2.3 Use Case examples
21.2.3.1 SPU Configuration 1
21.2.3.2 SPU Configuration 2
21.2.3.3 SPU Configuration 3
21.2.3.4 Thresholding
21.2.3.4.1 User Defined Thresholding
21.2.3.4.2 CFAR Based Thresholding Methods
21.2.3.5 Using Pre-acquisition Ramps
21.2.4 Elevation support
21.2.5 Phase demodulation
21.2.5.1 Alternate chirp demodulation
21.2.5.2 Static demodulation
21.2.5.3 HW optimisation for demodulation
21.2.6 Debugging
21.2.7 Execution flow
21.2.7.1 Execution flow for 4 Antennae
21.2.8 Memory mapping
21.2.8.1 Principle
21.2.8.2 Memory mapping for FFTs
21.2.8.3 Data Block Construction Control
21.2.8.3.1 Default Memory Mode
21.2.8.3.2 Integration Mode
21.2.8.4 Bandwidth Optimised Integration Mode
21.2.8.5 Memory mapping for other SPU results
21.2.8.6 Data sharing between SPU
21.2.8.6.1 Complex memory map via DMA reconfiguration
21.2.8.7 Example Memory mapping for 4 antenna and 16 bit operands
21.2.8.8 Data Read Order for 2nd stage FFT with 4 antennae and 16 bit operands
21.2.8.8.1 Data Mapping for 2nd Stage FFT results with 16bit Operands and 4 Antennae
21.2.8.8.2 Data Read Sequence in Integration Mode
21.2.8.8.3 Data Mapping for Integration Mode 2nd Stage FFT results with 16bit Operands and 4 Antennae
21.2.8.9 3rd stage FFT
21.2.8.10 Memory mapping for 4 antenna and 32bit operands
21.2.8.11 Data Mapping for 2nd Stage FFT with 4 antennae and 32 bit operands
21.2.8.12 Data Organisation in Integration Mode
21.2.8.13 Memory mapping for 3 antenna and 16bit operands
21.2.8.14 Data Read Sequence for 2nd Stage FFT with 3 antennae and 16 bit operands
21.2.8.15 Data Mapping for 2nd Stage FFT results with 16bit Operands and 3 Antennae
21.2.8.16 Data Read Order in Integration Mode
21.2.8.17 Data Mapping for 2nd Stage FFT results with 16bit Operands and 3 Antennae
21.2.8.18 Memory mapping for 6 antenna and 16bit operands
21.2.8.19 Data Read Order for 2nd Stage FFT with 6 antennae and 16 bit data
21.2.8.20 Data Mapping for 2nd Stage FFT results with 16bit Operands and 6 Antennae
21.2.8.21 Data Read Sequence in Integration Mode
21.2.8.22 Integration Mode Data Mapping for 2nd Stage FFT results with 16bit Operands and 6 Antennae
21.3 Functional Description
21.3.1 Input DMA Engine
21.3.1.1 Load ADC data from the RIF
21.3.1.1.1 Principles of Operation (ADC IF)
21.3.1.1.2 Split Processing
21.3.1.2 Load from Radar Memory
21.3.1.2.1 Principles of Operation (Radar Memory)
21.3.1.2.2 Case 1: “Bin Offset” is set to Sample Size
21.3.1.2.3 Case 2: “Inner Loop Offset” is set to Sample Size
21.3.1.2.4 Case 3: “Outer Loop Offset” is set to Sample Size
21.3.1.2.5 Bandwidth Optimisation for Default Processing Mode
21.3.1.2.6 Bandwidth Optimisation Integration Processing Mode.
21.3.1.3 Partial-acquisition Counter
21.3.1.4 FFT Data to Antenna Mapping
21.3.1.5 Reading Power Data From Radar Memory
21.3.1.6 Reading 16 bit Real Data From Radar Memory
21.3.1.6.1 Buffer Memory Switching for 16 bit real data
21.3.1.7 Data Storage in Buffer Memory
21.3.2 Streaming Processor 1
21.3.2.1 Double Pass Mode
21.3.2.1.1 Double Pass Switch Mode
21.3.2.1.2 Window Parameter Switch
21.3.2.2 Data Loader Unit
21.3.2.2.1 Data Reformatting
21.3.2.2.2 Integration Mode Bandwidth Optimisation
21.3.2.2.3 Overview of Data Truncation and Padding
21.3.2.3 MATH1 Unit
21.3.2.3.1 Truncation
21.3.2.3.2 Windowing
21.3.2.3.3 Phase Shift
21.3.2.3.4 Padding
21.3.2.4 FFT Accelerator
21.3.3 Data Unloader
21.3.3.1 Power Histogram
21.3.3.2 Statistical Information
21.3.4 Streaming Processor 2, The Output Data Processor
21.3.4.1 Streaming Processor 2 Data Fetch from Buffer Memory
21.3.4.2 In Place FFT
21.3.4.2.1 Restrictions
21.3.5 MATH2 Unit
21.3.5.1 Pre-Processing Units
21.3.5.1.1 Linear Power Calculation
21.3.5.1.2 Log2 Power Calculation
21.3.5.1.3 Magnitude Approximation
21.3.5.1.4 Saturating Truncation
21.3.5.2 Local Maximum Detection Unit
21.3.5.3 FFT Data Output Path
21.3.5.3.1 Scalar Addition
21.3.5.3.2 Complex Rescaling
21.3.5.3.3 Bin Rejection Unit
21.3.5.3.4 Half Precision Floating Point Format
21.3.5.4 Non-Coherent Integration
21.3.5.5 Constant False Alarm Rate Module
21.3.5.5.1 Inline Mode
21.3.5.5.2 Off-line Mode
21.3.5.5.3 CFAR Engine Architecture
21.3.5.5.4 CFAR Engine Data Format
21.3.5.5.5 CFAR Module Configuration
21.3.5.5.6 GOS-CFAR Engine
21.3.5.5.7 CA-CFAR Engine
21.3.5.5.8 CFAR Engine Configuration Restrictions
21.3.5.5.9 CFAR spectrum extension
21.3.5.5.10 Operation of Spectrum Extension
21.3.5.6 Summation Sideband Operations
21.3.5.6.1 Organisation
21.3.5.7 Statistical Information
21.3.6 Output DMA Engine
21.3.6.1 Output DMA Engine Channels
21.3.6.2 Data Cube Organisation and Size after processing ADC data
21.3.7 Radar sequencer
21.3.7.1 General Configuration
21.3.7.2 Radar sequencer start / stop
21.3.7.3 Synchronized Radar sequencer Start
21.3.7.4 Configuration / Reconfiguration
21.3.7.5 Linked Lists Organization
21.3.7.6 CPU monitoring during run time
21.3.7.7 Interrupts
21.3.8 Streaming Processor 1, Buffer RAM Switching Behaviour
21.3.8.1 Data Source is Radar Interface
21.3.8.2 Data Source is Radar Memory
21.3.9 Configuration Memory
21.3.9.1 Safety/Security
21.3.9.2 Configuration Register Data Format
21.3.9.2.1 Loading Configuration Settings
21.3.9.3 Window Data Format
21.3.9.4 Configuration Memory Usage Restrictions
21.4 Registers
21.4.1 Register Description
21.5 Debug
21.5.1 Trace Format
21.5.2 Debugger events
21.6 Safety Measures
21.6.1 Hardware Safety Mechanisms
21.6.1.1 Lockstep
21.6.1.1.1 Data Comparison Lockstep
21.6.1.2 Register CRC
21.6.1.3 RIF Interface CRC Check
21.6.1.4 Bypass Data CRC Check
21.6.1.5 Radar Memory Control Signal Redundancy
21.6.1.6 Radar Memory Tile Access Error
21.6.1.7 Radar Memory Read Data ECC
21.6.1.8 RAM ECC
21.6.1.9 RAM Address Signature ROM
21.6.1.10 Access Enable
21.6.2 Software Based Safety Mechanisms
21.6.2.1 Software Based Self Test
21.6.2.2 SPU Execution Time Check
21.6.2.3 Configuration Memory Content Check
21.6.3 Hardware Functionality Supporting Software Safety Mechanisms
21.6.3.1 Monitor Counters
21.6.3.2 Monitor CRC Units
21.6.3.3 Redundant Control Logic
21.6.4 SMU events
21.6.5 Safety assumptions
21.6.5.1 Safety assumptions and safety goals
21.6.5.1.1 Case1 = Radar with 1 Radar SPU only for low end applications
21.6.5.1.2 Case2 = Radar with 2 Radar SPUs only for mid to high end Radar
21.6.5.1.3 Case3 = Radar + sensor fusion with 2 Radar SPUs only for mid to high end Radar
21.6.5.2 Radar Application assumptions
21.6.5.2.1 Case 1: A decision is never taken on single ADC acquisition
21.6.5.2.2 Case 2: A decision is never taken on a single FFT computation (1st stage and 2nd stage FFTs)
21.6.5.2.3 Case 3: FFT peaks are never isolated
21.7 Use Cases
21.7.1 Use of FFT Clock Division (CTRL.DIV)
21.7.2 In Place FFT
21.7.3 ODM/MATH2 Dataset Sizes
21.7.4 In-line CFAR
21.7.5 CFAR Configuration
21.7.6 Non-Coherent Integration
21.7.7 FFT Data Output Path
21.7.8 Using SUMCTRL.SUMMODE=SUMANT with unconstrained ILR value
21.7.9 Kernel Reset and Lockstep
21.7.10 Supported Clocking Modes
21.7.11 RAM Initialization
21.7.12 Two SPU Instances Writing to the Same Radar Memory Tile
21.7.13 Performance of the SPU
21.7.13.1 Input Data Manager Performance
21.7.13.2 LOADER/FFT/UNLOADER Performance
21.7.13.3 MATH2/ODM Performance
21.7.13.4 Effect of “Double Pass” on Performance
21.8 I/O Interfaces
21.9 Revision History
22 SPU Lockstep Comparator (SPULCKSTP)
22.1 Feature List
22.2 Overview
22.3 Functional Description
22.3.1 SPU Lockstep Control
22.3.2 SPU Lockstep Monitoring
22.3.3 Lockstep Self Test
22.3.4 Functional Redundancy
22.3.5 Lockstep Failure Signalling Test
22.4 Registers
22.4.1 Details of SPULCKSTP Registers
22.5 Use Cases
22.5.1 Conditions of Use
22.5.2 Set Up
22.5.2.1 Specific Setup for Full Lockstep
22.5.3 SPU Triggering
22.5.4 Expected Use Cases
22.6 Revision History
23 Extension Memory (EMEM)
23.1 Feature List
23.2 Overview
23.3 Functional Description
23.3.1 Isolation Logic
23.3.2 EMEM Modes
23.3.2.1 Locked Mode
23.3.2.2 Standby Locked Mode
23.3.2.3 Changing the EMEM Mode
23.3.3 Tile Modes
23.3.3.1 Application Mode
23.3.3.2 MCDS Mode
23.3.3.3 Tool Mode
23.3.3.4 Accessing Tiles in Different Modes
23.3.4 Address Map
23.3.4.1 Address View
23.3.4.2 XTM Addressing
23.3.4.2.1 MCDS Mode
23.3.4.2.2 Tool Mode
23.3.5 EMEM Module SRAM
23.3.5.1 SRAM Initialization
23.3.5.2 Memory Integrity Check
23.3.5.3 RAM Alarm
23.3.6 SRI Interface
23.3.6.1 Register Protection
23.3.6.2 Memory Protection
23.3.6.3 Memory Disabled
23.3.6.4 True and Inverted Logic
23.3.6.5 Error Detection and Signalling
23.3.6.5.1 Access Enable Violation
23.3.6.5.2 SRI Access Address Phase Error
23.3.6.5.3 SRI Write Access Data Phase Error
23.3.6.5.4 SRI Write Access to SRAM Error
23.3.6.5.5 SRI Read Access to SRAM Error
23.3.6.5.6 True and Inverted Logic Error
23.3.6.5.7 Internal Data Transfer ECC Error
23.3.6.6 Control Redundancy
23.3.6.6.1 Control Redundancy Test
23.3.6.6.2 Consistency Check
23.3.7 SEP Interface
23.3.7.1 TC39xED SEP Accesses to EMEM Tiles
23.3.7.2 TC35x SEP Accesses to EMEM Tiles
23.3.7.3 TC33xED SEP Accesses to EMEM Tiles
23.3.7.4 SEP Error
23.3.7.5 SEP ECC Error
23.3.7.5.1 SEP Write Access
23.3.7.5.2 SEP Read Access
23.3.7.6 SPU Full Lockstep
23.3.8 Reset Control
23.3.9 Clock Control
23.4 Registers
23.4.1 EMEM Core Register Description
23.4.2 EMEM Module Register Description
23.4.2.1 EMEM Module General Registers
23.4.2.2 EMEM Module SRAM Protection Registers
23.4.3 EMEM Module RAM
23.4.4 EMEM XTM RAM
23.5 Revision History
24 Radar Interface (RIF)
24.1 Feature List
24.2 Overview
24.3 Functional Description
24.3.1 External Serial Interface (ESI)
24.3.2 Internal Parallel Interface (IPI)
24.3.3 Quad Processing Unit
24.3.4 Default CRC Scheme
24.3.5 Alternative CRC Scheme
24.3.5.1 Byte Swapping
24.3.6 CRC as a Safety Mechanism
24.3.7 Data Formatting Unit (DFU)
24.3.8 FIFO and Lane Management (FLM)
24.3.8.1 FLM Operating Modes
24.3.8.2 RIF Internal Lockstep and SPU CRC)
24.3.8.3 Real and Complex Sampling
24.3.8.4 Multi Lane Real Sampling
24.3.9 Data Memory Interface (DMI)
24.3.9.1 Data Format of the Memory Interface
24.3.10 Radar State Machine (RSM)
24.3.11 External ADC Use-Case
24.3.11.1 Frame Watchdog
24.3.11.2 On-Chip Signal Delay Calibration
24.3.11.3 On-chip Signal Delay Calibration Sequence
24.3.11.4 Waveforms Required to Perform On-Chip Signal Delay Calibration
24.3.11.5 RAMP1 Signal
24.3.12 Internal ADCs Use-Case
24.3.13 Frequency Domains
24.3.13.1 Synchronization of two RIF Modules
24.3.13.2 Interrupts
24.3.14 OCDS Trigger Sets
24.3.15 Register CRC
24.3.16 Operating Modes
24.3.16.1 Sleep Mode
24.3.16.2 OCDS Suspend Mode
24.3.17 Module Implementation
24.3.17.1 ID Registers
24.3.17.2 Implementation Details
24.3.17.3 On-Chip Connections
24.3.17.3.1 Connections to the internal ADCs
24.3.17.3.2 RAMP1 Connections
24.4 Registers
24.4.1 Kernel Registers
24.4.2 BPI_FPI Registers
24.5 IO Interfaces
24.6 Revision History
25 High Speed Pulse Density Modulation Module (HSPDM)
25.1 Feature List
25.2 Functional Description
25.2.1 HSPDM Modes of Operation
25.2.1.1 Shift Register Generated Bit-Stream
25.2.1.2 Delta-sigma Modulator Generated Bit-Stream with the CIC filter and the Compactor enabled
25.2.1.3 Delta-sigma Modulator Generated Bit-Stream with the CIC filter and the Compactor disabled
25.2.2 HSPDM clocking and EVADC trigger generation
25.2.2.1 Internal Timer Module (ITM)
25.2.2.2 ADC Trigger Generation
25.2.3 Pad Asymmetry Compensation (PAC)
25.2.4 SRAM and Data Management
25.2.4.1 RAM Buffer Manager (RAMBM)
25.2.4.2 MUTE Signal Generation
25.2.4.3 Interrupts
25.2.4.4 Starting and Stopping the Bit-Streaming
25.2.4.5 Hardware Run Feature
25.3 Registers
25.3.1 Kernel Registers
25.3.2 BPI_FPI Registers
25.4 IO Interfaces
25.5 Revision History
26 Camera and ADC Interface (CIF)
26.1 Feature List
26.2 Overview
26.2.1 Introduction
26.2.1.1 Camera and ADC Interface Functional Overview
26.2.1.2 Camera and ADC Interface Block Diagram
26.2.2 Camera and ADC Interface Functional Specification
26.2.2.1 Target Applications
26.2.2.1.1 Camera Interface Example
26.2.2.1.2 Connecting External ADC
26.3 Functional Description
26.3.1 Sub Module ISP
26.3.2 Sub Module Security Watchdog
26.3.3 Sub Module Y/C-Split
26.3.4 Sub Module JPEG Encoder
26.3.5 Sub Module Linear Downscaler
26.3.6 Sub Module Extra Path Units
26.3.7 Debug Path
26.3.8 Sub Module Memory Interface (MI)
26.3.8.1 Write to EMEM
26.3.9 BBB Master Interface
26.3.10 BBB Slave Interface
26.3.11 Control Unit
26.3.12 Shadow Registers
26.3.13 CIF Module Integration and BPI Adapter
26.3.13.1 BPI_SPB Module Registers
26.3.13.1.1 System Registers
26.3.14 CIF Programming Hints
26.3.14.1 Configuration and Shadow Registers
26.3.14.2 General Setup for Operation
26.3.14.3 Start-Stop Programming
26.3.14.3.1 Data capturing controlled by the ISP
26.3.14.4 Abort of Processing
26.3.14.4.1 Frame Skip
26.3.14.4.2 Handling Picture Size Error
26.3.14.5 Interrupt Handling
26.3.14.5.1 ISP Events
26.3.14.5.2 Memory Interface (MI) Events
26.3.14.6 Reset Handling
26.3.14.7 Programming Guide
26.3.14.7.1 ISP Programming
26.3.14.7.2 Memory Interface Programming
26.3.14.7.3 Getting Started - First steps for startup
26.3.14.8 Use Case Description
26.3.14.8.1 Data Transfer
26.3.14.8.2 Viewfinder Mode
26.3.14.8.3 Still Image Capture
26.3.14.9 Power Management
26.3.14.10 Basics on Configuration Access
26.4 Registers
26.4.1 CIF Control Registers
26.4.1.1 CIF Clock Control Registers
26.4.1.2 CIF Custom Registers
26.4.1.3 CIF Internal Control Registers
26.4.2 ISP Programming Registers
26.4.2.1 ISP Control Registers
26.4.2.2 ISP Acquisition Registers
26.4.2.3 ISP Output Control Registers
26.4.2.4 ISP Interrupt Control Registers
26.4.2.5 Miscellaneous ISP Registers
26.4.3 Linear Downscaler Programming Registers
26.4.3.1 Linear Downscaler Configuration Registers
26.4.4 Memory Interface Programming Registers
26.4.4.1 Memory Interface Control Registers
26.4.4.2 Memory Interface Shadow Registers
26.4.4.3 Memory Interface Interrupt Registers
26.4.5 JPEG Encoder Programming Registers
26.4.5.1 JPEG Encoder Control Registers
26.4.5.2 JPEG Encoder Interrupt Registers
26.4.6 Security Watchdog Programming Registers
26.4.6.1 Watchdog Configuration Registers
26.4.6.2 Watchdog Interrupt Registers
26.4.7 ISP Image Stabilization Registers
26.4.7.1 Image Stabilization Control Registers
26.4.7.2 Image Stabilization Shadow Registers
26.4.8 Extra Path Programming Registers
26.4.8.1 Extra Path Error Registers
26.4.8.2 Memory Interface Extra Path Interrupt Registers
26.4.8.3 Memory Interface Extra Path Control Registers
26.4.8.4 Extra Path Memory Interface Shadow Registers
26.4.8.5 Extra Path Image Cropping Control Registers
26.4.8.6 Extra Path Image Cropping Shadow Registers
26.4.9 Debug Path Programming Registers
26.4.9.1 Debug Path Control Registers
26.4.9.2 Debug Path Status Registers
26.4.9.3 Debug Path User Defined Symbols Registers
26.5 IO Interfaces
26.6 Revision History
Revision history
R E S T R I C T E D
N D A R e q u i r e d
A U R I X ™ T C 3 x x
About this document
Scope and purpose
This Target Specification describes the Infineon AURIX™ TC3xx Platform family, a range of 32-bit multicore
microcontrollers based on the Infineon TriCore™ Architecture.
This family document covers the superset functionality. It is supplemented by a separate device specific
document “Appendix” that covers differences of a particular device to this family superset.
Target Specification
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
Table of Contents
NDA Required
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preface-1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOC-1
1
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.2
1.2.1
1.2.1.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
1.2.2.5
1.2.2.6
1.2.2.7
1.2.3
1.2.3.1
1.2.3.2
1.2.3.3
1.2.4
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.4.1
1.3.4.2
1.3.4.3
1.3.5
1.3.6
1.4
1.4.1
1.4.2
1.4.2.1
1.4.2.2
1.4.2.2.1
1.4.2.2.2
1.4.2.2.3
1.4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Related Documentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Family Specification and Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Register and Memory Address Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Reserved, Undefined, and Unimplemented Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Register Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Register Reset Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
System Architecture of the AURIX™ TC3xx Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
AURIX™ TC3xx Platform High End – TC39xED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
TC39xED Lead Product (A-step device only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
AURIX™ TC3xx Platform - Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
TC38x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
TC37xED Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
TC37x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
TC36x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
TC35x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
TC33xED Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
TC33x Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Encoding of the Product Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
TC32x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
TC39xPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Emulation Device (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33
Comparison to AURIX Emulation Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
Trace Source Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
TMUX Setting Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
Trace Source Multiplexer in CPU Subsystem (TCMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
Parallel Trace Use Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
DAP ED Interface (DAPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
Software over the Air (SOTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Performance considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Configuring for SOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
Configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42
Initial device configuration for SOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42
Runtime SWAP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46
Target Specification
TOC-1
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
NDA Required
1.4.4
1.4.5
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.2.1
2.3.2.2
2.3.3
2.4
3
3.1
3.1.1
3.1.1.1
3.1.1.1.1
3.1.1.1.2
3.1.1.1.3
3.1.1.2
3.1.1.3
3.1.1.4
3.1.1.5
3.1.1.6
3.1.1.6.1
3.1.1.6.2
3.1.1.6.3
3.1.1.6.4
3.1.1.7
3.1.1.7.1
3.1.1.7.2
3.1.1.7.3
3.1.1.7.4
3.1.1.7.5
3.1.1.7.6
3.1.1.7.7
3.1.1.7.8
3.1.1.7.9
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
3.1.3
3.1.3.1
3.1.3.2
3.1.3.2.1
3.1.3.2.2
3.1.3.2.3
3.1.3.2.4
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46
Memory Maps (MEMMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Address Map of the On Chip Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Segments 0 to 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
AURIX™ TC3xx Platform Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Startup Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Events triggering SSW execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Cold (initial) power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Application reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Clock system during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
RAM overwrite during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Stand-by controller handling during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Boot Options Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Boot Mode evaluation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Evaluation of Boot Mode Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Alternate Boot Mode evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Processing in case no valid BMHD found . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Processing in case no Boot Mode configured by SSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Startup Software Main Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Flash ramp-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
RAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Select and execute Startup Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
LBIST execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Lockstep configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Debug System handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
ESR0 pin handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Ending the SSW and Starting the User Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Checker Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
CHSW execution flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Checks performed by CHSW and exit information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Checker Software exit information for ALL CHECKS PASSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Bootstrap Loaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
ASC Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
CAN Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
CAN BSL summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Clock system during CAN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
CAN BSL usage after application reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Supported CAN features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Target Specification
TOC-2
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
NDA Required
3.1.3.2.5
3.1.4
3.1.5
3.1.6
3.2
3.2.1
3.2.1.1
3.2.1.2
3.3
CAN BSL flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Support for Software over the Air (SOTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Shutdown request handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Power Supply Friendly Debug Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Firmware specific usage of device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Registers providing information on the boot selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Registers providing information on the Checker Software activity . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
4
4.1
4.1.1
4.2
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.1.5
4.3.1.6
4.3.2
4.3.2.1
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.3.4
4.3.3.5
4.3.3.6
4.3.3.7
4.3.4
4.3.4.1
4.3.4.2
4.3.4.3
4.3.4.4
4.3.4.5
4.3.4.6
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.6
4.6.1
4.7
On-Chip System Connectivity {and Bridges} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
What is new in the SRI Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Master Connection Interface (MCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Slave Connection Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Slave Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Default Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
OnLine Data Acquisition (OLDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Control and Status Register Access Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Arbitration Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Master Request Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
SRI Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
SRI Protocol Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
SRI Transaction ID Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
SRI EDC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Error Tracking Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Indication Event Interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Releasing the lock from registers ERR and ERRADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Implementation of the SRI Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Mapping of SRI Masters to Domain 0 Master Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Mapping of SRI Slaves to Domain 0 Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Mapping of SRI Masters to Domain 1 Master Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Mapping of SRI Slaves to Domain 1 Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Mapping of SRI Masters to Domain 2 Master Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Mapping of SRI Slaves to Domain 2 Slave Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Domain Common Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
SCI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
S2S Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
EDC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Protocol Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Transaction ID Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
Transaction Errors for Writes via S2S Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
SFI_F2S Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
SFI_S2F Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Target Specification
TOC-3
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
NDA Required
4.7.1
4.8
4.9
4.10
4.10.1
4.10.1.1
4.10.2
4.10.2.1
4.10.2.2
4.10.2.3
4.10.2.4
4.10.3
4.10.3.1
4.10.3.1.1
4.10.3.1.2
4.10.3.1.3
4.10.3.2
4.10.4
4.10.4.1
4.10.4.2
4.10.4.3
4.10.4.4
4.10.4.5
4.10.5
4.10.5.1
4.10.5.2
4.10.5.3
4.10.5.4
4.10.5.5
4.10.6
4.10.6.1
4.10.6.2
4.10.6.3
4.10.6.4
4.10.6.5
4.10.6.6
4.10.7
4.10.8
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Resource Access Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
FPI Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
Delta to TC2xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Bus Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36
Reaction of a Busy Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Address Alignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
FPI Bus Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37
Functional Description (SBCU, EBCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
FPI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Arbitration on the System Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Default Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
Arbitration Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FPI Bus Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
FPI Bus Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
Safety Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
FPI EDC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46
SPB: Mapping of ALARM signals to SBCU_ALSTATx and SBCU_ALCLRx registers . . . . . . . . . . . . 4-46
BBB: Mapping of ALARM signals to EBCU_ALSTATx and EBCU_ALCLRx registers . . . . . . . . . . . . 4-49
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
Address Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51
Signal Status Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52
Grant Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
Combination of Trigger Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
BCU Breakpoint Generation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-56
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73
Register Access Protection (ACCEN1/0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74
Kernel Reset Registers (KRST1/0, KRSTCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
Clock Control Register (CLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
OCDS Control and Status Register (OCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
On Chip Bus Master TAG Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-77
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.3.1
5.3.2
5.3.3
CPU Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
CPU Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Instruction Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
General Purpose Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Summary of functional changes from AURIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Summary of changes from TC39x A-Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
AURIXTM Family CPU configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Target Specification
TOC-4
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
NDA Required
5.3.4
5.3.4.1
5.3.4.2
5.3.4.3
5.3.4.4
5.3.4.5
5.3.4.6
5.3.4.7
5.3.4.8
5.3.4.9
5.3.4.10
5.3.4.11
5.3.4.12
5.3.4.12.1
5.3.4.13
5.3.4.14
5.3.4.14.1
5.3.4.15
5.3.4.16
5.3.4.17
5.3.4.18
5.3.4.19
5.3.4.19.1
5.3.4.20
5.3.4.20.1
5.3.4.21
5.3.4.21.1
5.3.4.22
5.3.4.22.1
5.3.4.22.2
5.3.5
5.3.5.1
5.3.5.1.1
5.3.5.1.2
5.3.5.1.3
5.3.5.1.4
5.3.5.2
5.3.5.2.1
5.3.5.2.2
5.3.5.2.3
5.3.5.2.4
5.3.5.3
5.3.6
5.3.6.1
5.3.6.1.1
5.3.6.1.2
5.3.6.1.3
5.3.6.1.4
5.3.6.2
5.3.6.2.1
CPU Implementation-Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Context Save Areas / Context Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Program Counter (PC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Store Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Trap System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Invalid Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Speculation extent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Instruction Memory Range Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Atomicity of Data Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
A11 usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Independent Core Kernel Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Kernel Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
CPU Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
CPU Core Special Function Registers (CSFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
CPU General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
FPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
CPU Memory Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Temporal Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Exception Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Exception Timers Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Memory Integrity Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
CPU Core Debug and Performance Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
Counter Source Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44
CPU Subsystem Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
Summary of CSFR Reset Values and Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47
Summary of SFR Reset Values and Access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
CPU Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
Integer-Pipeline Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
Simple Arithmetic Instruction Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56
Multiply Instruction Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
Multiply Accumulate (MAC) Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
Control Flow Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
Load-Store Pipeline Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61
Address Arithmetic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61
CSA Control Flow Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
Load Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
Store Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
Floating Point Pipeline Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
Local Memory Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Local and Global Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
CSFR and SFR base Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65
Cache Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
Customer-ID Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
Memory Integrity Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
Program Side Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67
Target Specification
TOC-5
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
NDA Required
5.3.6.2.2
5.3.6.2.3
5.3.6.3
5.3.6.3.1
5.3.6.3.2
5.3.6.4
5.3.6.4.1
5.3.6.4.2
5.3.6.4.3
5.3.6.4.4
5.3.7
5.3.7.1
5.3.7.2
5.3.7.3
5.3.7.4
5.3.7.4.1
5.3.8
5.3.8.1
5.3.8.2
5.3.8.3
5.3.8.4
5.3.8.5
5.3.8.6
5.3.9
5.3.9.1
5.3.9.2
5.3.9.2.1
5.3.9.3
5.3.9.3.1
5.3.9.3.2
5.3.9.3.3
5.3.9.4
5.3.9.4.1
5.3.9.5
5.3.9.6
5.3.9.7
5.3.9.7.1
5.3.9.8
5.3.10
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.6.1
5.4.6.2
5.4.7
5.4.7.1
Data Side Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
Memory Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69
Program Memory Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
TC1.6.2P PMI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
PMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Data Memory Interface (DMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76
DMI Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76
Distributed LMU (DLMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
DMI Trap Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78
DMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Boot Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
SSH usage recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Debug restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
Local Pflash Bank Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
Lockstep Comparator Logic (LCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
Lockstep Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-90
Lockstep Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
Lockstep Self Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-91
Lockstep Failure Signalling Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
Functional Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
Data Access Overlay (OVC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-94
Data Access Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
Target Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
Online Data Acquisition (OLDA) Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
Overlay Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
DSPR & PSPR Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
Global Overlay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
Global Overlay Control Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
Overlay Configuration Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
Access Protection, Attributes, Concurrent Matches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
Overlay Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100
Block control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-100
Global overlay control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104
CPU Architecture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-104
Safety Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
SRI Bus Master Address Phase Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
SRI Bus Master Write Phase Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
SRI bus Slave Read Phase Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
SRI Error Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
SRI Safe Data Master tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Safety Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Bus MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
Register Access Enable Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109
Registers Implementing Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-110
SRI safety registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-111
Target Specification
TOC-6
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
RESTRICTED
AURIX™ TC3xx
NDA Required
5.4.7.2
5.5
5.6
Safety Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
IO Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.3.1
6.2.3.1.1
6.2.3.1.2
6.2.3.2
6.2.3.2.1
6.2.3.2.2
6.2.3.3
6.2.3.4
6.2.4
6.2.5
6.2.6
6.3
6.3.1
6.3.2
6.3.3
6.3.3.1
6.3.3.2
6.3.4
6.3.5
6.3.5.1
6.3.5.2
6.4
6.5
6.5.1
6.5.2
6.5.2.1
6.5.2.1.1
6.5.2.1.2
6.5.2.2
6.5.2.2.1
6.5.2.2.2
6.5.2.2.3
6.5.2.2.4
6.5.2.2.5
6.5.2.2.6
6.5.2.2.7
6.5.2.2.8
6.5.2.3
6.5.2.4
6.5.2.4.1
Non Volatile Memory (NVM) Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Major changes from Aurix to AURIXTC3XX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Flash Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Program Flash Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
PFLASH Tuning Protection (TP) and HSM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Erase Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
EEPROM Emulation with DFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
DFLASH Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Robust EEPROM Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Data Flash Bank DFLASH0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Data Flash Bank DFLASH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Program Flash (PFLASH) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Data Flash (DFLASH) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Boot ROM (BROM) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Safety Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Safety Endinit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Data Reliability and Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
PFLASH ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
DFLASH ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Integrity of PFlash read data wait cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
SRI Access Address Phase Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
SRI Access Write Data Phase Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Data Memory Unit (DMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Flash Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Transaction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Configuring Flash Read Access Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Command Sequence Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Protection for Verify Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
DMU Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
Suspend and Resume Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
Programming Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43
Performing Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43
Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
Host Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47
Target Specification
TOC-7
V2.5.1
2018-04
Downloaded by IFXDMZ\par-suedward 20/02/2019 20:16:42
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