ARM Cortex-M0+ Devices Generic User Guide.pdf

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Cortex-M0+ Devices Generic User Guide

Contents

Preface

About this book

Product revision status

Intended audience

Using this book

Glossary

Conventions

Additional reading

Feedback

Feedback on this product

Feedback on content

1: Introduction

1.1 About the Cortex-M0+ processor and core peripherals

1.1.1 System-level interface

1.1.2 Optional integrated configurable debug

1.1.3 Cortex-M0+ processor features summary

1.1.4 Cortex-M0+ core peripherals

2: The Cortex-M0+ Processor

2.1 Programmers model

2.1.1 Processor modes and privilege levels for software execution

2.1.2 Stacks

2.1.3 Core registers

2.1.4 Exceptions and interrupts

2.1.5 Data types

2.1.6 The Cortex Microcontroller Software Interface Standard

2.2 Memory model

2.2.1 Memory regions, types and attributes

2.2.2 Memory system ordering of memory accesses

2.2.3 Behavior of memory accesses

2.2.4 Software ordering of memory accesses

2.2.5 Memory endianness

2.3 Exception model

2.3.1 Exception states

2.3.2 Exception types

2.3.3 Exception handlers

2.3.4 Vector table

2.3.5 Exception priorities

2.3.6 Exception entry and return

2.4 Fault handling

2.4.1 Lockup

2.5 Power management

2.5.1 Entering sleep mode

2.5.2 Wakeup from sleep mode

2.5.3 The optional Wakeup Interrupt Controller

2.5.4 The external event input

2.5.5 Power management programming hints

3: The Cortex-M0+ Instruction Set

3.1 Instruction set summary

3.2 Intrinsic functions

3.3 About the instruction descriptions

3.3.1 Operands

3.3.2 Restrictions when using PC or SP

3.3.3 Shift operations

3.3.4 Address alignment

3.3.5 PC-relative expressions

3.3.6 Conditional execution

3.4 Memory access instructions

3.4.1 ADR

3.4.2 LDR and STR, immediate offset

3.4.3 LDR and STR, register offset

3.4.4 LDR, PC-relative

3.4.5 LDM and STM

3.4.6 PUSH and POP

3.5 General data processing instructions

3.5.1 ADC, ADD, RSB, SBC, and SUB

3.5.2 AND, ORR, EOR, and BIC

3.5.3 ASR, LSL, LSR, and ROR

3.5.4 CMP and CMN

3.5.5 MOV and MVN

3.5.6 MULS

3.5.7 REV, REV16, and REVSH

3.5.8 SXT and UXT

3.5.9 TST

3.6 Branch and control instructions

3.6.1 B, BL, BX, and BLX

3.7 Miscellaneous instructions

3.7.1 BKPT

3.7.2 CPS

3.7.3 DMB

3.7.4 DSB

3.7.5 ISB

3.7.6 MRS

3.7.7 MSR

3.7.8 NOP

3.7.9 SEV

3.7.10 SVC

3.7.11 WFE

3.7.12 WFI

4: Cortex-M0+ Peripherals

4.1 About the Cortex-M0+ peripherals

4.2 Nested Vectored Interrupt Controller

4.2.1 Interrupt Set-Enable Register

4.2.2 Interrupt Clear-Enable Register

4.2.3 Interrupt Set-Pending Register

4.2.4 Interrupt Clear-Pending Register

4.2.5 Interrupt Priority Registers

4.2.6 Level-sensitive and pulse interrupts

4.2.7 NVIC usage hints and tips

4.3 System Control Block

4.3.1 CMSIS mapping of the Cortex-M0+ SCB registers

4.3.2 CPUID Register

4.3.3 Interrupt Control and State Register

4.3.4 Vector Table Offset Register

4.3.5 Application Interrupt and Reset Control Register

4.3.6 System Control Register

4.3.7 Configuration and Control Register

4.3.8 System Handler Priority Registers

4.3.9 SCB usage hints and tips

4.4 System timer, SysTick

4.4.1 SysTick Control and Status Register

4.4.2 SysTick Reload Value Register

4.4.3 SysTick Current Value Register

4.4.4 SysTick Calibration Value Register

4.4.5 SysTick usage hints and tips

4.5 Memory Protection Unit

4.5.1 MPU Type Register

4.5.2 MPU Control Register

4.5.3 MPU Region Number Register

4.5.4 MPU Region Base Address Register

4.5.5 MPU Region Attribute and Size Register

4.5.6 MPU access permission attributes

4.5.7 MPU access permission faults

4.5.8 Updating an MPU region

4.5.9 MPU usage hints and tips

4.6 Single-cycle I/O Port

A: Revisions

Cortex-M0+ Devices Generic User Guide Copyright © 2012 ARM. All rights reserved. Release Information The following changes have been made to this book. Change history Date Issue Confidentiality Change 04 April 2012 18 December 2012 A B Non-Confidential First release Non-Confidential Second release Proprietary Notice Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential ii

Contents Cortex-M0+ Devices Generic User Guide Chapter 1 Chapter 2 Chapter 3 Chapter 4 Preface About this book ........................................................................................................... vi Feedback .................................................................................................................. viii Introduction 1.1 About the Cortex-M0+ processor and core peripherals ........................................... 1-2 The Cortex-M0+ Processor 2.1 2.2 2.3 2.4 2.5 Programmers model ................................................................................................ 2-2 Memory model ....................................................................................................... 2-10 Exception model .................................................................................................... 2-16 Fault handling ........................................................................................................ 2-22 Power management ............................................................................................... 2-23 The Cortex-M0+ Instruction Set 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Instruction set summary ........................................................................................... 3-2 Intrinsic functions ..................................................................................................... 3-5 About the instruction descriptions ............................................................................ 3-6 Memory access instructions .................................................................................. 3-11 General data processing instructions .................................................................... 3-19 Branch and control instructions ............................................................................. 3-33 Miscellaneous instructions ..................................................................................... 3-36 Cortex-M0+ Peripherals 4.1 4.2 4.3 4.4 About the Cortex-M0+ peripherals ........................................................................... 4-2 Nested Vectored Interrupt Controller ....................................................................... 4-3 System Control Block .............................................................................................. 4-8 System timer, SysTick ........................................................................................... 4-16 ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential iii

4.5 4.6 Memory Protection Unit ......................................................................................... 4-19 Single-cycle I/O Port .............................................................................................. 4-28 Appendix A Revisions Contents ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential iv

Preface This preface introduces the Cortex-M0+ Devices Generic User Guide. It contains the following sections: • • About this book on page vi. Feedback on page viii. ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential v

About this book Product revision status Intended audience Using this book Glossary Preface This book is a generic user guide for devices that implement the ARM Cortex-M0+ processor. Implementers of Cortex-M0+ processor designs make a number of implementation choices, that can affect the functionality of the device. This means that, in this book: • • Some information is described as IMPLEMENTATION DEFINED. Some features are described as optional. See the documentation from the supplier of your Cortex-M0+ device for more information about these features. In this book, unless the context indicates otherwise: Processor Refers to the Cortex-M0+ processor, as supplied by ARM. Device Refers to an implemented device, supplied by an ARM partner, that incorporates a Cortex-M0+ processor. In particular, your device refers to the particular implementation of the Cortex-M0+ processor that you are using. Some features of your device depend on the implementation choices made by the ARM partner that made the device. The rnpn identifier indicates the revision status of the product described in this book, where: rn pn Identifies the major revision of the product. Identifies the minor revision or modification status of the product. This book is written for application and system-level software developers, familiar with programming, who want to program a device that includes the Cortex-M0+ processor. This book is organized into the following chapters: Chapter 1 Introduction Read this for an introduction to the Cortex-M0+ processor and its features. Chapter 2 The Cortex-M0+ Processor Read this for a description of the programmers model, the processor memory model, exception and fault handling, and power management. Chapter 3 The Cortex-M0+ Instruction Set Read this for a description of the processor instruction set. Chapter 4 Cortex-M0+ Peripherals Read this for a description of the Cortex-M0+ core peripherals. The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See ARM Glossary, http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html. ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential vi

Preface Conventions This book uses the conventions that are described in: • Typographical conventions. Typographical conventions The following table describes the typographical conventions: Style italic bold monospace monospace Purpose Introduces special terminology, denotes cross-references, and citations. Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0 , , , SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE. Additional reading This section lists publications by ARM and by third parties. See Infocenter, http://infocenter.arm.com, for access to ARM documentation. ARM publications This book contains information that is specific to this product. See the following documents for other relevant information: • • Cortex-M0+ Technical Reference Manual (ARM DDI 0484). ARMv6-M Architecture Reference Manual (ARM DDI 0419). Other publications This guide only provides generic information for devices that implement the ARM Cortex-M0+ processor. For information about your device see the documentation published by the device manufacturer. ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential vii

Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product Preface Feedback on content If you have any comments or suggestions about this product, contact your supplier and give: • • • The product name. The product revision or version. An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. If you have comments on content then send an e-mail to errata@arm.com. Give: • • • • The title. The number, ARM DUI 0662B. The page numbers to which your comments apply. A concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. ARM DUI 0662B ID011713 Copyright © 2012 ARM. All rights reserved. Non-Confidential viii

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