一、设计要求
设计一个由一条支干道和一条主干道的汇合点形成的十字交叉路口的交通
灯控制器,主要要求如下:
1.主、支干道各设有一个绿、黄、红指示灯,两个显示数码管。
2.主干道处于常允许状态,两支干道有车来才允许通行。
3.当主、支干道有车时,两者交替通行,主干道每次放行 45s,支干道每次
放行 25s,在每次由亮绿灯变成亮红灯转换过程中,要亮 5s 黄灯作为过渡,并
进行减计时显示。
二、对题目的理解
(一)、交通灯的功能是实现一个交叉口的通车控制,交通灯显示有以下 4
种状态:
1.主干道绿灯,支干道红灯;
2.主干道绿灯,支干道黄灯;
3.主干道红灯,支干道绿灯;
4.主干道黄灯,支干道绿灯。
(二)、支干道没车时,主干道一直亮绿灯;主干道没车时,主干道和支干
道交替亮绿灯;主干道和支干道都有车时同样交替亮红绿灯。在红绿灯交替时亮
5s 黄灯。
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一、JTDKZ
简单思路:假设 4 种状态分别为:A、B、C、D,在 CLK 上升沿来时,根
据 SB、SM 状态判断交通处于何种状态,该状态输出什么信号。
设计的原理图模块:
设计源程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JTDKZ IS
PORT(CLK,SM,SB:IN STD_LOGIC;
MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);
END ENTITY JTDKZ;
ARCHITECTURE ART OF JTDKZ IS
TYPE STATE_TYPE IS(A,B,C,D);
SIGNAL STATE:STATE_TYPE;
BEGIN
CNT:PROCESS(CLK)IS
VARIABLE S:INTEGER RANGE 0 TO 45;
VARIABLE CLR,EN:BIT;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF CLR='0'THEN S:=0;
ELSIF EN='0'THEN S:=S;
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ELSE S:=S+1;
END IF;
CASE STATE IS
WHEN A=>MR<='0';MY0<='0';MG0<='1';BR<='1';BY0<='0';BG0<='0';
IF(SB AND SM)='1' THEN
IF S=45 THEN STATE<=B;CLR:='0';EN:='0';
ELSE STATE<=A;CLR:='1';EN:='1';
END IF;
ELSIF(SB AND(NOT SM))='1'THEN STATE<=B;CLR:='0';EN:='0';
ELSE STATE<=A;CLR:='1';EN:='1';
END IF;
WHEN B=>MR<='0';MY0<='1';MG0<='0';BR<='1';BY0<='0';BG0<='0';
IF S=5 THEN STATE<=C;CLR:='0';EN:='0';
ELSE STATE<=B;CLR:='1';EN:='1';
END IF;
WHEN C=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='0';BG0<='1';
IF(SM AND SB)='1'THEN
IF S=25 THEN STATE<=D;CLR:='0';EN:='0';
ELSE STATE<=C;CLR:='1';EN:='1';
END IF;
ELSIF SB='0' THEN STATE<=D;CLR:='0';EN:='0';
ELSE STATE<=C;CLR:='1';EN:='1';
END IF;
WHEN D=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='1';BG0<='0';
IF S=5 THEN STATE<=A;CLR:='0';EN:='0';
ELSE STATE<=D;CLR:='1';EN:='1';
END IF;
END CASE;
END IF;
END PROCESS CNT;
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END ARCHITECTURE ART;
设计仿真的截图:
二、XSKZ
简单设计思路:根据EN45、EN25、EN05M、EN05B的信号以及3个倒计时
计数器的计数状态决定输出3个倒计时计数器中某个的状态输出。
原理图模块:
设计源程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CSKZ IS
PORT(INA:IN STD_LOGIC;
OUTA:OUT STD_LOGIC);
END ENTITY CSKZ;
ARCHITECTURE ART OF CSKZ IS
BEGIN
4
PROCESS(INA)IS
BEGIN
IF INA='1'THEN OUTA<='1';
ELSE OUTA<='0';
END IF;
END PROCESS;
END ARCHITECTURE ART;
设计仿真的截图:
三、CNT45S
简单思路:CLK 上升沿到来时,若到计时使能信号和 SB 信号有效,CNT45S
开始计数,并将输入状态通过 DOUT45M、DOUT45B 分别输出到主、支干道显
示。
设计的原理图模块:
设计源程序:3
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT45S IS
PORT(SB,CLK,EN45:IN STD_LOGIC;
DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END CNT45S;
ARCHITECTURE ART OF CNT45S IS
SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(SB,CLK,EN45) IS
BEGIN
IF SB='0' THEN CNT6B<=CNT6B-CNT6B-1;
ELSIF(CLK'EVENT AND CLK='1')THEN
IF EN45='1'THEN CNT6B<=CNT6B+1;
ELSIF EN45='0'THEN CNT6B<=CNT6B-CNT6B-1;
END IF;
END IF;
END PROCESS;
PROCESS(CNT6B)IS
BEGIN
CASE CNT6B IS
WHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000";
WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001";
WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000";
WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111";
WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110";
WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101";
WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100";
WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011";
WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010";
WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001";
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WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000";
WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="01101001";
WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000";
WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111";
WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110";
WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101";
WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100";
WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011";
WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";
WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";
WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";
WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";
WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";
WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";
WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";
WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";
WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";
WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";
WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";
WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";
WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";
WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";
WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";
WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";
WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";
WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";
WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";
WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";
WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";
WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";
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WHEN"101000"=>DOUT45M<="00000101";DOUT45B<="00010000";
WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";
WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";
WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";
WHEN"101100"=>DOUT45M<="00000001";DOUT45B<="00000110";
WHEN OTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";
END CASE;
END PROCESS;
END;
设计仿真的截图:
4、CNT25S
简单思路:CLK 上升沿到来时,若到计时使能信号、SM 信号和 SB 信号有
效,CNT25S 开始计数,并将输入状态通过 DOUT25M、DOUT25B 分别输出到
主、支干道显示。
设计的原理图模块:
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