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MIPI D-PHY_specification_v1-1..pdf
Contents
Figures
Tables
1 Introduction
1.1 Scope
1.2 Purpose
2 Terminology
2.1 Definitions
2.2 Abbreviations
2.3 Acronyms
3 References
4 D-PHY Overview
4.1 Summary of PHY Functionality
4.2 Mandatory Functionality
5 Architecture
5.1 Lane Modules
5.2 Master and Slave
5.3 High Frequency Clock Generation
5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface
5.5 Selectable Lane Options
5.6 Lane Module Types
5.6.1 Unidirectional Data Lane
5.6.2 Bi-directional Data Lanes
5.6.2.1 Bi-directional Data Lane without High-Speed Reverse Communication
5.6.2.2 Bi-directional Data Lane with High-Speed Reverse Communication
5.6.3 Clock Lane
5.7 Configurations
5.7.1 Unidirectional Configurations
5.7.1.1 PHY Configuration with a Single Data Lane
5.7.1.2 PHY Configuration with Multiple Data Lanes
5.7.1.3 Dual-Simplex (Two Directions with Unidirectional Lanes)
5.7.2 Bi-Directional Half-Duplex Configurations
5.7.2.1 PHY Configurations with a Single Data Lane
5.7.2.2 PHY Configurations with Multiple Data Lanes
5.7.3 Mixed Data Lane Configurations
6 Global Operation
6.1 Transmission Data Structure
6.1.1 Data Units
6.1.2 Bit order, Serialization, and De-Serialization
6.1.3 Encoding and Decoding
6.1.4 Data Buffering
6.2 Lane States and Line Levels
6.3 Operating Modes: Control, High-Speed, and Escape
6.4 High-Speed Data Transmission
6.4.1 Burst Payload Data
6.4.2 Start-of-Transmission
6.4.3 End-of-Transmission
6.4.4 HS Data Transmission Burst
6.5 Bi-directional Data Lane Turnaround
6.6 Escape Mode
6.6.1 Remote Triggers
6.6.2 Low-Power Data Transmission
6.6.3 Ultra-Low Power State
6.6.4 Escape Mode State Machine
6.7 High-Speed Clock Transmission
6.8 Clock Lane Ultra-Low Power State
6.9 Global Operation Timing Parameters
6.10 System Power States
6.11 Initialization
6.12 Calibration
6.13 Global Operation Flow Diagram
6.14 Data Rate Dependent Parameters (informative)
6.14.1 Parameters Containing Only UI Values
6.14.2 Parameters Containing Time and UI values
6.14.3 Parameters Containing Only Time Values
6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent
7 Fault Detection
7.1 Contention Detection
7.2 Sequence Error Detection
7.2.1 SoT Error
7.2.2 SoT Sync Error
7.2.3 EoT Sync Error
7.2.4 Escape Mode Entry Command Error
7.2.5 LP Transmission Sync Error
7.2.6 False Control Error
7.3 Protocol Watchdog Timers (informative)
7.3.1 HS RX Timeout
7.3.2 HS TX Timeout
7.3.3 Escape Mode Timeout
7.3.4 Escape Mode Silence Timeout
7.3.5 Turnaround Errors
8 Interconnect and Lane Configuration
8.1 Lane Configuration
8.2 Boundary Conditions
8.3 Definitions
8.4 S-parameter Specifications
8.5 Characterization Conditions
8.6 Interconnect Specifications
8.6.1 Differential Characteristics
8.6.2 Common-mode Characteristics
8.6.3 Intra-Lane Cross-Coupling
8.6.4 Mode-Conversion Limits
8.6.5 Inter-Lane Cross-Coupling
8.6.6 Inter-Lane Static Skew
8.7 Driver and Receiver Characteristics
8.7.1 Differential Characteristics
8.7.2 Common-Mode Characteristics
8.7.3 Mode-Conversion Limits
8.7.4 Inter-Lane Matching
9 Electrical Characteristics
9.1 Driver Characteristics
9.1.1 High-Speed Transmitter
9.1.2 Low-Power Transmitter
9.2 Receiver Characteristics
9.2.1 High-Speed Receiver
9.2.2 Low-Power Receiver
9.3 Line Contention Detection
9.4 Input Characteristics
10 High-Speed Data-Clock Timing
10.1 High-Speed Clock Timing
10.2 Forward High-Speed Data Transmission Timing
10.2.1 Data-Clock Timing Specifications
10.3 Reverse High-Speed Data Transmission Timing
11 Regulatory Requirements
Annex A Logical PHY-Protocol Interface Description (informative)
A.1 Signal Description
A.2 High-Speed Transmit from the Master Side
A.3 High-Speed Receive at the Slave Side
A.4 High-Speed Transmit from the Slave Side
A.5 High-Speed Receive at the Master Side
A.6 Low-Power Data Transmission
A.7 Low-Power Data Reception
A.8 Turn-around
Annex B Interconnect Design Guidelines (informative)
B.1 Practical Distances
B.2 RF Frequency Bands: Interference
B.3 Transmission Line Design
B.4 Reference Layer
B.5 Printed-Circuit Board
B.6 Flex-foils
B.7 Series Resistance
B.8 Connectors
Annex C 8b9b Line Coding for D-PHY (normative)
C.1 Line Coding Features
C.1.1 Enabled Features for the Protocol
C.1.2 Enabled Features for the PHY
C.2 Coding Scheme
C.2.1 8b9b Coding Properties
C.2.2 Data Codes: Basic Code Set
C.2.3 Comma Codes: Unique Exception Codes
C.2.4 Control Codes: Regular Exception Codes
C.2.5 Complete Coding Scheme
C.3 Operation with the D-PHY
C.3.1 Payload: Data and Control
C.3.1.1 Idle/Sync Comma Symbols
C.3.1.2 Protocol Marker Comma Symbol
C.3.1.3 EoT Marker
C.3.2 Details for HS Transmission
C.3.2.1 SoT
C.3.2.2 HS Transmission Payload
C.3.2.3 EoT
C.3.3 Details for LP Transmission
C.3.3.1 SoT
C.3.3.2 LP Transmission Payload
C.3.3.3 EoT
C.4 Error Signaling
C.5 Extended PPI
C.6 Complete Code Set
5-Jan-2012
MIPI® Alliance Specification for
D-PHY
Version 1.1 – 7 November 2011
* NOTE TO IMPLEMENTERS *
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to
this MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
However, implementers should be aware of the following:
It is the good faith expectation of the MIPI PHY Working Group that D-PHY v1.1 is stable and
robust. The MIPI Alliance currently recommends that any member companies considering
implementation of D-PHY base their work on this version of the Specification (v1.1), which is
intended to supersede the previous version (v1.00.00).
This version of the Specification includes minor relaxations to the conformance ranges for several
key parameters. These modifications are intended to ease implementation for designs supporting
HS bitrates > 1 Gbps, allowing for slightly greater conformance margins for these parameters, to
better allow for process and manufacturing variations in these implementations.
In some cases the modified conformance limits apply only to operation at HS rates > 1 Gbps
(while the previous limits still apply to rates ≤ 1Gbps), while in other cases the new conformance
values are applicable to all HS rates. In all cases, the modified conformance limits have been
widened with respect to the previous values, so that any implementation conformant to these
parameters in the previous version of this Specification (v1.00.00) should also be conformant to
the modified limits defined in this version (v1.1).
The follow list includes all parameters with modified conformance limits:
• HS rise/fall time (tR, tF)
• VOD mismatch (ΔVOD)
• TX data to clock skew (TSKEW[TX])
• RX setup and hold times (TSETUP[RX], THOLD[RX])
• TX and RX return loss (SddTX, SddRX)
Copyright © 2012 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
5-Jan-2012
See the respective Specification sections for details.
Also in this version of the Specification, one new parameter has been added (∆UI) that more
precisely constrains the allowed peak-to-peak variation of the HS bitrate (UI) within a single HS
burst. The addition of this new parameter is intended to address suspected interoperability
concerns that may arise for devices that show excessive variability of their HS-TX bitrate within a
single HS burst.
It is the good faith expectation of the MIPI PHY WG that there will be no significant functional
changes to the fundamental technology described in this Specification.
Copyright © 2012 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.1 7-Nov-2011
MIPI Alliance Specification for D-PHY
MIPI® Alliance Specification for
D-PHY
Version 1.1 – 7 November 2011
MIPI Board Approved 16-Dec-2011
Further technical changes to this document are expected as work continues in the PHY Working Group
Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.1 7-Nov-2011
MIPI Alliance Specification for D-PHY
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or
controlled by any of the authors or developers of this material or MIPI®. The material contained herein is
provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is
provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI
hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not
limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of
viruses, and of lack of negligence.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express
prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all
related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI
Alliance and cannot be used without its express prior written permission.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD
TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY
AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR
MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document
is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of
the contents of this Document; (b) does not monitor or enforce compliance with the contents of this
Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of
compliance with the contents of this Document. The use or implementation of the contents of this
Document may involve or require the use of intellectual property rights ("IPR") including (but not limited
to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of
MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the
disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
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1.2
2.1
2.2
2.3
Contents
Version 1.1 – 7 November 2011 ................................................................................................................ i
1
Introduction .................................................................................................................................... 10
Scope ...................................................................................................................................... 10
Purpose ................................................................................................................................... 11
Terminology ................................................................................................................................... 12
Definitions .............................................................................................................................. 12
Abbreviations .......................................................................................................................... 13
Acronyms ............................................................................................................................... 13
3 References ...................................................................................................................................... 16
4 D-PHY Overview ............................................................................................................................ 17
4.1
Summary of PHY Functionality............................................................................................... 17
4.2 Mandatory Functionality ......................................................................................................... 17
5 Architecture .................................................................................................................................... 18
5.1
Lane Modules ......................................................................................................................... 18
5.2 Master and Slave..................................................................................................................... 19
5.3
High Frequency Clock Generation........................................................................................... 19
Clock Lane, Data Lanes and the PHY-Protocol Interface ......................................................... 19
5.4
Selectable Lane Options .......................................................................................................... 20
5.5
5.6
Lane Module Types ................................................................................................................. 22
Unidirectional Data Lane ................................................................................................. 23
Bi-directional Data Lanes ................................................................................................ 23
Clock Lane ...................................................................................................................... 24
Configurations ........................................................................................................................ 24
Unidirectional Configurations.......................................................................................... 26
5.7.1
5.7.2
Bi-Directional Half-Duplex Configurations...................................................................... 28
5.7.3 Mixed Data Lane Configurations ..................................................................................... 29
6 Global Operation ............................................................................................................................ 30
Transmission Data Structure ................................................................................................... 30
Data Units ....................................................................................................................... 30
Bit order, Serialization, and De-Serialization ................................................................... 30
Encoding and Decoding ................................................................................................... 30
Data Buffering ................................................................................................................. 30
Lane States and Line Levels .................................................................................................... 30
Operating Modes: Control, High-Speed, and Escape ............................................................... 31
High-Speed Data Transmission ............................................................................................... 32
6.1.1
6.1.2
6.1.3
6.1.4
5.6.1
5.6.2
5.6.3
6.2
6.3
6.4
5.7
6.1
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Version 1.1 7-Nov-2011
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6.5
6.6
6.4.1
6.4.2
6.4.3
6.4.4
6.6.1
6.6.2
6.6.3
6.6.4
Burst Payload Data .......................................................................................................... 32
Start-of-Transmission ...................................................................................................... 32
End-of-Transmission ....................................................................................................... 33
HS Data Transmission Burst ............................................................................................ 33
Bi-directional Data Lane Turnaround ...................................................................................... 35
Escape Mode ........................................................................................................................... 38
Remote Triggers .............................................................................................................. 39
Low-Power Data Transmission ........................................................................................ 40
Ultra-Low Power State ..................................................................................................... 40
Escape Mode State Machine ............................................................................................ 40
High-Speed Clock Transmission ............................................................................................. 42
6.7
Clock Lane Ultra-Low Power State ......................................................................................... 47
6.8
6.9
Global Operation Timing Parameters ...................................................................................... 49
6.10 System Power States................................................................................................................ 53
6.11
Initialization ........................................................................................................................... 53
6.12 Calibration .............................................................................................................................. 53
6.13 Global Operation Flow Diagram ............................................................................................. 53
6.14 Data Rate Dependent Parameters (informative) ....................................................................... 55
Parameters Containing Only UI Values ........................................................................... 56
6.14.1
Parameters Containing Time and UI values ..................................................................... 56
6.14.2
Parameters Containing Only Time Values ....................................................................... 56
6.14.3
6.14.4
Parameters Containing Only Time Values That Are Not Data Rate Dependent ................ 57
Fault Detection ............................................................................................................................... 58
Contention Detection .............................................................................................................. 58
Sequence Error Detection ........................................................................................................ 58
SoT Error ........................................................................................................................ 59
SoT Sync Error ................................................................................................................ 59
EoT Sync Error ............................................................................................................... 59
Escape Mode Entry Command Error ............................................................................... 59
LP Transmission Sync Error ............................................................................................ 59
False Control Error .......................................................................................................... 59
Protocol Watchdog Timers (informative)................................................................................. 59
HS RX Timeout ............................................................................................................... 59
HS TX Timeout ............................................................................................................... 59
Escape Mode Timeout ..................................................................................................... 60
Escape Mode Silence Timeout ......................................................................................... 60
Turnaround Errors ........................................................................................................... 60
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.1
7.2
7.3
Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
iv
Version 1.1 7-Nov-2011
MIPI Alliance Specification for D-PHY
8
8.7
8.1
8.2
8.3
8.4
8.5
8.6
Interconnect and Lane Configuration .............................................................................................. 61
Lane Configuration ................................................................................................................. 61
Boundary Conditions .............................................................................................................. 61
Definitions .............................................................................................................................. 61
S-parameter Specifications ...................................................................................................... 62
Characterization Conditions .................................................................................................... 62
Interconnect Specifications...................................................................................................... 63
8.6.1
Differential Characteristics .............................................................................................. 63
8.6.2
Common-mode Characteristics ........................................................................................ 64
8.6.3
Intra-Lane Cross-Coupling .............................................................................................. 64
8.6.4 Mode-Conversion Limits ................................................................................................. 64
8.6.5
Inter-Lane Cross-Coupling .............................................................................................. 64
Inter-Lane Static Skew .................................................................................................... 65
8.6.6
Driver and Receiver Characteristics ........................................................................................ 65
Differential Characteristics .............................................................................................. 65
8.7.1
8.7.2
Common-Mode Characteristics ........................................................................................ 66
8.7.3 Mode-Conversion Limits ................................................................................................. 66
8.7.4
Inter-Lane Matching ........................................................................................................ 66
Electrical Characteristics ................................................................................................................ 67
Driver Characteristics ............................................................................................................. 68
High-Speed Transmitter .................................................................................................. 68
Low-Power Transmitter ................................................................................................... 73
Receiver Characteristics .......................................................................................................... 77
High-Speed Receiver ....................................................................................................... 77
Low-Power Receiver ........................................................................................................ 79
Line Contention Detection ...................................................................................................... 80
Input Characteristics ............................................................................................................... 81
High-Speed Data-Clock Timing .................................................................................................. 83
10.1 High-Speed Clock Timing ....................................................................................................... 83
10.2 Forward High-Speed Data Transmission Timing ..................................................................... 84
10.2.1 Data-Clock Timing Specifications ................................................................................... 85
10.3 Reverse High-Speed Data Transmission Timing...................................................................... 86
11
Regulatory Requirements ............................................................................................................ 88
Annex A Logical PHY-Protocol Interface Description (informative) ................................................... 89
Signal Description .................................................................................................................. 89
A.1
A.2 High-Speed Transmit from the Master Side............................................................................. 96
A.3 High-Speed Receive at the Slave Side...................................................................................... 97
9.1.1
9.1.2
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9.3
9.4
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9.2.1
9.2.2
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Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
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v
Version 1.1 7-Nov-2011
MIPI Alliance Specification for D-PHY
Annex B
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
A.4 High-Speed Transmit from the Slave Side ............................................................................... 97
A.5 High-Speed Receive at the Master Side ................................................................................... 98
Low-Power Data Transmission................................................................................................ 98
A.6
A.7
Low-Power Data Reception ..................................................................................................... 99
Turn-around............................................................................................................................ 99
A.8
Interconnect Design Guidelines (informative) .....................................................................101
Practical Distances .................................................................................................................101
RF Frequency Bands: Interference ..........................................................................................101
Transmission Line Design......................................................................................................101
Reference Layer .....................................................................................................................102
Printed-Circuit Board .............................................................................................................102
Flex-foils................................................................................................................................102
Series Resistance ....................................................................................................................102
Connectors .............................................................................................................................102
8b9b Line Coding for D-PHY (normative) ..........................................................................103
Line Coding Features .............................................................................................................104
Enabled Features for the Protocol ...................................................................................104
Enabled Features for the PHY .........................................................................................104
C.2 Coding Scheme ......................................................................................................................104
8b9b Coding Properties...................................................................................................104
Data Codes: Basic Code Set ............................................................................................105
Comma Codes: Unique Exception Codes ........................................................................106
Control Codes: Regular Exception Codes ........................................................................106
Complete Coding Scheme ...............................................................................................107
C.3 Operation with the D-PHY .....................................................................................................107
Payload: Data and Control ..............................................................................................107
Details for HS Transmission ...........................................................................................107
Details for LP Transmission ...........................................................................................108
Error Signaling ......................................................................................................................108
C.4
C.5
Extended PPI .........................................................................................................................109
C.6 Complete Code Set .................................................................................................................110
C.2.1
C.2.2
C.2.3
C.2.4
C.2.5
C.3.1
C.3.2
C.3.3
Annex C
C.1
C.1.1
C.1.2
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Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
vi
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