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RTL8367RBI-CG.pdf
1. General Description
2. Features
3. System Applications
4. Application Examples
4.1. 5-Port 1000Base-T Switch
4.2. 5-Port 1000Base-T Router with Dual MII/RGMII
5. Block Diagram
6. Pin Assignments
6.1. Package Identification
6.2. Pin Assignments Table
7. Pin Descriptions
7.1. Media Dependent Interface Pins
7.2. General Purpose Interfaces
7.2.1. RGMII Pins
7.2.2. MII Pins
7.3. LED Pins
7.4. Configuration Strapping Pins
7.4.1. Configuration Strapping Pins (DISAUTOLOAD and DIS_8051)
7.5. Management Interface Pins
7.6. Miscellaneous Pins
7.7. Test Pins
7.8. Power and GND Pins
8. Physical Layer Functional Overview
8.1. MDI Interface
8.2. 1000Base-T Transmit Function
8.3. 1000Base-T Receive Function
8.4. 100Base-TX Transmit Function
8.5. 100Base-TX Receive Function
8.6. 10Base-T Transmit Function
8.7. 10Base-T Receive Function
8.8. Auto-Negotiation for UTP
8.9. Crossover Detection and Auto Correction
8.10. Polarity Correction
9. General Function Description
9.1. Reset
9.1.1. Hardware Reset
9.1.2. Software Reset
9.1.2.1 CHIP_RESET
9.1.2.2 SOFT_RESET
9.2. IEEE 802.3x Full Duplex Flow Control
9.3. Half Duplex Flow Control
9.3.1. Back-Pressure Mode
9.4. Search and Learning
9.5. SVL and IVL/SVL
9.6. Illegal Frame Filtering
9.7. IEEE 802.3 Reserved Group Addresses Filtering Control
9.8. Broadcast/Multicast/Unknown DA Storm Control
9.9. Port Security Function
9.10. MIB Counters
9.11. Port Mirroring
9.12. VLAN Function
9.12.1. Port-Based VLAN
9.12.2. IEEE 802.1Q Tag-Based VLAN
9.12.3. Protocol-Based VLAN
9.12.4. Port VID
9.13. QoS Function
9.13.1. Input Bandwidth Control
9.13.2. Priority Assignment
9.13.3. Priority Queue Scheduling
9.13.4. IEEE 802.1p/Q and DSCP Remarking
9.13.5. ACL-Based Priority
9.14. IGMP & MLD Snooping Function
9.15. IEEE 802.1x Function
9.15.1. Port-Based Access Control
9.15.2. Authorized Port-Based Access Control
9.15.3. Port-Based Access Control Direction
9.15.4. MAC-Based Access Control
9.15.5. MAC-Based Access Control Direction
9.15.6. Optional Unauthorized Behavior
9.15.7. Guest VLAN
9.16. IEEE 802.1D Function
9.17. Embedded 8051
9.18. Realtek Cable Test (RTCT)
9.19. LED Indicators
9.20. Green Ethernet
9.20.1. Link-On and Cable Length Power Saving
9.20.2. Link-Down Power Saving
9.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function
9.22. Interrupt Pin for External CPU
10. Interface Descriptions
10.1. EEPROM SMI Host to EEPROM
10.2. EEPROM SMI Slave for External CPU
10.3. SPI Slave for External CPU
10.3.1. SPI-Slave Interface Access Format
10.4. General Purpose Interface
10.4.1. Extension Ports RGMII Mode (1Gbps)
10.4.2. Extension Ports MII MAC/PHY Mode Interface (10/100Mbps)
11. Register Descriptions
11.1. PCS Register (PHY 0~4)
11.2. Register 0: Control
11.3. Register 1: Status
11.4. Register 2: PHY Identifier 1
11.5. Register 3: PHY Identifier 2
11.6. Register 4: Auto-Negotiation Advertisement
11.7. Register 5: Auto-Negotiation Link Partner Ability
11.8. Register 6: Auto-Negotiation Expansion
11.9. Register 7: Auto-Negotiation Page Transmit Register
11.10. Register 8: Auto-Negotiation Link Partner Next Page Register
11.11. Register 9: 1000Base-T Control Register
11.12. Register 10: 1000Base-T Status Register
11.13. Register 15: Extended Status
12. Electrical Characteristics
12.1. Absolute Maximum Ratings
12.2. Recommended Operating Range
12.3. Thermal Characteristics
12.3.1. Assembly Description
12.3.2. Material Properties
12.3.3. Simulation Conditions
12.3.4. Thermal Performance of E-Pad LQFP-128 on PCB Under Still Air Convection
12.3.5. Thermal Performance of E-Pad LQFP-128 on PCB Under Forced Convection
12.4. DC Characteristics
12.5. AC Characteristics
12.5.1. EEPROM SMI Host Mode Timing Characteristics
12.5.2. EEPROM SMI Slave Mode Timing Characteristics
12.5.3. SPI Slave Mode Timing Characteristics
12.5.4. MDIO Slave Mode Timing Characteristics
12.5.5. MII MAC Mode Timing
12.5.6. MII PHY Mode Timing
12.5.7. RGMII Timing Characteristics
12.6. Power and Reset Characteristics
13. Mechanical Dimensions
14. Ordering Information
RTL8367RBI-CG
LAYER 2 MANAGED 5+2-PORT
10/100/1000M SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
23 August 2018
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8367RBI
Datasheet
COPYRIGHT
©2018 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8367RBI IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2018/08/23
Summary
First Release.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
ii
Track ID: JATR-8275-15 Rev. 1.0
Table of Contents
RTL8367RBI
Datasheet
4.1.
4.2.
6.1.
6.2.
7.1.
7.2.
5.
6.
7.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
FEATURES ......................................................................................................................................................................... 3
2.
3.
SYSTEM APPLICATIONS ............................................................................................................................................... 5
4. APPLICATION EXAMPLES ........................................................................................................................................... 5
5-PORT 1000BASE-T SWITCH ...................................................................................................................................... 5
5-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII............................................................................................... 6
BLOCK DIAGRAM ........................................................................................................................................................... 7
PIN ASSIGNMENTS ......................................................................................................................................................... 8
PACKAGE IDENTIFICATION ........................................................................................................................................... 8
PIN ASSIGNMENTS TABLE ............................................................................................................................................ 9
PIN DESCRIPTIONS ...................................................................................................................................................... 12
MEDIA DEPENDENT INTERFACE PINS ......................................................................................................................... 12
GENERAL PURPOSE INTERFACES ................................................................................................................................ 13
7.2.1. RGMII Pins........................................................................................................................................................... 15
7.2.2. MII Pins ................................................................................................................................................................ 17
LED PINS ................................................................................................................................................................... 20
CONFIGURATION STRAPPING PINS ............................................................................................................................. 21
7.4.1. Configuration Strapping Pins (DISAUTOLOAD and DIS_8051) ........................................................................ 23
MANAGEMENT INTERFACE PINS ................................................................................................................................ 23
MISCELLANEOUS PINS ............................................................................................................................................... 24
TEST PINS .................................................................................................................................................................. 27
POWER AND GND PINS .............................................................................................................................................. 27
PHYSICAL LAYER FUNCTIONAL OVERVIEW...................................................................................................... 28
MDI INTERFACE ........................................................................................................................................................ 28
1000BASE-T TRANSMIT FUNCTION ........................................................................................................................... 28
1000BASE-T RECEIVE FUNCTION .............................................................................................................................. 28
100BASE-TX TRANSMIT FUNCTION ........................................................................................................................... 28
100BASE-TX RECEIVE FUNCTION ............................................................................................................................. 29
10BASE-T TRANSMIT FUNCTION ............................................................................................................................... 29
10BASE-T RECEIVE FUNCTION .................................................................................................................................. 29
AUTO-NEGOTIATION FOR UTP .................................................................................................................................. 29
CROSSOVER DETECTION AND AUTO CORRECTION ..................................................................................................... 30
POLARITY CORRECTION ............................................................................................................................................. 30
9. GENERAL FUNCTION DESCRIPTION ...................................................................................................................... 31
RESET ........................................................................................................................................................................ 31
9.1.1. Hardware Reset .................................................................................................................................................... 31
9.1.2.
Software Reset ...................................................................................................................................................... 31
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................ 31
HALF DUPLEX FLOW CONTROL ................................................................................................................................. 32
9.3.1. Back-Pressure Mode ............................................................................................................................................ 32
SEARCH AND LEARNING ............................................................................................................................................ 33
SVL AND IVL/SVL ................................................................................................................................................... 33
ILLEGAL FRAME FILTERING ....................................................................................................................................... 33
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................. 34
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL ..................................................................................... 35
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
9.4.
9.5.
9.6.
9.7.
9.8.
9.1.
9.2.
9.3.
8.
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Track ID: JATR-8275-15 Rev. 1.0
9.14.
9.15.
10.
9.21.
9.22.
10.1.
10.2.
10.3.
11.
RTL8367RBI
Datasheet
9.12.1.
9.12.2.
9.12.3.
9.12.4.
9.13.1.
9.13.2.
9.13.3.
9.13.4.
9.13.5.
9.15.1.
9.15.2.
9.15.3.
9.15.4.
9.15.5.
9.15.6.
9.15.7.
9.9.
PORT SECURITY FUNCTION ........................................................................................................................................ 35
9.10. MIB COUNTERS ......................................................................................................................................................... 35
9.11.
PORT MIRRORING ...................................................................................................................................................... 35
9.12. VLAN FUNCTION ...................................................................................................................................................... 36
Port-Based VLAN ............................................................................................................................................ 36
IEEE 802.1Q Tag-Based VLAN ....................................................................................................................... 36
Protocol-Based VLAN ..................................................................................................................................... 37
Port VID .......................................................................................................................................................... 37
9.13. QOS FUNCTION .......................................................................................................................................................... 38
Input Bandwidth Control ................................................................................................................................. 38
Priority Assignment ......................................................................................................................................... 38
Priority Queue Scheduling............................................................................................................................... 38
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................ 39
ACL-Based Priority ......................................................................................................................................... 39
IGMP & MLD SNOOPING FUNCTION ......................................................................................................................... 40
IEEE 802.1X FUNCTION ............................................................................................................................................. 41
Port-Based Access Control .............................................................................................................................. 41
Authorized Port-Based Access Control ........................................................................................................... 41
Port-Based Access Control Direction .............................................................................................................. 41
MAC-Based Access Control............................................................................................................................. 41
MAC-Based Access Control Direction ............................................................................................................ 42
Optional Unauthorized Behavior ..................................................................................................................... 42
Guest VLAN ..................................................................................................................................................... 42
IEEE 802.1D FUNCTION ............................................................................................................................................ 42
9.16.
9.17.
EMBEDDED 8051 ........................................................................................................................................................ 42
9.18. REALTEK CABLE TEST (RTCT) ................................................................................................................................. 43
9.19.
LED INDICATORS ....................................................................................................................................................... 43
9.20. GREEN ETHERNET ...................................................................................................................................................... 45
Link-On and Cable Length Power Saving ....................................................................................................... 45
Link-Down Power Saving ................................................................................................................................ 45
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ............................................................................... 45
INTERRUPT PIN FOR EXTERNAL CPU ......................................................................................................................... 45
INTERFACE DESCRIPTIONS ................................................................................................................................. 46
EEPROM SMI HOST TO EEPROM ........................................................................................................................... 46
EEPROM SMI SLAVE FOR EXTERNAL CPU .............................................................................................................. 47
SPI SLAVE FOR EXTERNAL CPU ................................................................................................................................ 48
SPI-Slave Interface Access Format ................................................................................................................. 48
10.4. GENERAL PURPOSE INTERFACE ................................................................................................................................. 49
Extension Ports RGMII Mode (1Gbps) ............................................................................................................ 50
Extension Ports MII MAC/PHY Mode Interface (10/100Mbps) ...................................................................... 51
REGISTER DESCRIPTIONS .................................................................................................................................... 53
11.1.
PCS REGISTER (PHY 0~4) ......................................................................................................................................... 53
11.2. REGISTER 0: CONTROL ............................................................................................................................................... 54
11.3. REGISTER 1: STATUS .................................................................................................................................................. 55
11.4. REGISTER 2: PHY IDENTIFIER 1 ................................................................................................................................. 56
11.5. REGISTER 3: PHY IDENTIFIER 2 ................................................................................................................................. 56
11.6. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ................................................................................................. 56
11.7. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ....................................................................................... 57
11.8. REGISTER 6: AUTO-NEGOTIATION EXPANSION .......................................................................................................... 58
11.9. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER .................................................................................. 58
REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................ 59
11.10.
REGISTER 9: 1000BASE-T CONTROL REGISTER .................................................................................................... 59
11.11.
11.12.
REGISTER 10: 1000BASE-T STATUS REGISTER ..................................................................................................... 60
10.3.1.
10.4.1.
10.4.2.
9.20.1.
9.20.2.
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Track ID: JATR-8275-15 Rev. 1.0
RTL8367RBI
Datasheet
12.
11.13.
13.
14.
12.3.1.
12.3.2.
12.3.3.
12.3.4.
12.3.5.
REGISTER 15: EXTENDED STATUS ......................................................................................................................... 60
ELECTRICAL CHARACTERISTICS...................................................................................................................... 61
12.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 61
12.2. RECOMMENDED OPERATING RANGE .......................................................................................................................... 61
THERMAL CHARACTERISTICS .................................................................................................................................... 62
12.3.
Assembly Description ...................................................................................................................................... 62
Material Properties ......................................................................................................................................... 62
Simulation Conditions ..................................................................................................................................... 62
Thermal Performance of E-Pad LQFP-128 on PCB Under Still Air Convection ........................................... 63
Thermal Performance of E-Pad LQFP-128 on PCB Under Forced Convection ............................................ 63
12.4. DC CHARACTERISTICS ............................................................................................................................................... 64
12.5. AC CHARACTERISTICS ............................................................................................................................................... 65
EEPROM SMI Host Mode Timing Characteristics ......................................................................................... 65
EEPROM SMI Slave Mode Timing Characteristics ........................................................................................ 66
SPI Slave Mode Timing Characteristics .......................................................................................................... 67
MDIO Slave Mode Timing Characteristics ..................................................................................................... 67
MII MAC Mode Timing ................................................................................................................................... 69
MII PHY Mode Timing .................................................................................................................................... 70
RGMII Timing Characteristics ........................................................................................................................ 71
POWER AND RESET CHARACTERISTICS ...................................................................................................................... 74
MECHANICAL DIMENSIONS ................................................................................................................................. 76
ORDERING INFORMATION ................................................................................................................................... 77
12.5.1.
12.5.2.
12.5.3.
12.5.4.
12.5.5.
12.5.6.
12.5.7.
12.6.
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE .............................................................................................................................................. 9
TABLE 2. MEDIA DEPENDENT INTERFACE PINS ........................................................................................................................... 12
TABLE 3. GENERAL PURPOSE INTERFACES PINS .......................................................................................................................... 13
TABLE 4. EXTENSION GMAC1 RGMII PINS ............................................................................................................................... 15
TABLE 5. EXTENSION GMAC2 RGMII PINS ............................................................................................................................... 16
TABLE 6. EXTENSION GMAC1 MII PINS (MII MAC MODE OR MII PHY MODE) ....................................................................... 17
TABLE 7. EXTENSION GMAC2 MII PINS (MII MAC MODE OR MII PHY MODE) ....................................................................... 18
TABLE 8. LED PINS ..................................................................................................................................................................... 20
TABLE 9. CONFIGURATION STRAPPING PINS ............................................................................................................................... 21
TABLE 10. CONFIGURATION STRAPPING PINS (DISAUTOLOAD AND DIS_8051) ...................................................................... 23
TABLE 11. MANAGEMENT INTERFACE PINS .................................................................................................................................. 23
TABLE 12. MISCELLANEOUS PINS ................................................................................................................................................. 24
TABLE 13. TEST PINS .................................................................................................................................................................... 27
TABLE 14. POWER AND GND PINS ................................................................................................................................................ 27
TABLE 15. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................ 30
TABLE 16. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE ......................................................................................... 34
TABLE 17. IPV4/IPV6 MULTICAST ROUTING PROTOCOLS ............................................................................................................. 40
TABLE 18. LED DEFINITIONS........................................................................................................................................................ 43
TABLE 19. RTL8367RBI-VB EXTENSION PORT 1 PIN DEFINITIONS ............................................................................................. 49
TABLE 20. RTL8367RBI-VB EXTENSION PORT 2 PIN DEFINITIONS ............................................................................................. 49
TABLE 21. EXTENSION GMAC1 RGMII PINS ............................................................................................................................... 50
TABLE 22. EXTENSION GMAC2 RGMII PINS ............................................................................................................................... 50
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Track ID: JATR-8275-15 Rev. 1.0
RTL8367RBI
Datasheet
TABLE 23. EXTENSION GMAC1 MII PINS .................................................................................................................................... 51
TABLE 24. EXTENSION GMAC2 MII PINS .................................................................................................................................... 51
TABLE 25. PCS REGISTER (PHY 0~4)........................................................................................................................................... 53
TABLE 26. REGISTER 0: CONTROL ................................................................................................................................................ 54
TABLE 27. REGISTER 1: STATUS .................................................................................................................................................... 55
TABLE 28. REGISTER 2: PHY IDENTIFIER 1 ................................................................................................................................... 56
TABLE 29. REGISTER 3: PHY IDENTIFIER 2 ................................................................................................................................... 56
TABLE 30. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ................................................................................................... 56
TABLE 31. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................ 57
TABLE 32. REGISTER 6: AUTO-NEGOTIATION EXPANSION ............................................................................................................ 58
TABLE 33. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER.................................................................................... 58
TABLE 34. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ................................................................... 59
TABLE 35. REGISTER 9: 1000BASE-T CONTROL REGISTER ........................................................................................................... 59
TABLE 36. REGISTER 10: 1000BASE-T STATUS REGISTER ............................................................................................................ 60
TABLE 37. REGISTER 15: EXTENDED STATUS ............................................................................................................................... 60
TABLE 38. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 61
TABLE 39. RECOMMENDED OPERATING RANGE ........................................................................................................................... 61
TABLE 40. ASSEMBLY DESCRIPTION ............................................................................................................................................. 62
TABLE 41. MATERIAL PROPERTIES ............................................................................................................................................... 62
TABLE 42. SIMULATION CONDITIONS ........................................................................................................................................... 62
TABLE 43. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER STILL AIR CONVECTION ......................................... 63
TABLE 44. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER FORCED CONVECTION ............................................ 63
TABLE 45. DC CHARACTERISTICS ................................................................................................................................................. 64
TABLE 46. EEPROM SMI HOST MODE TIMING CHARACTERISTICS ............................................................................................. 66
TABLE 47. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ........................................................................................... 66
TABLE 48. SPI-SLAVE MODE TIMING CHARACTERISTICS ............................................................................................................. 67
TABLE 49. MDIO TIMING CHARACTERISTICS AND REQUIREMENT ............................................................................................... 68
TABLE 50. MII MAC MODE TIMING ............................................................................................................................................. 69
TABLE 51. MII PHY MODE TIMING CHARACTERISTICS ................................................................................................................ 70
TABLE 52. RGMII TIMING CHARACTERISTICS .............................................................................................................................. 72
TABLE 53. POWER AND RESET TIMING REQUIREMENTS................................................................................................................ 75
TABLE 54. POWER MONITOR RESET CHARACTERISTICS ............................................................................................................... 75
TABLE 55. ORDERING INFORMATION ............................................................................................................................................ 77
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
vi
Track ID: JATR-8275-15 Rev. 1.0
List of Figures
RTL8367RBI
Datasheet
FIGURE 1. 5-PORT 1000BASE-T SWITCH ....................................................................................................................................... 5
FIGURE 2. 5-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII................................................................................................ 6
FIGURE 3. BLOCK DIAGRAM .......................................................................................................................................................... 7
FIGURE 4. PIN ASSIGNMENTS (LQFP-128 EPAD) ......................................................................................................................... 8
FIGURE 5. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION .................................................................................................. 30
FIGURE 6. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART .................................................................................. 37
FIGURE 7. RTL8367RBI-VB MAX-MIN SCHEDULING DIAGRAM .............................................................................................. 39
FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED........................................................................... 44
FIGURE 9. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED ................................................................................... 44
FIGURE 10. SMI START AND STOP COMMAND .............................................................................................................................. 46
FIGURE 11. EEPROM SMI HOST TO EEPROM ............................................................................................................................ 46
FIGURE 12. EEPROM SMI HOST MODE FRAME ........................................................................................................................... 46
FIGURE 13. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................ 47
FIGURE 14. EEPROM SMI READ COMMAND FOR SLAVE MODE .................................................................................................. 47
FIGURE 15. SPI-SLAVE WRITE COMMAND ACCESS FORMAT ........................................................................................................ 48
FIGURE 16. SPI-SLAVE READ COMMAND ACCESS FORMAT ......................................................................................................... 48
FIGURE 17. RGMII MODE INTERFACE SIGNAL DIAGRAM ............................................................................................................. 50
FIGURE 18. SIGNAL DIAGRAM OF MII PHY MODE INTERFACE (100MBPS) .................................................................................. 52
FIGURE 19. SIGNAL DIAGRAM OF MII MAC MODE INTERFACE (100MBPS) ................................................................................. 52
FIGURE 20. EEPROM SMI HOST MODE TIMING CHARACTERISTICS ............................................................................................ 65
FIGURE 21. SCK/SDA POWER ON TIMING .................................................................................................................................... 65
FIGURE 22. EEPROM AUTO-LOAD TIMING.................................................................................................................................. 65
FIGURE 23. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS .......................................................................................... 66
FIGURE 24. SPI-SLAVE MODE TIMING CHARACTERISTICS ............................................................................................................ 67
FIGURE 25. MDIO SOURCED BY MASTER ..................................................................................................................................... 68
FIGURE 26. MDIO SOURCED BY RTL8367RBI-VB (SLAVE)........................................................................................................ 68
FIGURE 27. MII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING ...................................................................................... 69
FIGURE 28. MII MAC MODE INPUT TIMING ................................................................................................................................. 69
FIGURE 29. MII PHY MODE OUTPUT TIMING ............................................................................................................................... 70
FIGURE 30. MII PHY MODE CLOCK OUTPUT TO DATA INPUT DELAY TIMING ............................................................................. 70
FIGURE 31. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=0)................................................................. 71
FIGURE 32. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=2NS) ............................................................ 71
FIGURE 33. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=0) .................................................................... 71
FIGURE 34. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=2NS) ................................................................ 72
FIGURE 35. POWER AND RESET CHARACTERISTICS ....................................................................................................................... 74
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RTL8367RBI
Datasheet
1. General Description
The RTL8367RBI-CG is a LQFP128 EPAD, high-performance 5+2-port 10/100/1000M Ethernet switch
featuring a low-power integrated 5-port Giga-PHY that supports 1000Base-T, 100Base-TX, and 10Base-
T.
For specific applications, the RTL8367RBI supports two extra interfaces that could be configured as
RGMII/MII interfaces. The RTL8367RBI integrates all the functions of a high-speed switch system;
including SRAM for packet buffering, non-blocking switch fabric, and internal register management into
a single CMOS device. Only a 25MHz crystal is required; an optional EEPROM is offered for internal
register configuration.
The embedded packet storage SRAM in the RTL8367RBI features superior memory management
technology to efficiently utilize memory space. The RTL8367RBI integrates a 2K-entry look-up table
with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write
access from the EEPROM Serial Management Interface (SMI), Media Independent Interface
Management (MIIM), or SPI Interface. Each of the table entries can be configured as a static entry. The
entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used to provide
Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The Extension GMAC1 and Extension GMAC2 of the RTL8367RBI implement dual RGMII/MII
interfaces. These interfaces could be connected to an external PHY, MAC, CPU, or RISC for specific
applications. In router applications, the RTL8367RBI supports Port VID (PVID) for each port to insert a
PVID in the VLAN tag on egress. When using this function, VID information carried in the VLAN tag
will be changed to PVID.
Note: The RTL8367RBI Extra Interface (Extension GMAC1 and Extension GMAC2) supports:
Dual-Port Reduced Gigabit Media Independent Interface (RGMII)
Dual-Port Media Independent Interface (MII)
The RTL8367RBI supports standard 802.3x flow control frames for full duplex, and optional
backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the
availability of system resources, including the packet buffers and transmitting queues. The RTL8367RBI
supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-
blocked ports only. For IP multicast applications, the RTL8367RBI supports IPv4 IGMPv1/v2/v3 and
IPv6 MLDv1/v2 snooping.
In order to support flexible traffic classification, the RTL8367RBI supports 96-entry ACL rule check and
multiple actions options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, force output tag format and rate policing. The rate policing mechanism supports from
8Kbps to 1Gbps (in 8Kbps steps).
In Bridge operation the RTL8367RBI supports 16 sets of port configurations: disable, block, learning,
and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and
management application requirements, the RTL8367RBI supports IEEE 802.1x Port-based/MAC-based
Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8367RBI provides a
Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
1
Track ID: JATR-8275-15 Rev. 1.0
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