library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sipo is port(d_in : in std_logic:='1'; clk : in std_logic; reset : in std_logic:='0'; d_out : out std_logic_vector(11 downto 0); data_flag: out std_logic:='0' ); end sipo; architecture a of sipo is signal q : std_logic_vector(11 downto 0); type work_type is (init,working); signal work_st : work_type:=init; begin -- process(clk,reset) variable data_cnt: integer range 15 downto 0:=0; begin if reset ='1' then q<= (others=> '0'); d_out <= (others=>'0'); data_cnt:=0; data_flag <= '0'; work_st <= init; elsif clk 'event and clk = '1' then q(0)<=d_in; for i in 11 downto 1 loop q(i)<=q(i-1); end loop; -- if work_st = init then if data_cnt /= 12 then data_cnt:=data_cnt+1; data_flag <= '0'; else data_flag <= '1'; d_out <= q; data_cnt:=0; work_st <= working; end if; else 

if data_cnt/=11 then data_cnt:= data_cnt+1; data_flag<= '0'; else data_flag <= '1' ; data_cnt := 0; d_out <= q; end if; end if; end if; end process; -- end a;