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MIPI_D-PHY_Specification_v1.00.00.pdf
MIPI Alliance Specification forD-PHY Version 1.00.00
Contents
Figures
Tables
1 Overview
1.1 Scope
1.2 Purpose
2 Terminology
2.1 Definitions
2.2 Abbreviations
2.3 Acronyms
3 D-PHY Introduction
3.1 Summary of PHY Functionality
3.2 Mandatory Functionality
4 Architecture
4.1 Lane Modules
4.2 Master and Slave
4.3 High Frequency Clock Generation
4.4 Clock Lane, Data Lanes and the PHY-Protocol Interface
4.5 Selectable Lane Options
4.6 Lane Module Types
4.6.1 Unidirectional Data Lane
4.6.2 Bi-directional Data Lanes
4.6.3 Clock Lane
4.7 Configurations
4.7.1 Unidirectional Configurations
4.7.2 Bi-Directional Half-Duplex Configurations
4.7.3 Mixed Data Lane Configurations
5 Global Operation
5.1 Transmission Data Structure
5.1.1 Data Units
5.1.2 Bit order, Serialization, and De-Serialization
5.1.3 Encoding and Decoding
5.1.4 Data Buffering
5.2 Lane States and Line Levels
5.3 Operating Modes: Control, High-Speed, and Escape
5.4 High-Speed Data Transmission
5.4.1 Burst Payload Data
5.4.2 Start-of-Transmission
5.4.3 End-of-Transmission
5.4.4 HS Data Transmission Burst
5.5 Bi-directional Data Lane Turnaround
5.6 Escape Mode
5.6.1 Remote Triggers
5.6.2 Low-Power Data Transmission
5.6.3 Ultra-Low Power State
5.6.4 Escape Mode State Machine
5.7 High-Speed Clock Transmission
5.8 Clock Lane Ultra-Low Power State
5.9 Global Operation Timing Parameters
5.10 System Power States
5.11 Initialization
5.12 Calibration
5.13 Global Operation Flow Diagram
5.14 Data Rate Dependent Parameters (informative)
5.14.1 Parameters Containing Only UI Values
5.14.2 Parameters Containing Time and UI values
5.14.3 Parameters Containing Only Time Values
5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent
6 Fault Detection
6.1 Contention Detection
6.2 Sequence Error Detection
6.2.1 SoT Error
6.2.2 SoT Sync Error
6.2.3 EoT Sync Error
6.2.4 Escape Mode Entry Command Error
6.2.5 LP Transmission Sync Error
6.2.6 False Control Error
6.3 Protocol Watchdog Timers (informative)
6.3.1 HS RX Timeout
6.3.2 HS TX Timeout
6.3.3 Escape Mode Timeout
6.3.4 Escape Mode Silence Timeout
6.3.5 Turnaround Errors
7 Interconnect and Lane Configuration
7.1 Lane Configuration
7.2 Boundary Conditions
7.3 Definitions
7.4 S-parameter Specifications
7.5 Characterization Conditions
7.6 Interconnect Specifications
7.6.1 Differential Characteristics
7.6.2 Common-mode Characteristics
7.6.3 Intra-Lane Cross-Coupling
7.6.4 Mode-Conversion Limits
7.6.5 Inter-Lane Cross-Coupling
7.6.6 Inter-Lane Static Skew
7.7 Driver and Receiver Characteristics
7.7.1 Differential Characteristics
7.7.2 Common-Mode Characteristics
7.7.3 Mode-Conversion Limits
7.7.4 Inter-Lane Matching
8 Electrical Characteristics
8.1 Driver Characteristics
8.1.1 High-Speed Transmitter
8.1.2 Low-Power Transmitter
8.2 Receiver Characteristics
8.2.1 High-Speed Receiver
8.2.2 Low-Power Receiver
8.3 Line Contention Detection
8.4 Input Characteristics
9 High-Speed Data-Clock Timing
9.1 High-Speed Clock Timing
9.2 Forward High-Speed Data Transmission Timing
9.2.1 Data-Clock Timing Specifications
9.3 Reverse High-Speed Data Transmission Timing
10 Regulatory Requirements
Annex A Logical PHY-Protocol Interface Description (informative)
A.1 Signal Description
A.2 High-Speed Transmit from the Master Side
A.3 High-Speed Receive at the Slave Side
A.4 High-Speed Transmit from the Slave Side
A.5 High-Speed Receive at the Master Side
A.6 Low-Power Data Transmission
A.7 Low-Power Data Reception
A.8 Turn-around
Annex B Interconnect Design Guidelines (informative)
B.1 Practical Distances
B.2 RF Frequency Bands: Interference
B.3 Transmission Line Design
B.4 Reference Layer
B.5 Printed-Circuit Board
B.6 Flex-foils
B.7 Series Resistance
B.8 Connectors
Annex C 8b9b Line Coding for D-PHY (normative)
C.1 Line Coding Features
C.1.1 Enabled Features for the Protocol
C.1.2 Enabled Features for the PHY
C.2 Coding Scheme
C.2.1 8b9b Coding Properties
C.2.2 Data Codes: Basic Code Set
C.2.3 Comma Codes: Unique Exception Codes
C.2.4 Control Codes: Regular Exception Codes
C.2.5 Complete Coding Scheme
C.3 Operation with the D-PHY
C.3.1 Payload: Data and Control
C.3.2 Details for HS Transmission
C.3.3 Details for LP Transmission
C.4 Error Signaling
C.5 Extended PPI
C.6 Complete Code Set
22-Sep-2009
MIPI Alliance Specification for
D-PHY
Version 1.00.00 – 14 May 2009
MIPI Board Approved 22 September 2009
* Caution to Implementers *
This document is a MIPI® Specification formally approved by the MIPI Alliance Board of Directors
per the process defined in the MIPI Alliance Bylaws. However, implementers should be aware of
the following:
It is the good faith expectation of the MIPI PHY Working Group that D-PHY v1.00.00 is stable and
robust. The MIPI Alliance currently recommends that any member companies considering
implementation of D-PHY base their work on this version of the specification (v1.00.00).
MIPI Alliance strongly recommends that member companies NOT implement previously adopted
D-PHY specification v0.65 or D-PHY specification v0.90 which are superseded by this version
(v1.00.00).
It is the good faith expectation of the MIPI PHY WG that there will be no significant functional
changes to the fundamental technology described in this specification.
The D-PHY specification requires that powered-up Lanes be initialized simultaneously. However,
some corresponding protocol specifications may not mention this fact. The D-PHY specification
will continue to describe this requirement until all corresponding protocol specifications are
updated.
Copyright © 2009 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.00.00 14-May-2009
MIPI Alliance Specification for D-PHY
MIPI Alliance Specification for D-PHY
Version 1.00.00 – 14 May 2009
MIPI Board Approved 22-Sep-2009
Further technical changes to this document are expected as work continues in the PHY Working Group
Copyright © 2007-2009 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.00.00 14-May-2009
MIPI Alliance Specification for D-PHY
NOTICE OF DISCLAIMER
The material contained herein is not a license, either expressly or impliedly, to any IPR owned or
controlled by any of the authors or developers of this material or MIPI®. The material contained herein is
provided on an “AS IS” basis and to the maximum extent permitted by applicable law, this material is
provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI
hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not
limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a
particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of
viruses, and of lack of negligence.
All materials contained herein are protected by copyright laws, and may not be reproduced, republished,
distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express
prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related
trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and
cannot be used without its express prior written permission.
ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH
REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL
ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT
OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL,
CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER
CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR
ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL,
WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH
DAMAGES.
Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is
further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the
contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;
and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance
with the contents of this Document. The use or implementation of the contents of this Document may
involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,
patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI
does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any
IPR or claims of IPR as respects the contents of this Document or otherwise.
Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to:
MIPI Alliance, Inc.
c/o IEEE-ISTO
445 Hoes Lane
Piscataway, NJ 08854
Attn: Board Secretary
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Version 1.00.00 14-May-2009
MIPI Alliance Specification for D-PHY
Contents
Draft Version 1.00.00 – 14 May 2009.............................................................................................................. i
1 Overview ............................................................................................................................................... 14
1.1
1.2
Scope ............................................................................................................................................. 14
Purpose .......................................................................................................................................... 15
2
Terminology .......................................................................................................................................... 16
2.1
2.2
2.3
Definitions ..................................................................................................................................... 16
Abbreviations ................................................................................................................................ 17
Acronyms ...................................................................................................................................... 17
3 D-PHY Introduction .............................................................................................................................. 20
3.1
Summary of PHY Functionality .................................................................................................... 20
3.2 Mandatory Functionality ............................................................................................................... 20
4 Architecture ........................................................................................................................................... 21
4.1
Lane Modules ................................................................................................................................ 21
4.2 Master and Slave ........................................................................................................................... 22
4.3
4.4
4.5
4.6
High Frequency Clock Generation ................................................................................................ 22
Clock Lane, Data Lanes and the PHY-Protocol Interface ............................................................. 22
Selectable Lane Options ................................................................................................................ 23
Lane Module Types ....................................................................................................................... 25
4.6.1
4.6.2
4.6.3
Unidirectional Data Lane ....................................................................................................... 26
Bi-directional Data Lanes ...................................................................................................... 26
Clock Lane ............................................................................................................................. 27
4.7
Configurations ............................................................................................................................... 27
4.7.1
4.7.2
Unidirectional Configurations ............................................................................................... 29
Bi-Directional Half-Duplex Configurations .......................................................................... 31
4.7.3 Mixed Data Lane Configurations .......................................................................................... 32
5 Global Operation ................................................................................................................................... 33
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MIPI Alliance Specification for D-PHY
5.1
Transmission Data Structure ......................................................................................................... 33
5.1.1
5.1.2
5.1.3
5.1.4
Data Units .............................................................................................................................. 33
Bit order, Serialization, and De-Serialization ........................................................................ 33
Encoding and Decoding ........................................................................................................ 33
Data Buffering ....................................................................................................................... 33
5.2
5.3
5.4
Lane States and Line Levels .......................................................................................................... 33
Operating Modes: Control, High-Speed, and Escape .................................................................... 34
High-Speed Data Transmission ..................................................................................................... 35
5.4.1
5.4.2
5.4.3
5.4.4
Burst Payload Data ................................................................................................................ 35
Start-of-Transmission ............................................................................................................ 35
End-of-Transmission ............................................................................................................. 36
HS Data Transmission Burst ................................................................................................. 36
5.5
5.6
Bi-directional Data Lane Turnaround ............................................................................................ 38
Escape Mode ................................................................................................................................. 41
5.6.1
5.6.2
5.6.3
5.6.4
Remote Triggers .................................................................................................................... 42
Low-Power Data Transmission ............................................................................................. 43
Ultra-Low Power State .......................................................................................................... 43
Escape Mode State Machine .................................................................................................. 43
5.7
5.8
5.9
High-Speed Clock Transmission ................................................................................................... 45
Clock Lane Ultra-Low Power State ............................................................................................... 50
Global Operation Timing Parameters ............................................................................................ 52
5.10 System Power States ...................................................................................................................... 56
5.11
Initialization ................................................................................................................................... 56
5.12 Calibration ..................................................................................................................................... 56
5.13 Global Operation Flow Diagram ................................................................................................... 57
5.14 Data Rate Dependent Parameters (informative) ............................................................................ 58
5.14.1
Parameters Containing Only UI Values ................................................................................ 59
5.14.2
Parameters Containing Time and UI values .......................................................................... 59
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5.14.3
Parameters Containing Only Time Values ............................................................................ 59
5.14.4
Parameters Containing Only Time Values That Are Not Data Rate Dependent ................... 60
6
Fault Detection ...................................................................................................................................... 61
6.1
6.2
Contention Detection ..................................................................................................................... 61
Sequence Error Detection .............................................................................................................. 61
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
SoT Error ............................................................................................................................... 62
SoT Sync Error ...................................................................................................................... 62
EoT Sync Error ...................................................................................................................... 62
Escape Mode Entry Command Error ..................................................................................... 62
LP Transmission Sync Error .................................................................................................. 62
False Control Error ................................................................................................................ 62
6.3
Protocol Watchdog Timers (informative) ...................................................................................... 62
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
HS RX Timeout ..................................................................................................................... 62
HS TX Timeout ..................................................................................................................... 62
Escape Mode Timeout ........................................................................................................... 62
Escape Mode Silence Timeout .............................................................................................. 63
Turnaround Errors ................................................................................................................. 63
7
Interconnect and Lane Configuration .................................................................................................... 64
7.1
7.2
7.3
7.4
7.5
7.6
Lane Configuration ........................................................................................................................ 64
Boundary Conditions ..................................................................................................................... 64
Definitions ..................................................................................................................................... 64
S-parameter Specifications ............................................................................................................ 65
Characterization Conditions .......................................................................................................... 65
Interconnect Specifications ........................................................................................................... 66
7.6.1
7.6.2
7.6.3
Differential Characteristics .................................................................................................... 66
Common-mode Characteristics.............................................................................................. 67
Intra-Lane Cross-Coupling .................................................................................................... 67
7.6.4 Mode-Conversion Limits ....................................................................................................... 67
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7.6.5
7.6.6
Inter-Lane Cross-Coupling .................................................................................................... 67
Inter-Lane Static Skew .......................................................................................................... 68
7.7
Driver and Receiver Characteristics .............................................................................................. 68
7.7.1
7.7.2
Differential Characteristics .................................................................................................... 68
Common-Mode Characteristics ............................................................................................. 69
7.7.3 Mode-Conversion Limits ....................................................................................................... 69
7.7.4
Inter-Lane Matching .............................................................................................................. 69
8
Electrical Characteristics ....................................................................................................................... 70
8.1
Driver Characteristics .................................................................................................................... 71
8.1.1
8.1.2
High-Speed Transmitter ........................................................................................................ 71
Low-Power Transmitter ......................................................................................................... 75
8.2
Receiver Characteristics ................................................................................................................ 80
8.2.1
8.2.2
High-Speed Receiver ............................................................................................................. 80
Low-Power Receiver ............................................................................................................. 82
8.3
8.4
Line Contention Detection ............................................................................................................ 83
Input Characteristics ...................................................................................................................... 84
9 High-Speed Data-Clock Timing ............................................................................................................ 86
9.1
9.2
High-Speed Clock Timing ............................................................................................................. 86
Forward High-Speed Data Transmission Timing .......................................................................... 87
9.2.1
Data-Clock Timing Specifications ........................................................................................ 88
9.3
Reverse High-Speed Data Transmission Timing .......................................................................... 89
10
Regulatory Requirements .................................................................................................................. 91
Annex A Logical PHY-Protocol Interface Description (informative) .......................................................... 92
A.1
Signal Description ......................................................................................................................... 92
A.2 High-Speed Transmit from the Master Side ................................................................................ 100
A.3 High-Speed Receive at the Slave Side ........................................................................................ 100
A.4 High-Speed Transmit from the Slave Side .................................................................................. 101
A.5 High-Speed Receive at the Master Side ...................................................................................... 101
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A.6
A.7
A.8
Low-Power Data Transmission ................................................................................................... 102
Low-Power Data Reception ........................................................................................................ 103
Turn-around ................................................................................................................................. 103
Annex B Interconnect Design Guidelines (informative) ............................................................................. 105
B.1
Practical Distances ....................................................................................................................... 105
B.2 RF Frequency Bands: Interference .............................................................................................. 105
B.3
Transmission Line Design ........................................................................................................... 105
B.4 Reference Layer ........................................................................................................................... 106
B.5
B.6
B.7
Printed-Circuit Board .................................................................................................................. 106
Flex-foils ..................................................................................................................................... 106
Series Resistance ......................................................................................................................... 106
B.8 Connectors ................................................................................................................................... 106
Annex C 8b9b Line Coding for D-PHY (normative) .................................................................................. 107
C.1
Line Coding Features .................................................................................................................. 108
C.1.1
Enabled Features for the Protocol ....................................................................................... 108
C.1.2
Enabled Features for the PHY ............................................................................................. 108
C.2 Coding Scheme ............................................................................................................................ 108
C.2.1
8b9b Coding Properties ....................................................................................................... 108
C.2.2
Data Codes: Basic Code Set ................................................................................................ 109
C.2.3
Comma Codes: Unique Exception Codes ............................................................................ 110
C.2.4
Control Codes: Regular Exception Codes ........................................................................... 110
C.2.5
Complete Coding Scheme ................................................................................................... 111
C.3 Operation with the D-PHY .......................................................................................................... 111
C.3.1
Payload: Data and Control ................................................................................................... 111
C.3.2
Details for HS Transmission ................................................................................................ 112
C.3.3
Details for LP Transmission ................................................................................................ 112
C.4
C.5
Error Signaling ............................................................................................................................ 113
Extended PPI ............................................................................................................................... 113
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