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小米平板2原厂维修图纸(小米平板2 原理图 电路图).pdf
5544332211DDCCBBAA01020304050607080910111213141516171819202122232425262728293031323334353601_BT&WIFI_INTERFACE02_BT&WIFI_RF103_BT&WIFI_RF204_BT&WIFI_SUPPLY05_GPS06_SOC_LPDDR3 CH007_SOC_LPDDR3 CH108_SOC_DISPLAY CAMERA09_SOC_STORAGE I2S10_SOC_USB I2C GPIO11_SOC_UART SPI GPIO12_SOC_GND13_SOC_POWER 114_SOC_POWER 215_SOC_DECOUPLING16_SOC_SIGNALS17_PMU118_PMU219_PMU320_PMU421_PMU522_EMMC23_DDR124_DDR225_LPDDR3 CH0 DE-CAP TERMI26_LPDDR3 CH1 DE-CAP TERMI27_LCD CONNECTOR28_SD CONNECTOR29_CHARGER30 SPI_FlASH31_SENSOR32_Fuel Gauge33_AUDIO34_CAMERA35_TYPE_C36_CHANGE_LISTTitleSizeDocument NumberRevDate:SheetofC036Wednesday, August 19, 2015TitleSizeDocument NumberRevDate:Sheetof<Doc><RevCode><Title>C036Wednesday, August 19, 2015TitleSizeDocument NumberRevDate:Sheetof<Doc><RevCode><Title>C036Wednesday, August 19, 2015 </div><div id='PreviewText_2' class='preview-text'>5544332211DDCCBBAABT/WIFI INTERFACEVIO_4356VDD_CLDO_1P2_4356oWL_DEV_EN10oPCIE_CLKREQ0_N9oPCIE_PERST_N8oWIFI_HOST_WAKE_N1,11oPCIE_TDP_4356oPCIE_TDN_4356oPCIE_REFCLKP_4356oPCIE_REFCLKN_4356oPCIE_RDP_4356oPCIE_RDN_4356oBT_DEV_WAKE_R11oBT_HOST_WAKE10oI2S_1_COMBO_CLK9oI2S_1_COMBO_TXD9oI2S_1_COMBO_RXD9oI2S_1_COMBO_FS9oBT_DEV_EN_R11oUART_BT_RTS11oUART_BT_CTS11oUART_BT_RXD11oUART_BT_TXD11oWIFI_SLPCLK11oPCIE_TX0_DN9oPCIE_TX0_DP9oPCIE_RX0_DN9oPCIE_RX0_DP9oPCIE_REFCLK0_DP11oPCIE_REFCLK0_DN11oWIFI_HOST_WAKE_N1,11oCWS_SYNC_PULSE10TitleSizeDocument NumberRevDate:SheetofBT&WIFI_INTERFACEP0.1A3A3136TitleSizeDocument NumberRevDate:SheetofBT&WIFI_INTERFACEP0.1A3A3136TitleSizeDocument NumberRevDate:SheetofBT&WIFI_INTERFACEP0.1A3A3136SH3PMIC_Shielding_A311J1519XM-217-XC-042-SP11U100-1BCM4356XKUBGSDIO_DATA_3C8SDIO_DATA_2B8SDIO_DATA_1C9SDIO_DATA_0B9SDIO_CMDA9SDIO_CLKA8GPIO_7E7BT_GPIO_5A7BT_GPIO_2A6BT_GPIO_3D7JTAG_SELD9GPIO_6F8GPIO_2F11GPIO_3G9GPIO_4H9GPIO_5F9WL_REG_ONA10GPIO_0G11GPIO_1F10BT_GPIO_4K4PCIE_CLKREQ_LD5PCIE_PERST_LC4PCIE_PLL_AVSSB5PCIE_PME_LC5GPIO_8F7GPIO_9E6BT_REG_OND10BT_UART_CTS_LL5BT_UART_RTS_LK5BT_UART_TXDJ5BT_UART_RXDH5BT_PCM_CLKM6BT_PCM_INJ4BT_PCM_OUTH4BT_PCM_SYNCK6BT_I2S_CLKJ6BT_I2S_DIG5BT_I2S_DOG6BT_I2S_WSL6BT_DEV_WAKEL4BT_HOST_WAKEJ3LPO_INF6PCIE_RXTX_AVDD1P2B2PCIE_PLL_AVDD1P2B3PCIE_RDNB1PCIE_RDPC1PCIE_REFCLKNA5PCIE_REFCLKPA4PCIE_RXTX_AVSSB4PCIE_TDNA3PCIE_TDPA2PCIE_TESTNC2PCIE_TESTPC3GPIO_10H12C105100N020110V±20%12J1542XM-217-XC-043-SP-211C107100P020125V ±5% 12TP3112TP0.3mm1SH4EMMC_Shielding_A311C109NM020112J1521XM-217-XC-042-SP11J1539XM-217-XC-035-SP11SH5Smart-PA_Shielding_A311J1523XM-217-XC-042-SP11J1541XM-217-XC-043-SP-211R1020R±5%020112SH6Codec_Shielding_A311J1518XM-217-XC-042-SP11J1546XM-217-XC-043-SP-211J1516XM-217-XC-042-SP11C102100N020110V±20%12C108NM020112SH7RF_Shielding_A311J1520XM-217-XC-042-SP11R100NM020112TP3170TP0.3mm1J1545XM-217-XC-043-SP-211R10110K.05020112J1522XM-217-XC-042-SP11TP3171TP0.3mm1L101600ohm±25%020112C103100N020110V±20%12TP3172TP0.3mm1J1544XM-217-XC-043-SP-211SH1DDR_Shielding_Frame_A311C1011uF02016.3V±20%12C106100P020125V ±5% 12R167NM020112TP3173TP0.3mm1C104100N020110V±20%12J1543XM-217-XC-043-SP-211SH2GPS_Shielding_A311C1001uF02016.3V±20%12J1540XM-217-XC-043-SP-211L100600ohm±25%020112 </div><div id='PreviewText_3' class='preview-text'>5544332211DDCCBBAAVDD_LDO_3P3_B_4356VDD_LDO_3P3_B_4356oWL_TX_A_CORE0_CAP2oWL_RX_G_CORE0_ETR2oRF_SW_CTRL02oRF_SW_CTRL12oRF_SW_CTRL42oRF_SW_CTRL52oRF_SW_CTRL62oWL_RX_A_CORE0_ETR2oWL_TX_G_CORE0_CAP2oWL_RX_A_CORE0_ETR2oWL_TX_A_CORE0_CAP2oRF_SW_CTRL12oRF_SW_CTRL02oRF_SW_CTRL72oRF_SW_CTRL42oRF_SW_CTRL62oWL_TX_G_CORE0_CAP2oWL_RX_G_CORE0_ETR2oRF_SW_CTRL22oRF_SW_CTRL52oBT_TX4oRF_SW_CTRL22oRF_SW_CTRL72TitleSizeDocument NumberRevDate:SheetofBT&WIFI_RF1P0.1A3'A2236TitleSizeDocument NumberRevDate:SheetofBT&WIFI_RF1P0.1A3'A2236TitleSizeDocument NumberRevDate:SheetofBT&WIFI_RF1P0.1A3'A2236C1311uF12J1547XM-217-XC-043-SP-111C11910pF020150V5%12C11127pF020150V5%12L112NM020112L1173.9nH±0.1nH020112C133100N020110V±20%12J1548XM-217-XC-043-SP-111R110220R±5%020112L1142.2nH±0.1nH0.6×0.3mm12L116NM020112C11022pF020150V5%12C11710pF020150V5%12J199MM8030-2610BIN1GND3OUT2GND4C20012P020125V ±5% 12C1242.7P020125V±0.25pF12C12210pF020150V5%12C132100N020110V±20%12C12110pF020150V5%12R1120R±5%040212U200SKY85203-11CTX1TX2GND3GND4RX5LEN6VDD7BT8GND9CBT10CRX11ANT12GND13L1152.2nH±0.1nH0.6×0.3mm12C12010pF020150V5%12Y10037.400MHz,8Q3747000111224433C115NM020112FL100LFD212G45DS3R345GND11COM2GND23HIGH4GND35LOW6L1115.1nH±3%0.6×0.3mm12C1264.7pF020150V+/-0.25pF12C1148.2pF020150V+/-0.5pF12S100SKY85608-11ANT1CRX2RX3LEN4VDD5CTX6GND7TX8GND9C12915pF020150V±5%12C1235.6P020125V±0.25pF12C1254.7pF020150V+/-0.25pF12C128NM040212C11810pF020150V5%12C11212P020125V ±5% 12L1103.7nH±0.1nH020112C11610pF020150V5%12U100-4BCM4356XKUBGWRF_GPIO_OUT_CORE0R4WRF_TSSI_A_CORE0U3WRF_RX2G_GND1P2_CORE0N3WRF_RX5G_GND1P2_CORE0V3WRF_VCO_GND1P2U6WRF_XTAL_INP12WRF_XTAL_OUTN12WRF_XTAL_GND1P2N11WRF_TX_GND1P2_CORE0P3WRF_RFOUT_2G_CORE0P1WRF_RFIN_2G_CORE0N1RF_SW_CTRL_0R7RF_SW_CTRL_1N8RF_SW_CTRL_2P9RF_SW_CTRL_3N7RF_SW_CTRL_4N5RF_SW_CTRL_5P7RF_SW_CTRL_6P5RF_SW_CTRL_7M8WRF_RFOUT_5G_CORE0U1WRF_RFIN_5G_CORE0V1L1133.3nH3.3nH±0.1nH020112C1138.2pF020150V+/-0.5pF12C1302.2P020125V±0.25pF12 </div><div id='PreviewText_4' class='preview-text'>5544332211DDCCBBAAVDD_LDO_3P3_B_4356VDD_LDO_3P3_B_4356oWL_TX_A_CORE1_CAP3oWL_RX_G_CORE1_ETR3oWL_RX_A_CORE1_ETR3oWL_TX_G_CORE1_CAP3oRF_SW_CTRL83oRF_SW_CTRL93oRF_SW_CTRL123oRF_SW_CTRL143oRF_SW_CTRL143oWL_RX_A_CORE1_ETR3oWL_TX_A_CORE1_CAP3oRF_SW_CTRL93oRF_SW_CTRL83oRF_SW_CTRL153oRF_SW_CTRL123oWL_TX_G_CORE1_CAP3oWL_RX_G_CORE1_ETR3oRF_SW_CTRL103oRF_SW_CTRL103oRF_SW_CTRL153TitleSizeDocument NumberRevDate:SheetofBT&WIFI_RF2P0.1A3A2336TitleSizeDocument NumberRevDate:SheetofBT&WIFI_RF2P0.1A3A2336TitleSizeDocument NumberRevDate:SheetofBT&WIFI_RF2P0.1A3A2336C15610pF020150V5%12C16010pF020150V5%12FL401LFD212G45DS3R345GND11COM2GND23HIGH4GND35LOW6S200SKY85608-11ANT1CRX2RX3LEN4VDD5CTX6GND7TX8GND9C164NM040212C15410pF020150V5%12C169100N020110V±20%12L1212.7nH±0.1nH0.6×0.3mm12C19910pF020150V5%12U100-5BCM4356XKUBGWRF_GPIO_OUT_CORE1R9WRF_TSSI_A_CORE1T11WRF_RX2G_GND1P2_CORE1T7WRF_RX5G_GND1P2_CORE1T12WRF_TX_GND1P2_CORE1T8WRF_RFOUT_2G_CORE1V8WRF_RFIN_2G_CORE1V7RF_SW_CTRL_8K12RF_SW_CTRL_9J11RF_SW_CTRL_10M12RF_SW_CTRL_11L9RF_SW_CTRL_12J9RF_SW_CTRL_13K10RF_SW_CTRL_14M10RF_SW_CTRL_15L8WRF_RFOUT_5G_CORE1V11WRF_RFIN_5G_CORE1V12C1718.2pF020150V+/-0.5pF12J1549XM-217-XC-043-SP-111C1538.2pF020150V+/-0.5pF12C170100N020110V±20%12L1192.7nH±0.1nH0.6×0.3mm12C1503.9P020125V±0.25pF12J1550XM-217-XC-043-SP-111C1614.7pF020150V+/-0.25pF12U300SKY85203-11CTX1TX2GND3GND4RX5LEN6VDD7BT8GND9CBT10CRX11ANT12GND13C15910pF020150V5%12C15810pF020150V5%12J401MM8030-2610BIN1GND3OUT2GND4C1672.2P020125V±0.25pF12R1500R±5%040212C15510pF020150V5%12C152NM020112C1664.7pF020150V+/-0.25pF12L1182.7nH±0.1nH0.6×0.3mm12C15710pF020150V5%12L1222.2nH±0.1nH0.6×0.3mm12L1253.9nH±0.1nH020112C1634.7pF020150V+/-0.25pF12C1518.2pF020150V+/-0.5pF12C1681uF12L1953.0nH±0.2nH040212C1624.7pF020150V+/-0.25pF12L1232.2nH±0.1nH0.6×0.3mm12L124NM020112L120NM020112 </div><div id='PreviewText_5' class='preview-text'>5544332211DDCCBBAABT/WIFI RF SUPPLYplace closed to b11/b12place closed to e12VDD_LDO_3P3_B_4356VSYS_4356VDD_CBUCK_1P5_4356VDD_LDO_3P3_4356VDD_CBUCK_1P5_4356VDD_LNLDO_1P2_4356VDD_CLDO_1P2_4356VDD_XTAL_LDO_1P2_4356VDD_CBUCK_1P5_4356VDD_LDO_3P3_B_4356VDD_LDO_3P3_B_4356BT_LDO_2P5_4356VDD_CLDO_1P2_4356VDD_LNLDO_1P2_4356VDD_LDO_3P3_4356VDD_LDO_3P3_B_4356BT_LDO_2P5_4356VDD_LNLDO_1P2_4356VIO_4356+VSYSVIO_4356+V1P8AoFM_RX_ANT33oBT_TX2TitleSizeDocument NumberRevDate:Sheetof04_BT&WIFI_SUPPLYP0.1A3A3436TitleSizeDocument NumberRevDate:Sheetof04_BT&WIFI_SUPPLYP0.1A3A3436TitleSizeDocument NumberRevDate:Sheetof04_BT&WIFI_SUPPLYP0.1A3A3436C175220N020110V±20%12TP3165TP0.3mm1C1864.7uF040210V+/-20%12U100-2BCM4356XKUBGSR_VDDBATA5VB11SR_VDDBATP5VB12LDO_VDDBAT5VE12WRF_XTAL_VDD1P5P11AVDD_BBPLLH7NC_C7C7NC_C6C6BT_VDDOK7VDDIOE10VDDIO_SDE8WRF_SYNTH_VBAT_VDD3P3V6WRF_XTAL_VDD1P2N10WRF_MMD_VDD1P2T5WRF_PFD_VDD1P2T4VDDC_B7B7VDDC_D4D4VDDC_E9E9VDDC_G10G10VDDC_J12J12VDDC_J8J8VDDC_L10L10VDDC_M7M7VDDC_H3H3VDDC_M5M5VDDC_E4E4WRF_BUCK_VDD1P5_CORE0U4WRF_BUCK_VDD1P5_CORE1R11WRF_AFE_GND1P2_CORE0P4WRF_BUCK_GND1P5_CORE0V4WRF_BUCK_GND1P5_CORE1R12WRF_CP_GND1P2V5WRF_LNA_2G_GND1P2_CORE0N2WRF_LNA_2G_GND1P2_CORE1U7WRF_LNA_5G_GND1P2_CORE0V2WRF_LNA_5G_GND1P2_CORE1U12WRF_LOGEN_GND1P2R6WRF_LOGENG_GND1P2R5WRF_MMD_GND1P2T6VDDIO_RFH11VOUT_3P3F12VOUT_LDO3P3_BE11VOUT_BTLDO2P5D12VOUT_CLDOC11VOUT_LNLDOD11SR_VLXA11LDO_VDD1P5C12WRF_PA2G_VBAT_VDD3P3_CORE0R1WRF_PA5G_VBAT_VDD3P3_CORE0T1WRF_PADRV_VBAT_VDD3P3_CORE0R3WRF_PA2G_VBAT_VDD3P3_CORE1V9WRF_PA5G_VBAT_VDD3P3_CORE1V10WRF_PADRV_VBAT_VDD3P3_CORE1T9WRF_PADRV_VBAT_GND3P3_CORE0T3WRF_PADRV_VBAT_GND3P3_CORE1T10WRF_AFE_GND1P2_CORE1R8WRF_PA2G_VBAT_GND3P3_CORE0_P2P2WRF_PA2G_VBAT_GND3P3_CORE0_R2R2WRF_PA2G_VBAT_GND3P3_CORE1_U9U9WRF_PA2G_VBAT_GND3P3_CORE1_U8U8WRF_PA5G_VBAT_GND3P3_CORE0_T2T2WRF_PA5G_VBAT_GND3P3_CORE0_U2U2WRF_PA5G_VBAT_GND3P3_CORE1_U11U11WRF_PA5G_VBAT_GND3P3_CORE1_U10U10WRF_PFD_GND1P2U5AVSS_BBPLLG7PMU_AVSSB10SR_PVSSA12VSSC_C10C10VSSC_D3D3VSSC_G12G12VSSC_G8G8VSSC_G4G4VSSC_L11L11VSSC_L7L7VSSC_M4M4VSSC_D6D6NC_B6B6C19210pF020150V5%12C1912.2uF020110V+/-20%12TP3166TP0.3mm1C1832.2uF040216V±20%12C19310pF020150V5%12R1300R±5%020112L129600ohm±25%020112R1310R±5%040212C19510pF020150V5%12C1852.2uF040216V±20%12C194100N020110V±20%12L131600ohm±25%020112C1844.7uF040210V+/-20%12L128NM020112C1771uF02016.3V±20%12L130NM040212C196100N020110V±20%12C1824.7uF040210V+/-20%12C176100N020110V±20%12L1262.2uH2.2uH±30%2.0 ×1.6mm12C1802.2uF02016.3V±20%12R4500R±5%020112C1882.2uF020110V+/-20%12C1874.7uF040210V+/-20%12C1724.7UF040210V±20%12C179100N020110V±20%12C1812.2uF02016.3V±20%12C1781.5N020116V±10%12C1892.2uF020110V+/-20%12C1734.7UF040210V±20%12U100-3BCM4356XKUBGBT_RFL1BT_PAVDD2P5M1BT_IFVDD1P2K3BT_LNAVDD1P2K1BT_PLLVDD1P2K2BT_VCOVDD1P2J1BT_PAVSSL2BT_IFVSSM3BT_PLLVSSL3FM_LNAVSSH2CLK_REQF4BT_USB_DNE5BT_USB_DPF5FM_RFINH1FM_LNAVCOVDD1P2G1FM_PLLVDD1P2F3FM_AUDIOVDD1P2E2FM_AUDIOVSSF2FM_VCOVSSG2FM_PLLVSSG3BT_VCOVSSJ2FM_AOUT1E1FM_AOUT2F1C1902.2uF020110V+/-20%12 </div><div id='PreviewText_6' class='preview-text'>5544332211DDCCBBAAGPSGPS_VDDAUXGPS_VDDAUX+VSYS+V1P8A_GPSGPS_VDDAUX+V1P8A_GPSVSYS_GPS+V1P8A+V1P8A_GPSoGPS_WAKEUP_R11oUART_GPS_RXD11oUART_GPS_TXD11oUART_GPS_RTS11oUART_GPS_CTS11oGPS_LNA_EN5oGPS_SLP_CLK11oGPS_HOST_WAKE9oGPS_LNA_EN5oLSM6DS33_INT110,31TitleSizeDocument NumberRevDate:SheetofGPSP0.1A3A3536TitleSizeDocument NumberRevDate:SheetofGPSP0.1A3A3536TitleSizeDocument NumberRevDate:SheetofGPSP0.1A3A3536FL502_NMSAFFB1G56KB0F0AIN1OUT4GND23GND12GND35J501_NMMM8030-2610BIN1GND3OUT2GND4C557NM020112TP5081FL501_NMSAFFB1G56KB0F0AIN1OUT4GND23GND12GND35TP5101C516NM020112L505NM020112U517_NMBGU8019GND1VCC2RF_OUT3GNDRF4RF_IN5ENABLE6C555NM020112C512NM020112Y501_NMENA3654COUTPUT3VCC4GND1GND2R521NM020112TP5021L500NM020112C511NM020112C517NM040212R526NM040212C510NM020112C558NM020112C501NM020112C515NM020112C556NM020112TP5071L504NM040212L502NM040212TP5011R503NM040212C514NM020112C519NM020112R1532NM020112C509NM020112J1537_NMXM-217-XC-028-SP-111R527NM040212R588NM020112TP5091C518NM020112SYSTEM INTFHOST XPORTCLOCK INTFGPS RADIOPMU/POWER/GNDTEST MODEU500_NMBCM47531A1IUB2GCLK32B6GNSS_CALA6TCXO_INF4RF_INE6VDD1P8_AUXE3UART_RXD_SDAA1UART_NCTSB2UART_NRTS_HOST_REQB1UART_TXD_SCLA2LNA_ENC5IF_TEST_OUTD5VDD_LNAF6VDD_PMU_IND2VDD_IFF5VDD1P1_CORED1VDD_IOA4VDD_COREC1VSS_COREC4SYNC_PPSC6VSS_COREC3VSS_PMUD3IF_VALIDA3VDD1P2_GRFF2VSS_IFD6VSS_LNAE5NSTANDBYB3VDD_AUX_INF3TM0D4REF_CAPC2VSS_TSXE2HOST_WAKEA5RESERVED12B4RESERVED15B5RESERVED21E4RESERVED19F1RESERVED18E1 </div><div id='PreviewText_7' class='preview-text'>5544332211DDCCBBAASOC 1 OF 9+VDDR3_M0_OCAVREF+VDDR3_M0_ODQVREFoLPDDR3_M0_CA023,25oLPDDR3_M0_D0_A23oLPDDR3_M0_CA123,25oLPDDR3_M0_CA223,25oLPDDR3_M0_CA323,25oLPDDR3_M0_CA423,25oLPDDR3_M0_CA523,25oLPDDR3_M0_CA623,25oLPDDR3_M0_CA823,25oLPDDR3_M0_CA923,25oLPDDR3_M0_DM0_A23oLPDDR3_M0_DM1_A23oLPDDR3_M0_DM2_A23oLPDDR3_M0_DM3_A23oLPDDR3_M0_DM0_B23oLPDDR3_M0_DM1_B23oLPDDR3_M0_DM2_B23oLPDDR3_M0_DM3_B23oLPDDR3_M0_CKE0_A23oLPDDR3_M0_CKE1_A23oLPDDR3_M0_CKE0_B23oLPDDR3_M0_CKE1_B23oLPDDR3_M0_CA723,25oLPDDR3_M0_CS0_N23oLPDDR3_M0_CS1_N23oLPDDR3_M0_ODT_A23oLPDDR3_M0_ODT_B23oLPDDR3_M0_CLK_DP_A23,25oLPDDR3_M0_CLK_DN_A23,25oLPDDR3_M0_CLK_DP_B23,25oLPDDR3_M0_CLK_DN_B23,25oLPDDR3_M0_D1_A23oLPDDR3_M0_D2_A23oLPDDR3_M0_D3_A23oLPDDR3_M0_D4_A23oLPDDR3_M0_D5_A23oLPDDR3_M0_D6_A23oLPDDR3_M0_D7_A23oLPDDR3_M0_D8_A23oLPDDR3_M0_D9_A23oLPDDR3_M0_D10_A23oLPDDR3_M0_D11_A23oLPDDR3_M0_D12_A23oLPDDR3_M0_D13_A23oLPDDR3_M0_D14_A23oLPDDR3_M0_D15_A23oLPDDR3_M0_D16_A23oLPDDR3_M0_D17_A23oLPDDR3_M0_D18_A23oLPDDR3_M0_D19_A23oLPDDR3_M0_D20_A23oLPDDR3_M0_D21_A23oLPDDR3_M0_D22_A23oLPDDR3_M0_D23_A23oLPDDR3_M0_D24_A23oLPDDR3_M0_D25_A23oLPDDR3_M0_D26_A23oLPDDR3_M0_D27_A23oLPDDR3_M0_D28_A23oLPDDR3_M0_D29_A23oLPDDR3_M0_D30_A23oLPDDR3_M0_D31_A23oLPDDR3_M0_DQS0_P_A23oLPDDR3_M0_DQS0_N_A23oLPDDR3_M0_DQS1_P_A23oLPDDR3_M0_DQS1_N_A23oLPDDR3_M0_DQS2_P_A23oLPDDR3_M0_DQS2_N_A23oLPDDR3_M0_DQS3_P_A23oLPDDR3_M0_DQS3_N_A23oLPDDR3_M0_DQS0_P_B23oLPDDR3_M0_DQS0_N_B23oLPDDR3_M0_DQS1_P_B23oLPDDR3_M0_DQS1_N_B23oLPDDR3_M0_DQS2_P_B23oLPDDR3_M0_DQS2_N_B23oLPDDR3_M0_DQS3_P_B23oLPDDR3_M0_DQS3_N_B23oDRAMPWROK20oVCCAPWROK20oLPDDR3_M0_D0_B23oLPDDR3_M0_D1_B23oLPDDR3_M0_D2_B23oLPDDR3_M0_D3_B23oLPDDR3_M0_D4_B23oLPDDR3_M0_D5_B23oLPDDR3_M0_D6_B23oLPDDR3_M0_D7_B23oLPDDR3_M0_D8_B23oLPDDR3_M0_D9_B23oLPDDR3_M0_D10_B23oLPDDR3_M0_D11_B23oLPDDR3_M0_D12_B23oLPDDR3_M0_D13_B23oLPDDR3_M0_D14_B23oLPDDR3_M0_D15_B23oLPDDR3_M0_D16_B23oLPDDR3_M0_D17_B23oLPDDR3_M0_D18_B23oLPDDR3_M0_D19_B23oLPDDR3_M0_D20_B23oLPDDR3_M0_D21_B23oLPDDR3_M0_D22_B23oLPDDR3_M0_D23_B23oLPDDR3_M0_D24_B23oLPDDR3_M0_D25_B23oLPDDR3_M0_D26_B23oLPDDR3_M0_D27_B23oLPDDR3_M0_D28_B23oLPDDR3_M0_D29_B23oLPDDR3_M0_D30_B23oLPDDR3_M0_D31_B23TitleSizeDocument NumberRevDate:SheetofSOC_LPDDR3 CH0P0.1A3A3636Wednesday, August 19, 2015TitleSizeDocument NumberRevDate:SheetofSOC_LPDDR3 CH0P0.1A3A3636Wednesday, August 19, 2015TitleSizeDocument NumberRevDate:SheetofSOC_LPDDR3 CH0P0.1A3A3636Wednesday, August 19, 2015MEMORY-CH0U800-1Z8700LPDDR3_M0_CA0L49LPDDR3_M0_CA1M50LPDDR3_M0_CA2P48LPDDR3_M0_CA3L51LPDDR3_M0_CA4M54LPDDR3_M0_CA5L55LPDDR3_M0_CA6N51RSVD9R49LPDDR3_M0_CA8T52RSVD10P50RSVD11M48RSVD12L53RSVD13R51LPDDR3_M0_CA9R53RSVD14J55RSVD15H54LPDDR3_M0_DM0_AM46LPDDR3_M0_DM1_AG47LPDDR3_M0_DM2_AF46LPDDR3_M0_DM3_AE49LPDDR3_M0_DM0_BU55LPDDR3_M0_DM1_BAF56LPDDR3_M0_DM2_BAB50LPDDR3_M0_DM3_BAB48RSVD18G55RSVD7E55RSVD19F54RSVD5F56LPDDR3_M0_CA7L57RSVD6G57LPDDR3_M0_CS0*J57LPDDR3_M0_CS1*B56LPDDR3_M0_CKE0_AH58LPDDR3_M0_CKE1_AC57LPDDR3_M0_CKE0_BK56LPDDR3_M0_CKE1_BD58LPDDR3_M0_ODT_AB54LPDDR3_M0_ODT_BC55LPDDR3_M0_CK_P_AN57LPDDR3_M0_CK_N_AN55LPDDR3_M0_CK_P_BP56LPDDR3_M0_CK_N_BP54RSVD8E57LPDDR3_DRAM_PWROKAK49LPDDR3_CORE_PWROKAK51LPDDR3_M0_RCOMPPDAD44LPDDR3_M0_ODQVREFT50LPDDR3_M0_OCAVREFT48RSVD17AF45RSVD16AH46LPDDR3_M0_DQ0_AK42LPDDR3_M0_DQ1_AL43LPDDR3_M0_DQ2_AH42LPDDR3_M0_DQ3_AG43LPDDR3_M0_DQ4_AJ43LPDDR3_M0_DQ5_AK44LPDDR3_M0_DQ6_AM44LPDDR3_M0_DQ7_AJ45LPDDR3_M0_DQ8_AL47LPDDR3_M0_DQ9_AH48LPDDR3_M0_DQ10_AG49LPDDR3_M0_DQ11_AH52LPDDR3_M0_DQ12_AK52LPDDR3_M0_DQ13_AJ53LPDDR3_M0_DQ14_AJ49LPDDR3_M0_DQ15_AJ51LPDDR3_M0_DQ16_AF44LPDDR3_M0_DQ17_AB42LPDDR3_M0_DQ18_AE43LPDDR3_M0_DQ19_AF42LPDDR3_M0_DQ20_AE45LPDDR3_M0_DQ21_AD44LPDDR3_M0_DQ22_AC43LPDDR3_M0_DQ23_AC45LPDDR3_M0_DQ24_AE47LPDDR3_M0_DQ25_AC49LPDDR3_M0_DQ26_AD48LPDDR3_M0_DQ27_AD52LPDDR3_M0_DQ28_AF50LPDDR3_M0_DQ29_AE51LPDDR3_M0_DQ30_AC53LPDDR3_M0_DQ31_AF52LPDDR3_M0_DQ0_BT54LPDDR3_M0_DQ1_BU57LPDDR3_M0_DQ2_BR55LPDDR3_M0_DQ3_BT58LPDDR3_M0_DQ4_BY54LPDDR3_M0_DQ5_BW57LPDDR3_M0_DQ6_BY58LPDDR3_M0_DQ7_BAA55LPDDR3_M0_DQ8_BAA57LPDDR3_M0_DQ9_BAB56LPDDR3_M0_DQ10_BAB54LPDDR3_M0_DQ11_BAG55LPDDR3_M0_DQ12_BAE55LPDDR3_M0_DQ13_BAC57LPDDR3_M0_DQ14_BAC55LPDDR3_M0_DQ15_BAG57LPDDR3_M0_DQ16_BW49LPDDR3_M0_DQ17_BV48LPDDR3_M0_DQ18_BAA51LPDDR3_M0_DQ19_BV50LPDDR3_M0_DQ20_BY48LPDDR3_M0_DQ21_BAA53LPDDR3_M0_DQ22_BY52LPDDR3_M0_DQ23_BAB52LPDDR3_M0_DQ24_BAH50LPDDR3_M0_DQ25_BAD48LPDDR3_M0_DQ26_BAD50LPDDR3_M0_DQ27_BAE53LPDDR3_M0_DQ28_BAH48LPDDR3_M0_DQ29_BAF48LPDDR3_M0_DQ30_BAE49LPDDR3_M0_DQ31_BAF52LPDDR3_M0_DQS0_P_AK46LPDDR3_M0_DQS0_N_AJ47LPDDR3_M0_DQS1_P_AH50LPDDR3_M0_DQS1_N_AG51LPDDR3_M0_DQS2_P_AB46LPDDR3_M0_DQS2_N_AC47LPDDR3_M0_DQS3_P_AB50LPDDR3_M0_DQS3_N_AC51LPDDR3_M0_DQS0_P_BW55LPDDR3_M0_DQS0_N_BV56LPDDR3_M0_DQS1_P_BAE57LPDDR3_M0_DQS1_N_BAD58LPDDR3_M0_DQS2_P_BY50LPDDR3_M0_DQS2_N_BW51LPDDR3_M0_DQS3_P_BAF50LPDDR3_M0_DQS3_N_BAE51R802182R±1%020112R800NM020112R801NM020112 </div><div id='PreviewText_8' class='preview-text'>5544332211DDCCBBAASOC 2 OF 9+VDDR3_M1_OCAVREF+VDDR3_M1_ODQVREFoLPDDR3_M1_CA024,26oLPDDR3_M1_CA124,26oLPDDR3_M1_CA224,26oLPDDR3_M1_CA324,26oLPDDR3_M1_CA424,26oLPDDR3_M1_CA524,26oLPDDR3_M1_CA624,26oLPDDR3_M1_CA824,26oLPDDR3_M1_CA924,26oLPDDR3_M1_DM2_B24oLPDDR3_M1_DM3_B24oLPDDR3_M1_DM0_A24oLPDDR3_M1_DM1_A24oLPDDR3_M1_DM2_A24oLPDDR3_M1_DM3_A24oLPDDR3_M1_CA724,26oLPDDR3_M1_DM0_B24oLPDDR3_M1_DM1_B24oLPDDR3_M1_CS0_N24oLPDDR3_M1_CS1_N24oLPDDR3_M1_CKE0_B24oLPDDR3_M1_CKE1_B24oLPDDR3_M1_CKE0_A24oLPDDR3_M1_CKE1_A24oLPDDR3_M1_CLK_DP_B24,26oLPDDR3_M1_CLK_DN_B24,26oLPDDR3_M1_CLK_DP_A24,26oLPDDR3_M1_CLK_DN_A24,26oLPDDR3_M1_ODT_B24oLPDDR3_M1_ODT_A24oLPDDR3_M1_D0_B24oLPDDR3_M1_D1_B24oLPDDR3_M1_D2_B24oLPDDR3_M1_D3_B24oLPDDR3_M1_D4_B24oLPDDR3_M1_D5_B24oLPDDR3_M1_D6_B24oLPDDR3_M1_D7_B24oLPDDR3_M1_D8_B24oLPDDR3_M1_D9_B24oLPDDR3_M1_D10_B24oLPDDR3_M1_D11_B24oLPDDR3_M1_D12_B24oLPDDR3_M1_D13_B24oLPDDR3_M1_D14_B24oLPDDR3_M1_D15_B24oLPDDR3_M1_D16_B24oLPDDR3_M1_D17_B24oLPDDR3_M1_D18_B24oLPDDR3_M1_D19_B24oLPDDR3_M1_D20_B24oLPDDR3_M1_D21_B24oLPDDR3_M1_D22_B24oLPDDR3_M1_D23_B24oLPDDR3_M1_D24_B24oLPDDR3_M1_D25_B24oLPDDR3_M1_D26_B24oLPDDR3_M1_D27_B24oLPDDR3_M1_D28_B24oLPDDR3_M1_D29_B24oLPDDR3_M1_D30_B24oLPDDR3_M1_D31_B24oLPDDR3_M1_D0_A24oLPDDR3_M1_D1_A24oLPDDR3_M1_D2_A24oLPDDR3_M1_D3_A24oLPDDR3_M1_D4_A24oLPDDR3_M1_D5_A24oLPDDR3_M1_D6_A24oLPDDR3_M1_D7_A24oLPDDR3_M1_D8_A24oLPDDR3_M1_D9_A24oLPDDR3_M1_D10_A24oLPDDR3_M1_D11_A24oLPDDR3_M1_D12_A24oLPDDR3_M1_D13_A24oLPDDR3_M1_D14_A24oLPDDR3_M1_D15_A24oLPDDR3_M1_D16_A24oLPDDR3_M1_D17_A24oLPDDR3_M1_D18_A24oLPDDR3_M1_D19_A24oLPDDR3_M1_D20_A24oLPDDR3_M1_D21_A24oLPDDR3_M1_D22_A24oLPDDR3_M1_D23_A24oLPDDR3_M1_D24_A24oLPDDR3_M1_D25_A24oLPDDR3_M1_D26_A24oLPDDR3_M1_D27_A24oLPDDR3_M1_D28_A24oLPDDR3_M1_D29_A24oLPDDR3_M1_D30_A24oLPDDR3_M1_D31_A24oLPDDR3_M1_DQS0_P_A24oLPDDR3_M1_DQS0_N_A24oLPDDR3_M1_DQS1_P_A24oLPDDR3_M1_DQS1_N_A24oLPDDR3_M1_DQS2_P_A24oLPDDR3_M1_DQS2_N_A24oLPDDR3_M1_DQS3_P_A24oLPDDR3_M1_DQS3_N_A24oLPDDR3_M1_DQS0_P_B24oLPDDR3_M1_DQS0_N_B24oLPDDR3_M1_DQS1_P_B24oLPDDR3_M1_DQS1_N_B24oLPDDR3_M1_DQS2_P_B24oLPDDR3_M1_DQS2_N_B24oLPDDR3_M1_DQS3_P_B24oLPDDR3_M1_DQS3_N_B24TitleSizeDocument NumberRevDate:SheetofSOC_LPDDR3 CH1P0.1<Title>A3736Wednesday, August 19, 2015TitleSizeDocument NumberRevDate:SheetofSOC_LPDDR3 CH1P0.1<Title>A3736Wednesday, August 19, 2015TitleSizeDocument NumberRevDate:SheetofSOC_LPDDR3 CH1P0.1<Title>A3736Wednesday, August 19, 2015MEMORY-CH1U800-2Z8700LPDDR3_M1_CA0BJ49LPDDR3_M1_CA1BH50LPDDR3_M1_CA2BF48LPDDR3_M1_CA3BJ51LPDDR3_M1_CA4BH54LPDDR3_M1_CA5BJ55LPDDR3_M1_CA6BG51RSVD24BE49LPDDR3_M1_CA8BD52RSVD25BF50RSVD26BH48RSVD27BJ53RSVD28BE51LPDDR3_M1_CA9BE53RSVD29BL55RSVD30BM54LPDDR3_M1_DM0_BBN47LPDDR3_M1_DM1_BBH46LPDDR3_M1_DM2_BBR49LPDDR3_M1_DM3_BBP46LPDDR3_M1_DM0_AAP56LPDDR3_M1_DM1_ABC55LPDDR3_M1_DM2_AAV48LPDDR3_M1_DM3_AAV50RSVD33BN55RSVD22BR55RSVD34BP54RSVD20BP56LPDDR3_M1_CA7BJ57RSVD21BN57LPDDR3_M1_CS0*BL57LPDDR3_M1_CS1*BV56LPDDR3_M1_CKE0_BBM58LPDDR3_M1_CKE1_BBU57LPDDR3_M1_CKE0_ABK56LPDDR3_M1_CKE1_ABT58LPDDR3_M1_ODT_BBV54LPDDR3_M1_ODT_ABU55LPDDR3_M1_CK_P_BBG57LPDDR3_M1_CK_N_BBG55LPDDR3_M1_CK_P_ABF56LPDDR3_M1_CK_N_ABF54RSVD23BR57LPDDR3_M1_RCOMPPDAP43LPDDR3_M1_ODQVREFBD50LPDDR3_M1_OCAVREFBD48RSVD32AP45RSVD31AM46LPDDR3_M1_DQ0_BBL51LPDDR3_M1_DQ1_BBL49LPDDR3_M1_DQ2_BBL53LPDDR3_M1_DQ3_BBK52LPDDR3_M1_DQ4_BBM52LPDDR3_M1_DQ5_BBN49LPDDR3_M1_DQ6_BBM48LPDDR3_M1_DQ7_BBJ47LPDDR3_M1_DQ8_BBL45LPDDR3_M1_DQ9_BBH44LPDDR3_M1_DQ10_BBK44LPDDR3_M1_DQ11_BBL43LPDDR3_M1_DQ12_BBN43LPDDR3_M1_DQ13_BBM42LPDDR3_M1_DQ14_BBJ43LPDDR3_M1_DQ15_BBK42LPDDR3_M1_DQ16_BBP52LPDDR3_M1_DQ17_BBU53LPDDR3_M1_DQ18_BBR51LPDDR3_M1_DQ19_BBP50LPDDR3_M1_DQ20_BBT52LPDDR3_M1_DQ21_BBT48LPDDR3_M1_DQ22_BBU49LPDDR3_M1_DQ23_BBR47LPDDR3_M1_DQ24_BBU45LPDDR3_M1_DQ25_BBU43LPDDR3_M1_DQ26_BBT44LPDDR3_M1_DQ27_BBR45LPDDR3_M1_DQ28_BBP42LPDDR3_M1_DQ29_BBR43LPDDR3_M1_DQ30_BBV42LPDDR3_M1_DQ31_BBP44LPDDR3_M1_DQ0_AAN57LPDDR3_M1_DQ1_AAU55LPDDR3_M1_DQ2_AAU57LPDDR3_M1_DQ3_AAR55LPDDR3_M1_DQ4_AAN55LPDDR3_M1_DQ5_AAV54LPDDR3_M1_DQ6_AAV56LPDDR3_M1_DQ7_AAW57LPDDR3_M1_DQ8_AAW55LPDDR3_M1_DQ9_AAY58LPDDR3_M1_DQ10_ABA57LPDDR3_M1_DQ11_AAY54LPDDR3_M1_DQ12_ABD58LPDDR3_M1_DQ13_ABE55LPDDR3_M1_DQ14_ABC57LPDDR3_M1_DQ15_ABD54LPDDR3_M1_DQ16_AAP52LPDDR3_M1_DQ17_AAR49LPDDR3_M1_DQ18_AAP48LPDDR3_M1_DQ19_AAM48LPDDR3_M1_DQ20_AAR53LPDDR3_M1_DQ21_AAT50LPDDR3_M1_DQ22_AAT48LPDDR3_M1_DQ23_AAM50LPDDR3_M1_DQ24_AAV52LPDDR3_M1_DQ25_AAY52LPDDR3_M1_DQ26_AAW53LPDDR3_M1_DQ27_AAY48LPDDR3_M1_DQ28_ABB50LPDDR3_M1_DQ29_AAW51LPDDR3_M1_DQ30_ABB48LPDDR3_M1_DQ31_ABA49LPDDR3_M1_DQS0_P_BBM50LPDDR3_M1_DQS0_N_BBN51LPDDR3_M1_DQS1_P_BBK46LPDDR3_M1_DQS1_N_BBL47LPDDR3_M1_DQS2_P_BBV50LPDDR3_M1_DQS2_N_BBU51LPDDR3_M1_DQS3_P_BBV46LPDDR3_M1_DQS3_N_BBU47LPDDR3_M1_DQS0_P_AAR57LPDDR3_M1_DQS0_N_AAT58LPDDR3_M1_DQS1_P_ABA55LPDDR3_M1_DQS1_N_ABB56LPDDR3_M1_DQS2_P_AAP50LPDDR3_M1_DQS2_N_AAR51LPDDR3_M1_DQS3_P_AAY50LPDDR3_M1_DQS3_N_ABA51R803182R±1%020112 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url: "/Res/_UpdateLookTimes?resId=3bc262aab5e14ff9b0b32a7738563049",
method: 'get',
dataType: 'json',
cache: false, //不保存缓存
success: function(data) {}
});
$('.tab-nav li a').click(function () {
$(".tab-item").hide();
$('[data-tab-item=' + $(this).attr("data-tab-target") + ']').show();
});
var articleBar = $('.article-bar')
$(window).scroll(function () {
var h = document.documentElement.scrollTop + document.body.scrollTop;
var contentHeight = $('.article-content').height();
if (h > 200 && h < contentHeight) {
articleBar.addClass("fixed");
$('.article-bar').css('width', $('.article-content').width());
$('.article-bar').css('margin-left', $('.article-content').offset().left);
}
else
{
articleBar.removeClass("fixed");
$('.article-bar').css('width', '');
$('.article-bar').css('margin-left','');
}
})
})
</script>
<!--Cached In 5/19/2024 4:52:51 AM-->
</body>
</html>