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IEEE 1801 UPF2.0.pdf
IEEE Standard for Design and Verification of Low Power Integrated Circuits
IEEE Std 1801-2009 title page
Introduction
Notice to users
Copyrights
Updating of IEEE documents
Errata
Interpretations
Patents
Participants
CONTENTS
Important Notice
1. Overview
1.1 Scope
1.2 Purpose
1.3 Key characteristics of the Unified Power Format (UPF)
1.4 Power supply network design intent
1.5 Extending logic specification
1.6 Conventions used
1.7 Use of color in this standard
1.8 Contents of this standard
2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions
3.2 Acronyms and abbreviations
4. Power domains, supply sets, name spaces, and precedence
4.1 Power domains
4.2 Supply nets and ports
4.3 Supply sets
4.3.1 Explicit connection of supply nets
4.3.2 Automatic connection of supply nets
4.3.3 Implicit connection of supply nets
4.3.4 Predefined supply set functions
4.4 Naming rules
4.5 Name space semantics
4.6 Attributes and HDLs
4.7 Precedence
4.8 Lexical elements
4.9 Units
4.10 Boolean expressions
5. Simulation semantics
5.1 Supply network creation
5.2 Supply network simulation semantics
5.2.1 Supply network initialization
5.2.2 Supply network update and evaluation
5.3 Power switch modeling
5.4 Power states
5.4.1 Power states of supply nets and ports
5.4.2 Power states of supply sets
5.4.3 Power states of power domains
5.4.4 Power states of systems and subsystems
5.5 Power state name spaces
5.6 Simstate simulation semantics
5.6.1 NORMAL
5.6.2 CORRUPT
5.6.3 CORRUPT_ON_ACTIVITY
5.6.4 CORRUPT_STATE_ON_CHANGE
5.6.5 CORRUPT_STATE_ON_ACTIVITY
5.6.6 NOT_NORMAL
5.7 Transitioning from one simstate state to another
5.7.1 Any state transition to CORRUPT
5.7.2 Any state transition to CORRUPT_ON_ACTIVITY
5.7.3 Any state transition to CORRUPT_STATE_ON_CHANGE
5.7.4 Any state transition to CORRUPT_STATE_ON_ACTIVITY
5.7.5 Any state transition to NORMAL
5.7.6 Any state transition to NOT_NORMAL
6. Commands
6.1 Conventions used
6.2 Generic UPF command semantics
6.3 effective_element_list semantics
6.3.1 Transitive TRUE
6.3.2 Result
6.4 Command refinement
6.5 Error handling
6.5.1 errorCode
6.5.2 errorInfo
6.6 add_domain_elements
6.7 add_port_state
6.8 add_power_state
6.9 add_pst_state
6.10 associate_supply_set
6.11 bind_checker
6.12 connect_logic_net
6.13 connect_supply_net
6.14 connect_supply_set
6.15 create_composite_domain
6.16 create_hdl2upf_vct
6.17 create_logic_net
6.18 create_logic_port
6.19 create_power_domain
6.20 create_power_switch
6.21 create_pst
6.22 create_supply_net
6.22.1 Supply net resolution
6.22.2 Resolutions methods
6.22.3 Supply nets defined in HDL
6.23 create_supply_port
6.24 create_supply_set
6.24.1 Predefined supply set functions
6.24.2 Referencing supply set functions
6.25 create_upf2hdl_vct
6.26 describe_state_transition
6.27 load_simstate_behavior
6.28 load_upf
6.29 load_upf_protected
6.30 map_isolation_cell
6.31 map_level_shifter_cell
6.32 map_power_switch
6.33 map_retention_cell
6.34 merge_power_domains
6.35 name_format
6.36 save_upf
6.37 set_design_attributes
6.38 set_design_top
6.39 set_domain_supply_net
6.40 set_isolation
6.41 set_isolation_control
6.42 set_level_shifter
6.43 set_partial_on_translation
6.44 set_pin_related_supply
6.45 set_port_attributes
6.46 set_power_switch
6.47 set_retention
6.48 set_retention_control
6.49 set_retention_elements
6.50 set_scope
6.51 set_simstate_behavior
6.52 upf_version
6.53 use_interface_cell
7. Queries
7.1 find_objects
7.1.1 Pattern matching and wildcarding
7.1.2 Wildcarding examples
7.2 query_upf
7.3 query_associate_supply_set
7.4 query_bind_checker
7.5 query_cell_instances
7.6 query_cell_mapped
7.7 query_composite_domain
7.8 query_design_attributes
7.9 query_hdl2upf_vct
7.10 query_isolation
7.11 query_isolation_control
7.12 query_level_shifter
7.13 query_map_isolation_cell
7.14 query_map_level_shifter_cell
7.15 query_map_power_switch
7.16 query_map_retention_cell
7.17 query_name_format
7.18 query_net_ports
7.19 query_partial_on_translation
7.20 query_pin_related_supply
7.21 query_port_attributes
7.22 query_port_direction
7.23 query_port_net
7.24 query_port_state
7.25 query_power_domain
7.26 query_power_domain_element
7.27 query_power_state
7.28 query_power_switch
7.29 query_pst
7.30 query_pst_state
7.31 query_retention
7.32 query_retention_control
7.33 query_retention_elements
7.34 query_simstate_behavior
7.35 query_state_transition
7.36 query_supply_net
7.37 query_supply_port
7.38 query_supply_set
7.39 query_upf2hdl_vct
7.40 query_use_interface_cell
8. Switching Activity Interchange Format (SAIF)
8.1 Syntactic conventions
8.2 Lexical conventions
8.2.1 White space
8.2.2 Comments
8.2.3 Numbers
8.2.4 Strings
8.2.5 Parenthesis
8.2.6 Operators
8.2.7 Hierarchical separator character
8.2.8 Identifiers
8.2.9 Keywords
8.2.10 Syntactic categories for token types
8.3 Backward SAIF file
8.3.1 SAIF file
8.3.2 Header
8.3.3 Simple timing attributes
8.3.4 Simple toggle attributes
8.3.5 State-dependent timing attributes
8.3.6 State-dependent toggle attributes
8.3.7 Path-dependent toggle attributes
8.3.8 SDPD toggle attributes
8.3.9 Net, port, and leakage switching specifications
8.3.10 Backward SAIF info and instance data
8.4 Library forward SAIF file
8.4.1 The SAIF file
8.4.2 State-dependent timing directive
8.4.3 State-dependent toggle directive
8.4.4 Path-dependent toggle directive
8.4.5 SDPD toggle directives
8.4.6 Module SDPD declarations
8.4.7 Library SDPD information
8.5 The RTL forward SAIF file
8.5.1 The SAIF file
8.5.2 Port and net mapping directives
8.5.3 Instance declarations
Annex A (informative) Bibliography
Annex B (normative) Supply net logic type
B.1 VHDL
B.2 SystemVerilog
Annex C (normative) Value conversion tables (VCTs)
C.1 VHDL_SL2UPF
C.2 UPF2VHDL_SL
C.3 VHDL_SL2UPF_GNDZERO
C.4 UPF_GNDZERO2VHDL_SL
C.5 SV_LOGIC2UPF
C.6 UPF2SV_LOGIC
C.7 SV_LOGIC2UPF_GNDZERO
C.8 UPF_GNDZERO2SV_LOGIC
C.9 VHDL_TIED_HI
C.10 SV_TIED_HI
C.11 VHDL_TIED_LO
C.12 SV_TIED_LO
Annex D (informative) UPF procs
Annex E (informative) De-rating factor for inertial glitch
IEEE Standard for
Design and Verification of
Low Power Integrated Circuits
IEEE Computer Society
Sponsored by the
Design Automation Standards Committee
and the
IEEE Standards Association Corporate Advisory Group
IEEE
3 Park Avenue
New York, NY 10016-5997, USA
IEEE Std 1801™-2009
M
T
1
0
8
1
27 March 2009
Authorized licensed use limited to: ST Microelectronics. Downloaded on May 27, 2009 at 11:23 from IEEE Xplore. Restrictions apply.
Authorized licensed use limited to: ST Microelectronics. Downloaded on May 27, 2009 at 11:23 from IEEE Xplore. Restrictions apply.
IEEE Std 1801™-2009
IEEE Standard for
Design and Verification of
Low Power Integrated Circuits
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Approved 19 March 2009
IEEE-SA Standards Board
Authorized licensed use limited to: ST Microelectronics. Downloaded on May 27, 2009 at 11:23 from IEEE Xplore. Restrictions apply.
Grateful acknowledgment is made to Accellera, Inc. for the permission to use the following source material:
Unified Power Format (UPF) Standard, Version 1.0
Abstract: The power supplied to elements in an electronic design affects the way circuits operate.
Although this is obvious when stated, today’s set of high-level design languages have not had a
consistent way to concisely represent the regions of a design with different power provisions, nor
the states of those regions or domains. This standard provides an HDL-independent way of
annotating a design with power intent. In addition, the level-shifting and isolation between power
domains may be described for a specific implementation, from high-level constraints to particular
configurations. When the logic in a power domain receives different power supply levels, the logic
state of portions of the design may be preserved with various state-retention strategies. This
standard provides mechanisms for the refined and specific description of intent, effect, and
implementation of various retention strategies. Incorporating components into designs is greatly
assisted by the encapsulation and specification of the characteristics of the power environment of
the design and the power requirements and capabilities of the components; this information
encapsulation mechanism is also described in this standard. The analysis of the various power
modes of a design is enabled with a combination of the description of the power modes and the
collection, generation, and propagation of switching information.
Keywords: corruption semantics, interface specification, IP reuse, isolation, level-shifting, power-
aware design, power intent, power domains, power modes, power states, progressive design
refinement, retention, retention strategies
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2009 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 27 March 2009. Printed in the United States of America.
Verilog is a registered trademark of Cadence Design Systems, Inc.
PDF:
Print:
ISBN 978-0-7381-5929-4 STD95919
ISBN 978-0-7381-5930-0 STDPD95919
No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior
written permission of the publisher.
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Introduction
This introduction is not part of IEEE Std 1801-2009, IEEE Standard for Design and Verification of Low Power
Integrated Circuits.
The purpose of this standard is to provide portable low power design specifications that can be used with a
variety of commercial products throughout an electronic system design, analysis, verification, and
implementation flow.
When the electronic design automation (EDA) industry began creating standards for use in specifying,
simulating and implementing functional specifications of digital electronic circuits in the 1980s, the primary
design constraint was the transistor area necessary to implement the required functionality in the prevailing
process technology at that time. Power considerations were simple and easily assumed for the design as
power consumption was not a major consideration and most chips operated on a single voltage for all
functionality. Therefore, hardware description languages (HDLs) such as VHDL (IEC/IEEE 61691-1-1)a
and Verilog (IEEE Std 1364™) [B2]b provided a rich set of capabilities necessary for capturing the
functional specification of electronic systems, but no capabilities for capturing the power architecture (how
each element of the system is to be powered).
As the process technology for manufacturing electronic circuits continued to advance, power (as a design
constraint) continually increased in importance. Even above the 90–100 nm process node size, dynamic
power consumption became an important design constraint as the functional size of designs increased power
consumption at the same time battery-operated mobile systems, such as cell phones and laptop computers,
became a significant driver of the electronics industry. Techniques for reducing dynamic power
consumption—the amount of power consumed to transition a node from a 0 to 1 state or vice
versa—became commonplace. Although these techniques affected the design methodology, the changes
were relatively easy to accommodate within the existing HDL-based design flow, as these techniques were
primarily focused on managing the clocking for the design (more clock domains operating at different
frequencies and gating of clocks when logic in a clock domain is not needed for the active operational
mode). Multi-voltage power management methods were also developed. These methods did not directly
impact the functionality of the design, requiring only level-shifters between different voltage domains.
Multi-voltage power domains could be verified in existing design flows with additional, straight-forward
extensions to the methodology.
With process technologies below 100 nm, static power consumption has become a prominent and, in many
cases, dominant design constraint. Due to the physics of the smaller process nodes, power is leaked from
transistors even when the circuitry is quiescent (no toggling of nodes from 0 to 1 or vice versa). New design
techniques were developed to manage static power consumption. Power gating or power shut-off turns off
power for a set of logic elements. Back bias techniques are used to raise the voltage threshold at which a
transistor can change its state. While back bias slows the performance of the transistor, it greatly reduces
leakage. These techniques are often combined with multi-voltages and require additional functionality:
power management controllers, isolation cells that logically and/or electrically isolate a shutdown power
domain from “powered-up” domains, level-shifters that translate signal voltages from one domain to
another, and retention registers to facilitate fast transition from a power-off state to a power-on state for a
domain.
The EDA industry responded with multiple vendors developing proprietary low power specification
capabilities for different tools in the design and implementation flow. Although this solved the problem
locally for a given tool, it was not a global solution in that the same information was often required to be
specified multiple times for different tools without portability of the power specification. At the Design
aInformation on references can be found in Clause 2.
bThe number in brackets correspond to those of the bibliography in Annex A.
iv
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Automation Conference (DAC) in June 2006, several semiconductor/electronics companies challenged the
EDA industry to define an open, portable power specification standard. The EDA industry standards
incubation consortium, Accellera, answered the call by creating a Technical SubCommittee (TSC) to
develop a standard. The effort was named Unified Power Format (UPF) to recognize the need of unifying
the capabilities of multiple proprietary formats into a single industry standard. Accellera approved UPF 1.0
as an Accellera standard in February 2007. In May 2007, Accellera donated UPF to the IEEE for the
purposes of creating an IEEE standard. The donation was executed to the P1801 working group and,
although this standard is the first version of what is formally titled the IEEE Standard for the Design and
Verification of Low Power Integrated Circuits, it represents the second version of what is more colloquially
referred to as UPF.
Notice to users
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Interpretations
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Patents
Attention is called to the possibility that implementation of this standard may require use of subject matter
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standard are expressly advised that determination of the validity of any patent rights, and the risk of
infringement of such rights, is entirely their own responsibility. Further information may be obtained from
the IEEE Standards Association.
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