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USB3.1 SPEC.pdf
Acknowledgement of Technical Contribution
1 Introduction
1.1 Background
1.2 Objective of the Specification
1.3 Scope of the Document
1.4 USB Product Compliance
1.5 Document Organization
1.6 Design Goals
1.7 Related Documents
2 Terms and Abbreviations
3 Architectural Overview
3.1 USB 3.1 System Description
3.1.1 USB 3.1 Physical Interface
3.1.1.1 USB 3.1 Mechanical
3.1.2 USB 3.1 Power
3.1.3 USB 3.1 System Configuration
3.1.4 USB 3.1 Architecture Summary
3.2 Enhanced SuperSpeed Bus Architecture
3.2.1 Physical Layer
3.2.1.1 Gen 1 Physical Layer
3.2.1.2 Gen 2 Physical Layer
3.2.2 Link Layer
3.2.3 Protocol Layer
3.2.3.1 SuperSpeed Protocol
3.2.3.2 SuperSpeedPlus Protocol
3.2.4 Robustness
3.2.4.1 Error Detection
3.2.4.2 Error Handling
3.2.5 Enhanced SuperSpeed Power Management
3.2.6 Devices
3.2.6.1 Peripheral Devices
3.2.6.2 Hubs
3.2.6.3 SuperSpeed Hub
3.2.6.4 SuperSpeedPlus Hub
3.2.7 Hosts
3.3 Enhanced SuperSpeed Bus Data Flow Models
4. Enhanced SuperSpeed Data Flow Model
4.1 Implementer Viewpoints
4.2 Enhanced SuperSpeed Communication Flow
4.2.1 Pipes
4.3 Enhanced SuperSpeed Protocol Overview
4.3.1 Differences from USB 2.0
4.3.1.1 Comparing USB 2.0 and Enhanced SuperSpeed Transactions
4.3.1.2 Introduction to Enhanced SuperSpeed Packets
4.4 Generalized Transfer Description
4.4.1 Data Bursting
4.4.2 IN Transfers
4.4.3 OUT Transfers
4.4.4 Power Management and Performance
4.4.5 Control Transfers
4.4.5.1 Control Transfer Packet Size
4.4.5.2 Control Transfer Bandwidth Requirements
4.4.5.3 Control Transfer Data Sequences
4.4.6 Bulk Transfers
4.4.6.1 Bulk Transfer Data Packet Size
4.4.6.2 Bulk Transfer Bandwidth Requirements
4.4.6.3 Bulk Transfer Data Sequences
4.4.6.4 Bulk Streams
4.4.7 Interrupt Transfers
4.4.7.1 Interrupt Transfer Packet Size
4.4.7.2 Interrupt Transfer Bandwidth Requirements
4.4.7.3 Interrupt Transfer Data Sequences
4.4.8 Isochronous Transfers
4.4.8.1 Isochronous Transfer Packet Size
4.4.8.2 Isochronous Transfer Bandwidth Requirements
4.4.8.3 Isochronous Transfer Data Sequences
4.4.8.4 Special Considerations for Isochronous Transfers
4.4.8.4.1 Explicit Feedback
4.4.9 Device Notifications
4.4.10 Reliability
4.4.10.1 Physical Layer
4.4.10.2 Link Layer
4.4.10.3 Protocol Layer
4.4.11 Efficiency
5 Mechanical
5.1 Objective
5.2 Significant Features
5.2.1 Connectors
5.2.1.1 USB 3.1 Standard-A Connector
5.2.1.2 USB 3.1 Standard-B Connector
5.2.1.3 USB 3.1 Micro-B Connector
5.2.1.4 USB 3.1 Micro-AB and USB 3.1 Micro-A Connectors
5.2.2 Allowed Cable Assemblies
5.2.3 Raw Cables
5.3 Connector Mating Interfaces
5.3.1 USB 3.1 Standard-A Connector
5.3.1.1 Interface Definition
5.3.1.2 USB 3.1 Standard-A Reference Footprints
5.3.1.3 Pin Assignments and Description
5.3.1.4 USB 3.1 Standard-A Connector Color Coding
5.3.2 USB 3.1 Standard-B Connector
5.3.2.1 Interface Definition
5.3.2.2 Pin Assignments and Description
5.3.3 USB 3.1 Micro Connector Family
5.3.3.1 Interfaces Definition
5.3.3.2 Pin Assignments and Description
5.4 Cable Construction and Wire Assignments
5.4.1 Cable Construction
5.4.2 Wire Assignments
5.4.3 Wire Gauges and Cable Diameters
5.5 Cable Assemblies
5.5.1 USB 3.1 Standard-A to USB 3.1 Standard-B Cable Assembly
5.5.2 USB 3.1 Standard-A to USB 3.1 Standard-A Cable Assembly
5.5.3 USB 3.1 Standard-A to USB 3.1 Micro-B Cable Assembly
5.5.4 USB 3.1 Micro-A to USB 3.1 Micro-B Cable Assembly
5.5.5 USB 3.1 Micro-A to USB 3.1 Standard-B Cable Assembly
5.5.6 USB 3.1 Icon Location
5.5.7 Cable Assembly Length
5.6 Electrical Requirements
5.6.1 Enhanced SuperSpeed Electrical Requirements
5.6.1.1 Raw Cable
5.6.1.1.1 Characteristic Impedance
5.6.1.1.2 Intra-Pair Skew
5.6.1.1.3 Differential Insertion Loss
5.6.1.2 Mated Connector Impedance
5.6.1.2.1 Mated Connector Impedance for Gen 2 Speed
5.6.1.3 Mated Cable Assemblies for Gen 2 speed
5.6.1.3.1 Design Targets
5.6.1.3.2 Normative Requirements
5.6.1.3.2.1 Test Fixtures
5.6.1.3.2.2 Reference Hosts and Devices
5.6.1.3.2.3 Channel Metrics
5.6.1.3.2.4 Pass/Fail Criteria
5.6.1.3.2.5 Differential Crosstalk between D+/D- and SuperSpeed Gen 2 Signal Pairs (EIA-360-90)
5.6.1.3.2.6 Differential to Common Mode Conversion
5.6.1.3.2.7 Cable Shielding Effectiveness
5.6.2 DC Electrical Requirements
5.6.2.1 Low Level Contact Resistance (EIA 364-23B)
5.6.2.2 Dielectric Strength (EIA 364-20)
5.6.2.3 Insulation Resistance (EIA 364-21)
5.6.2.4 Contact Current Rating (EIA 364-70, Method 2)
5.7 Mechanical and Environmental Requirements
5.7.1 Mechanical Requirements
5.7.1.1 Insertion Force (EIA 364-13)
5.7.1.2 Extraction Force Requirements (EIA 364-13)
5.7.1.2.1 Extraction Force (EIA 364-13, USB3.1 Standard Connector)
5.7.1.2.2 Extraction Force (EIA 364-13, USB 3.1 Micro Connector Family Only)
5.7.1.3 Durability or Insertion/Extraction Cycles (EIA 364-09)
5.7.1.4 Cable Flexing (EIA 364-41, Condition I)
5.7.1.5 Cable Pull-Out (EIA 364-38, Condition A)
5.7.1.6 Peel Strength (USB 3.1 Micro Connector Family Only)
5.7.1.7 4-Axes Continuity Test (USB 3.1 Micro Connector Family Only)
5.7.1.8 Wrenching Strength (Reference, USB 3.1 Micro Connector Family Only)
5.7.1.9 Lead Co-Planarity
5.7.1.10 Solderability
5.7.1.11 Restriction of Hazardous Substances (RoHS) Compliance
5.7.2 Environmental Requirements
5.7.3 Materials
5.8 Implementation Notes and Design Guides
5.8.1 Mated Connector Dimensions
5.8.2 EMI and RFI Management
5.8.3 Stacked Connectors
6 Physical Layer
6.1 Physical Layer Overview
6.2 Physical Layer Functions
6.2.1 Measurement Overview
6.2.2 Channel Overview
6.3 Symbol Encoding
6.3.1 Gen 1 Encoding
6.3.1.1 Serialization and Deserialization of Data
6.3.1.2 Normative 8b/10b Decode Rules for Gen 1 Operation
6.3.1.3 Gen 1 Data Scrambling
6.3.1.4 8b/10b Decode Errors for Gen 1 Operation
6.3.2 Gen 2 Encoding
6.3.2.1 Serialization and Deserialization of Data
6.3.2.2 Normative 128b/132b Decode Rules
6.3.2.3 Data Scrambling for Gen 2 Operation
6.3.2.4 128b/132b Decode Errors
6.3.3 Special Symbols for Framing and Link Management
6.4 Link Initialization and Training
6.4.1 Link Training
6.4.1.1 Gen 1 Operation
6.4.1.1.1 Normative Training Sequence Rules for Gen 1 Operation
6.4.1.1.2 Training Control Bits for Gen 1 Operation
6.4.1.1.3 Training Sequence Values for Gen 1 Operation
6.4.1.2 Gen 2 Operation
6.4.1.2.1 Normative Training Sequence Rules for Gen 2 Operation
6.4.1.2.2 Training Sequence Values for Gen 2 Operation
6.4.1.2.3 Training Control Bits for Gen 2 Operation
6.4.1.2.4 Informative Block Alignment for Gen 2 Operation
6.4.2 Lane Polarity Inversion
6.4.2.1 Gen 1 Operation
6.4.2.2 Gen 2 Operation
6.4.3 Elasticity Buffer and SKP Ordered Set
6.4.3.1 SKP Rules (Host/Device/Hub) for Gen 1 Operation
6.4.3.2 SKP Rules (Host/Device/Hub) for Gen 2 Operation:
6.4.4 Compliance Pattern
6.4.4.1 Gen 2 Compliance Pattern CP9
6.5 Clock and Jitter
6.5.1 Informative Jitter Budgeting
6.5.2 Normative Clock Recovery Function
6.5.3 Normative Spread Spectrum Clocking (SSC)
6.5.4 Normative Slew Rate Limit
6.6 Signaling
6.6.1 Eye Diagrams
6.6.2 Voltage Level Definitions
6.6.3 Tx and Rx Input Parasitics
6.7 Transmitter Specifications
6.7.1 Transmitter Electrical Parameters
6.7.2 Low Power Transmitter
6.7.3 Transmitter Eye
6.7.4 Tx Compliance Reference Receiver Equalize Function
6.7.5 Informative Transmitter De-emphasis
6.7.5.1 Gen 1 (5GT/s)
6.7.5.2 Gen 2 (10GT/s)
6.7.6 Entry into Electrical Idle, U1
6.8 Receiver Specifications
6.8.1 Receiver Equalization Training
6.8.2 Informative Receiver CTLE Function
6.8.2.1 Gen 1 Reference CTLE
6.8.2.2 Gen 2 Reference Equalizer Function
6.8.2.2.1 Reference CTLE
6.8.2.2.2 Reference DFE
6.8.3 Receiver Electrical Parameters
6.8.4 Receiver Loopback
6.8.4.1 Loopback BERT for Gen 1 Operation
6.8.5 Normative Receiver Tolerance Compliance Test
6.9 Low Frequency Periodic Signaling (LFPS)
6.9.1 LFPS Signal Definition
6.9.2 Example LFPS Handshake for U1/U2 Exit, Loopback Exit, and U3 Wakeup
6.9.3 Warm Reset
6.9.4 SuperSpeedPlus Capability Declaration
6.9.4.1 Binary Representation of Polling.LFPS
6.9.4.2 SCD1/SCD2 Definitions and Transmission
6.9.5 SuperSpeedPlus LFPS Based PWM Message (LBPM)
6.9.5.1 Introduction to LFPS Based PWM Signaling (LBPS)
6.9.5.2 LBPM Definition and Transmission
6.10 Transmitter and Receiver DC Specifications
6.10.1 Informative ESD Protection
6.10.2 Informative Short Circuit Requirements
6.10.3 Normative High Impedance Reflections
6.11 Receiver Detection
6.11.1 Rx Detect Overview
6.11.2 Rx Detect Sequence
6.11.3 Upper Limit on Channel Capacitance
6.12 Retimers
7 Link Layer
7.1 Byte Ordering
7.1.1 SuperSpeed USB Line Code
7.1.2 SuperSpeedPlus USB Line Code
7.2 Link Management and Flow Control
7.2.1 Packets and Packet Framing
7.2.1.1 Header Packet Structure
7.2.1.1.1 Header Packet Framing
7.2.1.1.2 Packet Header
7.2.1.1.3 Link Control Word
7.2.1.2 Data Packet Payload Structure
7.2.1.2.1 Data Packet Payload Framing
7.2.1.2.2 Data Packet Payload
7.2.1.2.3 Data Payload Structure and Spacing between DPH and DPP
7.2.1.3 SuperSpeedPlus Packet Placement
7.2.2 Link Commands
7.2.2.1 Link Command Structure
7.2.2.2 Link Command Word Definition
7.2.2.3 Link Command Placement
7.2.3 Logical Idle
7.2.4 Link Command Usage for Flow Control, Error Recovery, and Power Management
7.2.4.1 Header Packet Flow Control and Error Recovery
7.2.4.1.1 Initialization
7.2.4.1.2 General Rules of LGOOD_n and LCRD_x/LCRD1_x/LCRD2_x Usage
7.2.4.1.3 Transmitting Packets
7.2.4.1.4 Deferred DPH
7.2.4.1.5 Receiving Header Packets
7.2.4.1.6 Receiving Data Packet Header in SuperSpeedPlus Operation
7.2.4.1.7 SuperSpeed Rx Header Buffer Credit
7.2.4.1.8 SuperSpeedPlus Type 1/Type 2 Rx Buffer Credit
7.2.4.1.9 Receiving Data Packet Payload
7.2.4.1.10 Receiving LGOOD_n
7.2.4.1.11 Receiving LCRD_x/LCRD1_x/LCRD2_x
7.2.4.1.12 Receiving LBAD
7.2.4.1.13 Transmitter Timers
7.2.4.2 Link Power Management and Flow
7.2.4.2.1 Power Management Link Timers
7.2.4.2.2 Low Power Link State Initiation
7.2.4.2.3 U1/U2 Entry Flow
7.2.4.2.4 U3 Entry Flow
7.2.4.2.5 Concurrent Low Power Link Management Flow
7.2.4.2.6 Concurrent Low Power Link Management and Recovery Flow
7.2.4.2.7 Low Power Link State Exit Flow
7.3 Link Error Rules/Recovery
7.3.1 Overview of Enhanced SuperSpeed Bit Errors
7.3.2 Link Error Types, Detection, and Recovery
7.3.3 Link Error Statistics
7.3.3.1 Link Error Count
7.3.3.2 Soft Error Count
7.3.4 Header Packet Errors
7.3.4.1 Packet Framing Error
7.3.4.2 Header Packet Error
7.3.4.3 Rx Header Sequence Number Error
7.3.5 Link Command Errors
7.3.6 ACK Tx Header Sequence Number Error
7.3.7 Header Sequence Number Advertisement Error
7.3.8 SuperSpeed Rx Header Buffer Credit Advertisement Error
7.3.9 SuperSpeedPlus Type 1/Type 2 Rx Buffer Credit Advertisement Error
7.3.10 Training Sequence Error
7.3.11 SuperSpeed 8b/10b Errors
7.3.12 SuperSpeedPlus Block Header Errors
7.3.13 Summary of Error Types and Recovery
7.4 PowerOn Reset and Inband Reset
7.4.1 PowerOn Reset
7.4.2 Inband Reset
7.5 Link Training and Status State Machine (LTSSM)
7.5.1 eSS.Disabled
7.5.1.1 eSS.Disabled for Downstream Ports and Hub Upstream Ports
7.5.1.1.1 eSS.Disabled Requirements
7.5.1.1.2 Exit from eSS.Disabled
7.5.1.2 eSS.Disabled for Upstream Ports of Peripheral Devices
7.5.1.2.1 eSS.Disabled Substate Machine
7.5.1.2.2 eSS.Disabled Requirements
7.5.1.2.3 Exit from eSS.Disabled.Default
7.5.1.2.4 Exit from eSS.Disabled.Error
7.5.2 eSS.Inactive
7.5.2.1 eSS.Inactive Substate Machines
7.5.2.2 eSS.Inactive Requirements
7.5.2.3 eSS.Inactive.Quiet
7.5.2.3.1 eSS.Inactive.Quiet Requirements
7.5.2.3.2 Exit from eSS.Inactive.Quiet
7.5.2.4 eSS.Inactive.Disconnect.Detect
7.5.2.4.1 eSS.Inactive.Disconnect.Detect Requirements
7.5.2.4.2 Exit from eSS.Inactive.Disconnect.Detect
7.5.3 Rx.Detect
7.5.3.1 Rx.Detect Substate Machines
7.5.3.2 Rx.Detect Requirements
7.5.3.3 Rx.Detect.Reset
7.5.3.3.1 Rx.Detect.Reset Requirements
7.5.3.3.2 Exit from Rx.Detect.Reset
7.5.3.4 Rx.Detect.Active
7.5.3.5 Rx.Detect.Active Requirements
7.5.3.6 Exit from Rx.Detect.Active
7.5.3.7 Rx.Detect.Quiet
7.5.3.7.1 Rx.Detect.Quiet Requirements
7.5.3.7.2 Exit from Rx.Detect.Quiet
7.5.4 Polling
7.5.4.1 Polling Substate Machines
7.5.4.2 Polling Requirements
7.5.4.3 Polling.LFPS
7.5.4.3.1 Polling.LFPS Requirements
7.5.4.3.2 Exit from Polling.LFPS
7.5.4.4 Polling.LFPSPlus
7.5.4.4.1 Polling.LFPSPlus Requirements
7.5.4.4.2 Exit from Polling.LFPSPlus
7.5.4.5 Polling.PortMatch
7.5.4.5.1 PHY Capability LBPM Definition
7.5.4.5.2 Polling.PortMatch Requirements
7.5.4.5.3 Exit from Polling.PortMatch
7.5.4.6 Polling.PortConfig
7.5.4.6.1 Polling.PortConfig Requirements
7.5.4.6.2 Exit from Polling.PortConfig
7.5.4.7 Polling.RxEQ
7.5.4.7.1 Polling.RxEQ Requirements
7.5.4.7.2 Exit from Polling.RxEQ
7.5.4.8 Polling.Active
7.5.4.8.1 Polling.Active Requirements
7.5.4.8.2 Exit from Polling.Active
7.5.4.9 Polling.Configuration
7.5.4.9.1 Polling.Configuration Requirements
7.5.4.9.2 Exit from Polling.Configuration
7.5.4.10 Polling.Idle
7.5.4.10.1 Polling.Idle Requirements
7.5.4.10.2 Exit from Polling.Idle
7.5.5 Compliance Mode
7.5.5.1 Compliance Mode Requirements
7.5.5.2 Exit from Compliance Mode
7.5.6 U0
7.5.6.1 U0 Requirements
7.5.6.2 Exit from U0
7.5.7 U1
7.5.7.1 U1 Requirements
7.5.7.2 Exit from U1
7.5.8 U2
7.5.8.1 U2 Requirements
7.5.8.2 Exit from U2
7.5.9 U3
7.5.9.1 U3 Requirements
7.5.9.2 Exit from U3
7.5.10 Recovery
7.5.10.1 Recovery Substate Machines
7.5.10.2 Recovery Requirements
7.5.10.3 Recovery.Active
7.5.10.3.1 Recovery.Active Requirements
7.5.10.3.2 Exit from Recovery.Active
7.5.10.4 Recovery.Configuration
7.5.10.4.1 Recovery.Configuration Requirements
7.5.10.4.2 Exit from Recovery.Configuration
7.5.10.5 Recovery.Idle
7.5.10.5.1 Recovery.Idle Requirements
7.5.10.5.2 Exit from Recovery.Idle
7.5.11 Loopback
7.5.11.1 Loopback Substate Machines
7.5.11.2 Loopback Requirements
7.5.11.3 Loopback.Active
7.5.11.3.1 Loopback.Active Requirements
7.5.11.3.2 Exit from Loopback.Active
7.5.11.4 Loopback.Exit
7.5.11.4.1 Loopback.Exit Requirements
7.5.11.4.2 Exit from Loopback.Exit
7.5.12 Hot Reset
7.5.12.1 Hot Reset Substate Machines
7.5.12.2 Hot Reset Requirements
7.5.12.3 Hot Reset.Active
7.5.12.3.1 Hot Reset.Active Requirements
7.5.12.3.2 Exit from Hot Reset.Active
7.5.12.4 Hot Reset.Exit
7.5.12.4.1 Hot Reset.Exit Requirements
7.5.12.4.2 Exit from Hot Reset.Exit
8 Protocol Layer
8.1 Enhanced SuperSpeed Transactions
8.1.1 Transactions on a SuperSpeed Bus Instance
8.1.2 Transactions on a SuperSpeedPlus Bus Instance
8.1.2.1 Simultaneous IN Transactions
8.1.2.2 Transaction Reordering
8.2 Packet Types
8.3 Packet Formats
8.3.1 Fields Common to all Headers
8.3.1.1 Reserved Values and Reserved Field Handling
8.3.1.2 Type Field
8.3.1.3 CRC-16
8.3.1.4 Link Control Word
8.4 Link Management Packet (LMP)
8.4.1 Subtype Field
8.4.2 Set Link Function
8.4.3 U2 Inactivity Timeout
8.4.4 Vendor Device Test
8.4.5 Port Capabilities
8.4.6 Port Configuration
8.4.7 Port Configuration Response
8.4.8 Precision Time Measurement
8.4.8.1 PTM Bus Interval Boundary Counters
8.4.8.2 LDM Protocol
8.4.8.2.1 LDM Timestamp Exchange
8.4.8.2.2 PTM ITP Transfer
8.4.8.3 LDM State Machines
8.4.8.3.1 Requester Operation
8.4.8.3.1.1 Init Request
8.4.8.3.1.2 Init Response
8.4.8.3.1.3 Timestamp Request
8.4.8.3.1.4 Timestamp Response
8.4.8.3.1.5 LDM Disabled
8.4.8.3.2 Responder Operation
8.4.8.3.2.1 Responder Disabled
8.4.8.3.2.2 Timestamp Request
8.4.8.3.2.3 Timestamp Response
8.4.8.4 LDM Link Delay
8.4.8.4.1 Calculation
8.4.8.5 PTM Bus Interval Boundary Device Calculation
8.4.8.6 PTM Bus Interval Boundary Host Calculation
8.4.8.7 PTM Hub ITP Regeneration
8.4.8.8 Performance
8.4.8.9 LDM Rules
8.4.8.10 LDM and Hubs
8.4.8.11 Link Delay Measurement (LDM) LMP
8.5 Transaction Packet (TP)
8.5.1 Acknowledgement (ACK) Transaction Packet
8.5.2 Not Ready (NRDY) Transaction Packet
8.5.3 Endpoint Ready (ERDY) Transaction Packet
8.5.4 STATUS Transaction Packet
8.5.5 STALL Transaction Packet
8.5.6 Device Notification (DEV_NOTIFICATION) Transaction Packet
8.5.6.1 Function Wake Device Notification
8.5.6.2 Latency Tolerance Message (LTM) Device Notification
8.5.6.3 Bus Interval Adjustment Message Device Notification
8.5.6.4 Function Wake Notification
8.5.6.5 Latency Tolerance Messaging
8.5.6.5.1 Optional Normative LTM and BELT Requirements
8.5.6.6 Bus Interval Adjustment Message
8.5.6.7 Sublink Speed Device Notification
8.5.7 PING Transaction Packet
8.5.8 PING_RESPONSE Transaction Packet
8.6 Data Packet (DP)
8.7 Isochronous Timestamp Packet (ITP)
8.8 Addressing Triple
8.9 Route String Field
8.9.1 Route String Port Field
8.9.2 Route String Port Field Width
8.9.3 Port Number
8.10 Transaction Packet Usages
8.10.1 Flow Control Conditions
8.10.2 Burst Transactions
8.10.2.1 Enhanced SuperSpeed Burst Transactions
8.10.2.2 SuperSpeedPlus Burst Transactions
8.10.3 Short Packets
8.10.4 SuperSpeedPlus Transaction Reordering
8.11 TP or DP Responses
8.11.1 Device Response to TP Requesting Data
8.11.2 Host Response to Data Received from a Device
8.11.3 Device Response to Data Received from the Host
8.11.4 Device Response to a SETUP DP
8.12 TP Sequences
8.12.1 Bulk Transactions
8.12.1.1 State Machine Notation Information
8.12.1.2 Bulk IN Transactions
8.12.1.3 Bulk OUT Transactions
8.12.1.4 Bulk Streaming Protocol
8.12.1.4.1 Stream IDs
8.12.1.4.2 Device IN Stream Protocol
8.12.1.4.2.1 Disabled
8.12.1.4.2.2 Prime Pipe
8.12.1.4.2.3 Deferred Prime Pipe
8.12.1.4.2.4 Idle
8.12.1.4.2.5 Start Stream
8.12.1.4.2.6 Move Data
8.12.1.4.2.7 INMvData Device
8.12.1.4.2.8 INMvData Host
8.12.1.4.2.9 INMvData Device Terminate
8.12.1.4.2.10 INMvData Burst End
8.12.1.4.3 Device OUT Stream Protocol
8.12.1.4.3.1 Disabled
8.12.1.4.3.2 Prime Pipe
8.12.1.4.3.3 Deferred Prime Pipe
8.12.1.4.3.4 Idle
8.12.1.4.3.5 Start Stream
8.12.1.4.3.6 Start Stream End
8.12.1.4.3.7 Move Data
8.12.1.4.3.8 OUTMvData Device
8.12.1.4.3.9 OUTMvData Host
8.12.1.4.3.10 OUTMvData Host Terminate
8.12.1.4.4 Host IN Stream Protocol
8.12.1.4.4.1 Disabled
8.12.1.4.4.2 Prime Pipe
8.12.1.4.4.3 Idle
8.12.1.4.4.4 Start Stream
8.12.1.4.4.5 Move Data
8.12.1.4.4.6 INMvData Device
8.12.1.4.4.7 INMvData Host
8.12.1.4.4.8 INMvData Burst End
8.12.1.4.4.9 INMvData Device Terminate
8.12.1.4.5 Host OUT Stream Protocol
8.12.1.4.5.1 Disabled
8.12.1.4.5.2 Prime Pipe
8.12.1.4.5.3 Idle
8.12.1.4.5.4 Start Stream
8.12.1.4.5.5 Start Stream End
8.12.1.4.5.6 Move Data
8.12.1.4.5.7 OUTMvData Device
8.12.1.4.5.8 OUTMvData Host
8.12.1.4.5.9 OUTMvData Host Terminate
8.12.2 Control Transfers
8.12.2.1 Reporting Status Results
8.12.2.2 Variable-length Data Stage
8.12.2.3 STALL TPs Returned by Control Pipes
8.12.3 Bus Interval and Service Interval
8.12.4 Interrupt Transactions
8.12.4.1 Interrupt IN Transactions
8.12.4.2 Interrupt OUT Transactions
8.12.5 Host Timing Information
8.12.6 Isochronous Transactions
8.12.6.1 Enhanced SuperSpeed Isochronous Transactions
8.12.6.1.1 Smart Isochronous Scheduling Protocol
8.12.6.2 Host Flexibility in Performing SuperSpeed Isochronous Transactions
8.12.6.3 SuperSpeedPlus Isochronous Transactions
8.12.6.3.1 Pipelined Isochronous IN Transactions
8.12.6.4 Host Flexibility in Performing SuperSpeedPlus Isochronous Transactions
8.12.6.5 Device Response to Isochronous IN Transactions
8.12.6.6 Host Processing of Isochronous IN Transactions
8.12.6.7 Device Response to an Isochronous OUT Data Packet
8.13 Timing Parameters
9 Device Framework
9.1 USB Device States
9.1.1 Visible Device States
9.1.1.1 Attached
9.1.1.2 Powered
9.1.1.2.1 Far-end Receiver Termination Substate
9.1.1.2.2 Link Training Substate
9.1.1.3 Default
9.1.1.4 Address
9.1.1.5 Configured
9.1.1.6 Suspended
9.1.1.7 Error
9.1.2 Bus Enumeration
9.2 Generic Device Operations
9.2.1 Dynamic Attachment and Removal
9.2.2 Address Assignment
9.2.3 Configuration
9.2.4 Data Transfer
9.2.5 Power Management
9.2.5.1 Power Budgeting
9.2.5.2 Changing Device Suspend State
9.2.5.3 Function Suspend
9.2.5.4 Changing Function Suspend State
9.2.6 Request Processing
9.2.6.1 Request Processing Timing
9.2.6.2 Reset/Resume Recovery Time
9.2.6.3 Set Address Processing
9.2.6.4 Standard Device Requests
9.2.6.5 Class-specific Requests
9.2.6.6 Speed Dependent Descriptors
9.2.7 Request Error
9.3 USB Device Requests
9.3.1 bmRequestType
9.3.2 bRequest
9.3.3 wValue
9.3.4 wIndex
9.3.5 wLength
9.4 Standard Device Requests
9.4.1 Clear Feature
9.4.2 Get Configuration
9.4.3 Get Descriptor
9.4.4 Get Interface
9.4.5 Get Status
9.4.6 Set Address
9.4.7 Set Configuration
9.4.8 Set Descriptor
9.4.9 Set Feature
9.4.10 Set Interface
9.4.11 Set Isochronous Delay
9.4.12 Set SEL
9.4.13 Synch Frame
9.4.14 Events and Their Effect on Device Parameters
9.5 Descriptors
9.6 Standard USB Descriptor Definitions
9.6.1 Device
9.6.2 Binary Device Object Store (BOS)
9.6.2.1 USB 2.0 Extension
9.6.2.2 SuperSpeed USB Device Capability
9.6.2.3 Container ID
9.6.2.4 Platform Descriptor
9.6.2.5 SuperSpeedPlus USB Device Capability
9.6.2.6 Precision Time Measurement
9.6.3 Configuration
9.6.4 Interface Association
9.6.5 Interface
9.6.6 Endpoint
9.6.7 SuperSpeed Endpoint Companion
9.6.8 SuperSpeedPlus Isochronous Endpoint Companion
9.6.9 String
9.7 Device Class Definitions
9.7.1 Descriptors
9.7.2 Interface(s)
9.7.3 Requests
10 Hub, Host Downstream Port, and Device Upstream Port Specification
10.1 Hub Feature Summary
10.1.1 Connecting to an Enhanced SuperSpeed Capable Host
10.1.2 Connecting to a USB 2.0 Host
10.1.3 Hub Connectivity
10.1.3.1 Routing Information
10.1.3.2 SuperSpeed Hub Packet Signaling Connectivity
10.1.3.3 SuperSpeedPlus Hub Packet Routing
10.1.4 Resume Connectivity
10.1.5 Hub Fault Recovery Mechanisms
10.1.6 Hub Buffer Architecture
10.1.6.1 SuperSpeed Hub Buffer Architecture
10.1.6.1.1 SuperSpeed Hub Header Packet Buffer Architecture
10.1.6.1.2 Hub Data Buffer Architecture
10.1.6.2 SuperSpeedPlus Hub Buffer Architecture
10.2 Hub Power Management
10.2.1 Link States
10.2.2 Hub Downstream Port U1/U2 Timers
10.2.3 Downstream/Upstream Port Link State Transitions
10.3 Hub Downstream Facing Ports
10.3.1 Hub Downstream Facing Port State Descriptions
10.3.1.1 DSPORT.Powered-off
10.3.1.2 DSPORT.Disconnected (Waiting for eSS Connect)
10.3.1.3 DSPORT.Training
10.3.1.4 DSPORT.ERROR
10.3.1.5 DSPORT.Enabled
10.3.1.6 DSPORT.Resetting
10.3.1.7 DSPORT.Compliance
10.3.1.8 DSPORT.Loopback
10.3.1.9 DSPORT.Disabled
10.3.1.10 DSPORT.Powered-off-detect
10.3.1.11 DSPORT.Powered-off-reset
10.3.2 Disconnect Detect Mechanism
10.3.3 Labeling
10.4 Hub Downstream Facing Port Power Management
10.4.1 Downstream Facing Port PM Timers
10.4.2 Hub Downstream Facing Port State Descriptions
10.4.2.1 Enabled U0 States
10.4.2.2 Attempt U0 – U1 Transition
10.4.2.3 Attempt U0 – U2 Transition
10.4.2.4 Link in U1
10.4.2.5 Link in U2
10.4.2.6 Link in U3
10.5 Hub Upstream Facing Port
10.5.1 Upstream Facing Port State Descriptions
10.5.1.1 USPORT.Powered-off
10.5.1.2 USPORT.Powered-on
10.5.1.3 USPORT.Training
10.5.1.4 USPORT.Connected/Enabled
10.5.1.5 USPORT.Error
10.5.2 Hub Connect State Machine
10.5.2.1 Hub Connect State Descriptions
10.5.2.2 HCONNECT.Powered-off
10.5.2.3 HCONNECT.Attempt ESS Connect
10.5.2.4 HCONNECT.Connected on ESS
10.6 Upstream Facing Port Power Management
10.6.1 Upstream Facing Port PM Timer
10.6.2 Hub Upstream Facing Port State Descriptions
10.6.2.1 Enabled U0 States
10.6.2.2 Attempt U0 – U1 Transition
10.6.2.3 Attempt U0 – U2 Transition
10.6.2.4 Link in U1
10.6.2.5 Link in U2
10.6.2.6 Link in U3
10.7 SuperSpeed Hub Header Packet Forwarding and Data Repeater
10.7.1 SuperSpeed Hub Elasticity Buffer
10.7.2 SKP Ordered Sets
10.7.3 Interpacket Spacing
10.7.4 SuperSpeed Header Packet Buffer Architecture
10.7.5 SuperSpeed Packet Connectivity
10.8 SuperSpeedPlus Store and Forward Behavior
10.8.1 Hub Elasticity Buffer
10.8.2 SKP Ordered Sets
10.8.3 Interpacket Spacing
10.8.4 Upstream Flowing Buffering
10.8.5 Downstream Flowing Buffering
10.8.6 SuperSpeedPlus Hub Arbitration of Packets
10.8.6.1 Arbitration Weight
10.8.6.2 Direction Independent Packet Selection
10.8.6.3 Downstream Flowing Packet Reception and Selection
10.8.6.4 Upstream Flowing Packet Reception and Selection
10.8.6.4.1 Partially Buffered DP Selection Candidate
10.8.6.4.2 Upstream Weighted Round Robin Arbitration
10.8.7 SuperSpeedPlus Upstream Flowing Packet Modifications
10.8.8 SuperSpeedPlus Downstream Controller
10.9 Port State Machines
10.9.1 Port Transmit State Machine
10.9.2 Port Transmit State Descriptions
10.9.2.1 Tx IDLE
10.9.2.2 Tx Header
10.9.2.3 Tx Data
10.9.2.4 Tx Data Abort
10.9.2.5 Tx Link Command
10.9.3 Port Receive State Machine
10.9.4 Port Receive State Descriptions
10.9.4.1 Rx Default
10.9.4.2 Rx Data
10.9.4.3 Rx Header
10.9.4.4 Process Header Packet
10.9.4.4.1 SuperSpeed Hub Upstream Facing Port
10.9.4.4.2 SuperSpeedPlus Hub Upstream Facing Port
10.9.4.4.3 SuperSpeed Hub Downstream Facing Port
10.9.4.4.4 SuperSpeedPlus Hub Downstream Facing Port
10.9.4.5 Rx Link Command
10.9.4.6 Process Link Command
10.10 Suspend and Resume
10.11 Hub Upstream Port Reset Behavior
10.12 Hub Port Power Control
10.12.1 Multiple Gangs
10.13 Hub Controller
10.13.1 Endpoint Organization
10.13.2 Hub Information Architecture and Operation
10.13.3 Port Change Information Processing
10.13.4 Hub and Port Status Change Bitmap
10.13.5 Over-current Reporting and Recovery
10.13.6 Enumeration Handling
10.14 Hub Configuration
10.15 Descriptors
10.15.1 Standard Descriptors for Hub Class
10.15.2 Class-specific Descriptors
10.15.2.1 Hub Descriptor
10.16 Requests
10.16.1 Standard Requests
10.16.2 Class-specific Requests
10.16.2.1 Clear Hub Feature
10.16.2.2 Clear Port Feature
10.16.2.3 Get Hub Descriptor
10.16.2.4 Get Hub Status
10.16.2.5 Get Port Error Count
10.16.2.6 Get Port Status
10.16.2.6.1 Port Status Bits
PORT_CONNECTION
PORT_ENABLE
PORT_OVER_CURRENT
PORT_RESET
PORT_LINK_STATE
PORT_POWER
PORT_SPEED
10.16.2.6.2 Port Status Change Bits
C_PORT_CONNECTION
C_PORT_OVER_CURRENT
C_PORT_RESET
C_PORT_BH_RESET
C_PORT_LINK_STATE
C_PORT_CONFIG_ERROR
10.16.2.6.3 Extended Port Status Bits
TX_SUBLINK_SPEED_ID and RX_SUBLINK_SPEED_ID
TX_LANE_COUNT and RX_LANE_COUNT
10.16.2.7 Set Hub Descriptor
10.16.2.8 Set Hub Feature
10.16.2.9 Set Hub Depth
10.16.2.10 Set Port Feature
10.17 Host Root (Downstream) Ports
10.18 Peripheral Device Upstream Ports
10.18.1 Peripheral Device Upstream Ports
10.18.2 Peripheral Device Upstream Port State Machine
10.18.2.1 USDPORT.Powered-off
10.18.2.2 USDPORT.Powered on
10.18.2.3 USDPORT.Training
10.18.2.4 USDPORT.Connected/Enabled
10.18.2.5 USDPORT.Error
10.18.2.6 USDPORT.Disabled
10.18.2.7 USDPORT.Disabled_Error
10.19 Hub Chapter Parameters
11 Interoperability and Power Delivery
11.1 USB 3.1 Host Support for USB 2.0
11.2 USB 3.1 Hub Support for USB 2.0
11.3 USB 3.1 Device Support for USB 2.0
11.4 Power Distribution
11.4.1 Classes of Devices and Connections
11.4.1.1 Self-powered Hubs
11.4.1.1.1 Over-current Protection
11.4.1.2 Low-power Bus-powered Devices
11.4.1.3 High-power Bus-powered Devices
11.4.1.4 Self-powered Devices
11.4.2 Steady-State Voltage Drop Budget
11.4.3 Power Control During Suspend/Resume
11.4.4 Dynamic Attach and Detach
11.4.4.1 Inrush Current Limiting
11.4.4.2 Dynamic Detach
11.4.5 Vbus Electrical Characteristics
11.4.6 Powered-B Connector
11.4.7 Wire Gauge Table
A Gen 1 Symbol Encoding
B Symbol Scrambling
B.1 Data Scrambling
C Power Management
C.1 SuperSpeed Power Management Overview
C.1.1 Link Power Management
C.1.1.1 Summary of Link States
C.1.1.2 U0 – Link Active
C.1.1.3 U1 – Link Idle with Fast Exit
C.1.1.3.1 U1 Entry
C.1.1.3.2 Exiting the U1 State
C.1.1.4 U2 – Link Idle with Slow Exit
C.1.1.5 U3 – Link Suspend
C.1.2 Link Power Management for Downstream Ports
C.1.2.1 Link State Coordination and Management
C.1.2.2 Packet Deferring
C.1.2.3 Software Interface
C.1.3 Other Link Power Management Support Mechanisms
C.1.3.1 Packets Pending Flag
C.1.3.2 Support for Isochronous Transfers
C.1.3.3 Support for Interrupt Transfers
C.1.4 Device Power Management
C.1.4.1 Function Suspend
C.1.4.2 Device Suspend
C.1.4.3 Host Initiated Suspend
C.1.4.4 Host Initiated Wake from Suspend
C.1.4.5 Device Initiated Wake from Suspend
C.1.5 Platform Power Management Support
C.1.5.1 System Exit Latency and BELT
C.1.5.2 Maximum Exit Latency and PING
C.1.5.2.1 Maximum Exit Latency t1 (tMEL1)
C.1.5.2.2 Maximum Exit Latency t2 (tMEL2)
C.1.5.2.3 Maximum Exit Latency t3 (tMEL3)
C.1.5.2.4 Maximum Exit Latency t4 (tMEL4)
C.2 Calculating U1 and U2 End to End Exit Latencies
C.2.1 Device Connected Directly to Host
C.2.1.1 Host Initiated Transition
C.2.1.2 Device Initiated Transition
C.2.2 Device Connected Through a Hub
C.2.2.1 Host Initiated Transition
C.2.2.2 Device Initiated Transition
C.3 Device-Initiated Link Power Management Policies
C.3.1 Overview and Background Information
C.3.2 Entry Conditions for U1 and U2
C.3.2.1 Control Endpoints
C.3.2.2 Bulk Endpoints
C.3.2.3 Interrupt Endpoints
C.3.2.4 Isochronous Endpoints
C.3.2.5 Devices That Need Timestamp Packets
C.4 Latency Tolerance Message (LTM) Implementation Example
C.4.1 Device State Machine Implementation Example
C.4.1.1 LTM-Idle State BELT
C.4.1.2 LTM-Active State BELT
C.4.1.3 Transitioning Between LT-States
C.4.1.3.1 Transitioning From LT-idle to LT-active
C.4.1.3.2 Transitioning From LT-active to LT-idle
C.4.2 Other Considerations
C.5 SuperSpeed vs. High Speed Power Management Considerations
D Example Packets
E Repeaters
Universal Serial Bus 3.1
Specification
Hewlett-Packard Company
Intel Corporation
Microsoft Corporation
Renesas Corporation
ST-Ericsson
Texas Instruments
Revision 1.0
July 26, 2013
Universal Serial Bus 3.1 Specification, Revision 1.0
Revision History
Revision
1.0
1.0
Comments
Initial release. USB 3.0
Incorporated errata and ECNs
Initial release. USB 3.1
Issue Date
November 12, 2008
June 6, 2011
July 26, 2013
INTELLECTUAL PROPERTY DISCLAIMER
THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY
WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE
AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY
PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE
PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
ii
Please send comments to techsup@usb.org
For industry information, refer to the USB Implementers Forum web page at http://www.usb.org
All product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2007-2013, Hewlett-Packard Company, Intel Corporation, Microsoft Corporation, Renesas Corporation, ST-
Ericsson, and Texas Instruments.
All rights reserved.
Acknowledgement of Technical Contribution
Dedication
Dedicated to the memory of Brad Hosler, the impact of whose
accomplishments made the Universal Serial Bus one of the most
successful technology innovations of the Personal Computer era.
The authors of this specification would like to recognize the following people who participated in the
USB 3.0 Bus Specification technical workgroups. We would also like to acknowledge the many others
throughout the industry who provided feedback and contributed to the development of this specification.
Promoter Company Employees
Alan Berkema
Walter Fry
Anthony Hudson
David Roderick
Kok Hong Chan
Huimin Chen
Bob Dunstan
Dan Froelich
Howard Heck
Brad Hosler
John Howard
Rahman Ismail
John Keys
Yun Ling
Andy Martwick
Steve McGowan
Ramin Neshati
Duane Quiet
Jeff Ravencraft
Brad Saunders
Joe Schaefer
Sarah Sharp
Micah Sheller
Gary Solomon
Karthi Vadivelu
Clint Walker
Jim Walsh
Randy Aull
Fred Bhesania
Martin Borve
Jim Bovee
Stephen Cooper
Lars Giusti
Robbie Harris
Allen Marshall
Kiran Muthabatulla
Hewlett-Packard Company
Hewlett-Packard Company
Hewlett-Packard Company
Hewlett-Packard Company
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
iii
Universal Serial Bus 3.1 Specification, Revision 1.0
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
NEC Corporation
ST-NXP Wireless
ST-NXP Wireless
ST-NXP Wireless
NXP Semiconductors, B.V.
ST-NXP Wireless
NXP Semiconductors, B.V.
NXP Semiconductors, B.V.
ST-NXP Wireless
NXP Semiconductors, B.V.
ST-NXP Wireless
ST-NXP Wireless
ST-NXP Wireless
ST-NXP Wireless
ST-NXP Wireless
NXP Semiconductors, B.V.
ST-NXP Wireless
Texas Instruments.
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments.
Texas Instruments
Tomas Perez-Rodriguez
Mukund Sankaranarayan
Nathan Sherman
Glen Slick
David Wooten
Rob Young
Nobuo Furuya
Hiroshi Kariya
Masami Katagiri
Yuichi Mizoguchi
Kats Nakazawa
Nobuyuki Mizukoshi
Yutaka Noguchi
Hajime Nozaki
Kenji Oguma
Satoshi Ohtani
Takanori Saeki
Eiji Sakai
Hiro Sakamoto
Hajime Sakuma
Makoto Sato
Hock Seow
"Peter" Chu Tin Teng
Yoshiyuki Tomoda
Satomi Yamauchi
Yoshiyuki Yamada
Susumu Yasuda
Alan Chang
Wing Yan Chung
Socol Constantin
Knud Holtvoeth
Linus Kerk
Martin Klein
Geert Knapen
Chee Ee Lee
Christian Paquet
Veerappan Rajaram
Shaun Reemeyer
Dave Sroka
Chee-Yen TEE
Jerome Tjia
Bart Vertenten
Hock Meng Yeo
Olivier Alavoine
David Arciniega
Richard Baker
Sujoy Chakravarty
T. Y. Chan
Romit Dasgupta
Alex Davidson
iv
Eric Desmarchelier
Christophe Gautier
Dan Harmon
Will Harris
Richard Hubbard
Ivo Huber
Scott Kim
Grant Ley
Karl Muth
Lee Myers
Julie Nirchi
Wes Ray
Matthew Rowley
Bill Sherry
Mitsuru Shimada
James Skidmore
Yoram Solomon
Sue Vining
Jin-sheng Wang
Roy Wojciechowski
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments.
Texas Instruments
Texas Instruments
Texas Instruments
Contributor Company Employees
Glen Chandler
John Chen
Roger Hou
Charles Wang
Norman Wu
Steven Yang
George Yee
George Olear
Sophia Liu
William Northey
Tom Sultzer
Garry Biddle
Kuan-Yu Chen
Jason Chou
Gustavo Duenas
Bob Hall
Jiayong He
Jim Koser
Joe Ortega
Ash Raheja
James Sabo
Pei Tsao
Kevin Walker
Tsuneki Watanabe
Chong Yi
Taro Hishinuma
Kaz Ichikawa
Ryozo Koyama
Karl Kwiat
Tadashi Sakaizawa
Shinya Tono
Eiji Wakatsuki
Takashi Ehara
Ron Muir
Acon
Acon
Acon
Acon
Acon
Acon
Acon
Contech Research
Electronics Testing Center, Taiwan (ETC)
FCI
FCI
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Foxconn
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Hirose Electric
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
v
Universal Serial Bus 3.1 Specification, Revision 1.0
Kazuhiro Saito
Hitoshi Kawamura
Takashi Kawasaki
Atsushi Nishio
Yasuhiko Shinohara
Tom Lu
Edmund Poh
Scott Sommers
Jason Squire
Dat Ba Nguyen
Jan Fahllund
Richard Petrie
Panu Ylihaavisto
Martin Furuhjelm
Julian Gorfajn
Marc Hildebrant
Tony Priborsky
Harold To
Robert Lefferts
Saleem Mohammad
Matthew Myers
Daniel Weinlader
Mike Engbretson
Thomas Grzysiewicz
Masaaki Iwasaki
Kazukiyo Osada
Hiroshi Shirai
Scott Shuey
Masaru Ueno
Japan Aviation Electronics Industry Ltd. (JAE)
Mitsumi
Mitsumi
Mitsumi
Mitsumi
Molex Inc.
Molex Inc.
Molex Inc.
Molex Inc.
NTS/National Technical System
Nokia
Nokia
Nokia
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Tektronix, Inc.
Tyco Electronics
Tyco Electronics
Tyco Electronics
Tyco Electronics
Tyco Electronics
Tyco Electronics
The authors of this specification would like to recognize the following people who participated in the
USB 3.1 Bus Specification technical workgroups. Additionally we would like to acknowledge the many
others throughout industry who provided feedback and contributed to the development of this
specification.
Promoter Company Employees
Alan Berkema
Norton Ewart
Monji Jabori
Rahul Lakdawala
Jim Mann
Linden McClure
Mike Bell
Huimin Chen
Kuan-Yu Chen
Bob Dunstan
Benjamin Graniello
Howard Heck
John Howard
Rahman Ismail
Yun Ling
Steve Mcgowan
Sridharan Ranganathan
Kaleb Ruof
Brad Saunders
Sarah Sharp
Ronald Swartz
Jennifer Tsai
Karthi Vadivelu
Randy Aull
Vivek Gupta
Toby Nixon
Hewlett Packard
Hewlett Packard
Hewlett Packard
Hewlett Packard
Hewlett Packard
Hewlett Packard
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Intel Corporation
Microsoft Corporation
Microsoft Corporation
Microsoft Corporation
vi
Yang You
Nobuo Furuya
Masami Katagiri
Steven Kawamoto
Kiichi Muto
Peter Teng
Hicham Bouzekri
Morten Christiansen
Grant Ley
James Skidmore
Sue Vining
Tod Wolf
Li Yang
Microsoft Corporation
Renesas Electronics Corp.
Renesas Electronics Corp.
Renesas Electronics Corp.
Renesas Electronics Corp.
Renesas Electronics Corp.
ST-Ericsson
ST-Ericsson
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Contributor Company Employees
Jason Chen
Andy Feng
Chris Kao
Glen Chandler
Alan MacDougall
Shadi Barakat
Walter Fry
Will Harris
Jason Hawken
Hugo Lamarche
Yufei Ma
Joseph Scanlon
Vishant Tyagi
Min Wang
James Choate
Thorsten Goetzelmann
Takuya Hirato
Hiroshi Kanda
Donald Schoenecker
Chi Chang
Chin Chang
Chiahsin Chen
Weber Chuang
Ming-Wei Hsu
Han Sung Kuo
ShuYu Lin
Luke Peng
Daniel Wei
ShengChung Wu
Ted Hsiao
Pete Burgers
Dan Ellis
Richard Petrie
Terry Little
Steve Sedio
Tim Barilovits
Bob McVay
Christopher Meyers
Jie Ni
Jeffrey Yang
Jing-Fan Zhang
Mike Engbretson
Kunia Aihara
Kazu Ichikawa
Masaru Kawamura
William MacKillop
Sho Nakamura
Toshiyuki Takada
Sid Tono
Tirumal Annamaneni
Colby Keith
Aces Electronics Co., Ltd.
Aces Electronics Co., Ltd.
Aces Electronics Co., Ltd.
ACON, Advanced-Connectek, Inc.
ACON, Advanced-Connectek, Inc.
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Advanced Micro Devices
Agilent Technologies, Inc.
Agilent Technologies, Inc.
Agilent Technologies, Inc.
Agilent Technologies, Inc.
Agilent Technologies, Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
ASMedia Technology Inc.
Bizlink Technology, Inc.
DisplayLink (UK) Ltd.
DisplayLink (UK) Ltd.
DisplayLink (UK) Ltd.
Foxconn / Hon Hai
Foxconn / Hon Hai
Fresco Logic Inc.
Fresco Logic Inc.
Fresco Logic Inc.
Fresco Logic Inc.
Fresco Logic Inc.
Fresco Logic Inc.
Granite River Labs
Hirose Electric Co., Ltd.
Hirose Electric Co., Ltd.
Hirose Electric Co., Ltd.
Hirose Electric Co., Ltd.
Hirose Electric Co., Ltd.
Hirose Electric Co., Ltd.
Hirose Electric Co., Ltd.
Intersil Corporation
Intersil Corporation
vii
Universal Serial Bus 3.1 Specification, Revision 1.0
Intersil Corporation
Intersil Corporation
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
Japan Aviation Electronics Industry Ltd. (JAE)
LeCroy Corporation
LeCroy Corporation
LeCroy Corporation
LeCroy Corporation
LeCroy Corporation
LeCroy Corporation
LeCroy Corporation
LeCroy Corporation
Lenovo
Lotes Co., Ltd.
Lotes Co., Ltd.
Lotes Co., Ltd.
LSI Corporation
LSI Corporation
LSI Corporation
Luxshare-ICT
Luxshare-ICT
Luxshare-ICT
Luxshare-ICT
Luxshare-ICT
MCCI Corporation
Nokia Corporation
Nokia Corporation
Nokia Corporation
NXP Semiconductors
NXP Semiconductors
NXP Semiconductors
NXP Semiconductors
Samsung Electronics Co., Ltd.
Samsung Electronics Co., Ltd.
Samsung Electronics Co., Ltd.
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
Seagate Technology LLC
SMSC
STMicroelectronics
STMicroelectronics
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Synopsys, Inc.
Tektronix, Inc.
Tektronix, Inc.
Tektronix, Inc.
Tektronix, Inc.
Tyco Electronics Corp., a TE Connectivity Ltd. company
Tyco Electronics Corp., a TE Connectivity Ltd. company
Tyco Electronics Corp., a TE Connectivity Ltd. company
Gourgen Oganessyan
Michael Vrazel
Toshiyuki Moritake
Takeharu Naito
Mark Saubert
Toshio Shimoyama
Takamitsu Wada
Roy Chestnut
Christopher Forker
Linden Hsu
Daniel H Jacobs
David Li
Mike Micheletti
Michael Romm
Chris Webb
Tomoki Harada
Ariel Delos Reyes
Smark Huo
Regina Liu-Hwang
Harvey Newman
Dave Thompson
Srinivas Vura
Josue Castillo
Alan Kinningham
John Lin
Stone Lin
Pat Young
John Garney
Peter Harrison
Mika Tolvanen
Panu Ylihaavisto
Jason Chen
Gerrit den Besten
Bart Vertenten
Ho Wai Wong-Lam
Jagoun Koo
Cheolho Lee
Jun Bum Lee
Alvin Cox
Steven Davis
Bahar Ghaffari
Henry (John) Hein
Tony Priborsky
Tom Skaar
Dan Smith
Mark Bohm
Jerome DeRoo
Benoit Mercier
Subramaniam Aravindhan
Bala Babu
Sanjay Dave
Gervais Fong
Kevin Heilman
Eric Huang
Behram Minwalla
Saleem Mohammad
Matthew Myers
Tri Nguyen
John Stonick
Zongyao Wen
Paul Wyborny
Sarah Boen
Darren Gray
Srikrishna N.H.
Randy White
Jim McGrath
Josh Moody
Scott Shuey
viii
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