logo资料库

高性能交换机及路由器(High Performance Switches and Routers)Prof.J.Chao 200....pdf

发布时间：2022-06-09 发布人：admin 分类：说明书 资料大小：23.86M 资料格式：pdf 举报 版权申诉
第1页 / 共634页
第2页 / 共634页
第3页 / 共634页
第4页 / 共634页
第5页 / 共634页
第6页 / 共634页
第7页 / 共634页
第8页 / 共634页
资料共634页，剩余部分请下载后查看
    PREFACE
    ACKNOWLEDGMENTS
    1 INTRODUCTION
    1.1 Architecture of the Internet: Present and Future
    1.2 Router Architectures
    1.3 Commercial Core Router Examples
    1.4 Design of Core Routers
    1.5 IP Network Management
    1.6 Outline of the Book
    2 IP ADDRESS LOOKUP
    2.1 Overview
    2.2 Trie-Based Algorithms
    2.3 Hardware-Based Schemes
    2.4 IPv6 Lookup
    2.5 Comparison
    3 PACKET CLASSIFICATION
    3.1 Introduction
    3.2 Trie-Based Classifications
    3.3 Geometric Algorithms
    3.4 Heuristic Algorithms
    3.5 TCAM-Based Algorithms
    4 TRAFFIC MANAGEMENT
    4.1 Quality of Service
    4.2 Integrated Serv
    4.3 Differentiated Services
    4.4 Traffic Policing and Shaping
    4.5 Packet Scheduling
    4.6 Buffer Management
    5 BASICS OF PACKET SWITCHING
    5.1 Fundamental Switching Concept
    5.2 Switch Fabric Classification
    5.3 Buffering Strategy in Switching Fabrics
    5.4 Multiplane Switching and Multistage Switching
    5.5 Performance of Basic Switches
    6 SHARED-MEMORY SWITCHES
    6.1 Linked List Approach
    6.2 Content Addressable Memory Approach
    6.3 Space-Time-Space Approach
    6.4 Scaling the Shared-Memory Switches
    6.5 Multicast Shared-Memory Switches
    7 INPUT-BUFFERED SWITCHES
    7.1 Scheduling in VOQ-Based Switches
    7.2 Maximum Matching
    7.3 Maximal Matching
    7.4 Randomized Matching Algorithms
    7.5 Frame-based Matching
    7.6 Stable Matching with Speedup
    8 BANYAN-BASED SWITCHES
    8.1 Banyan Networks
    8.2 Batcher-Sorting Network
    8.3 Output Contention Resolution Algorithms
    8.4 The Sunshine Switch
    8.5 Deflection Routing
    8.6 Multicast Copy Networks
    9 KNOCKOUT-BASED SWITCHES
    9.1 Single-Stage Knockout Switch
    9.2 Channel Grouping Principle
    9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS)
    9.4 Appendix
    10 THE ABACUS SWITCH
    10.1 Basic Architecture
    10.2 Multicast Contention Resolution Algorithm
    10.3 Implementation of Input Port Controller
    10.4 Performance
    10.5 ATM Routing and Concentration (ARC) Chip
    10.6 Enhanced Abacus Switch
    10.7 Abacus Switch for Packet Switching
    11 CROSSPOINT BUFFERED SWITCHES
    11.1 Combined Input and Crosspoint Buffered Switches
    11.2 Combined Input and Crosspoint Buffered Switches with VOQ
    11.3 OCF_OCF: Oldest Cell First Scheduling
    11.4 LQF_RR: Longest Queue First and Round-Robin Scheduling in CIXB-1
    11.5 MCBF: Most Critical Buffer First Scheduling
    12 CLOS-NETWORK SWITCHES
    12.1 Routing Property of Clos Network Switches
    12.2 Looping Algorithm
    12.3 m-Matching Algorithm
    12.4 Euler Partition Algorithm
    12.5 Karol’s Algorithm
    12.6 Frame-Based Matching Algorithm for Clos Network (f-MAC)
    12.7 Concurrent Matching Algorithm for Clos Network (c-MAC)
    12.8 Dual-Level Matching Algorithm for Clos Network (d-MAC)
    12.9 The ATLANTA Switch
    12.10 Concurrent Round-Robin Dispatching (CRRD) Scheme
    12.11 The Path Switch
    13 MULTI-PLANE MULTI-STAGE BUFFERED SWITCH
    13.1 TrueWay Switch Architecture
    13.2 Packet Scheduling
    13.3 Stage-To-Stage Flow Control
    13.4 Port-To-Port Flow Control
    13.5 Performance Analysis
    13.6 Prototype
    14 LOAD-BALANCED SWITCHES
    14.1 Birkhoff–Von Neumann Switch
    14.2 Load-Balanced Birkhoff–von Neumann Switches
    14.3 Load-Balanced Birkhoff–von Neumann SwitchesWith FIFO Service
    15 OPTICAL PACKET SWITCHES
    15.1 Opto-Electronic Packet Switches
    15.2 Optoelectronic Packet Switch Case Study I
    15.3 Optoelectronic Packet Switch Case Study II
    15.4 All Optical Packet Switches
    15.5 Optical Packet Switch with Shared Fiber Delay Lines Single-stage Case
    15.6 All Optical Packet Switch with Shared Fiber Delay Lines – Three Stage Case
    16 HIGH-SPEED ROUTER CHIP SET
    16.1 Network Processors (NPs)
    16.2 Co-Processors for Packet Classification
    16.3 Traffic Management Chips
    16.4 Switching Fabric Chips
    INDEX
    HIGH PERFORMANCE SWITCHES AND ROUTERS H. JONATHAN CHAO and BIN LIU
    HIGH PERFORMANCE SWITCHES AND ROUTERS
    HIGH PERFORMANCE SWITCHES AND ROUTERS H. JONATHAN CHAO and BIN LIU
    Copyright © 2007 by John Wiley & Sons, Inc., All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey Published simultaneously in Canada No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic formats. For more information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data. Chao, H. Jonathan, 1955- High performance switches and routers / by H. Jonathan Chao, Bin Liu. p. cm. ISBN-13: 978-0-470-05367-6 ISBN-10: 0-470-05367-4 1. Asynchronous transfer mode. 2. Routers (Computer networks) 3. Computer network protocols. 4. Packet switching (Data transmission) I. Liu, Bin. II. Title. TK5105.35.C454 2007 621.382 2006026971 16- -dc22 Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1
    CONTENTS PREFACE ACKNOWLEDGMENTS 1 INTRODUCTION 1.1 1.2 1.3 1.4 1.5 1.6 T640 TX-Matrix / 9 Carrier Routing System (CRS-1) / 11 Architecture of the Internet: Present and Future / 2 The Present / 2 1.1.1 1.1.2 The Future / 4 Router Architectures / 5 Commercial Core Router Examples / 9 1.3.1 1.3.2 Design of Core Routers / 13 IP Network Management / 16 1.5.1 1.5.2 1.5.3 Outline of the Book / 19 Network Management System Functionalities / 16 NMS Architecture / 17 Element Management System / 18 2 IP ADDRESS LOOKUP 2.1 2.2 Overview / 25 Trie-Based Algorithms / 29 2.2.1 2.2.2 Binary Trie / 29 Path-Compressed Trie / 31 xv xvii 1 25 v
    分享到：
    赞 收藏

    相关推荐

    资料库

    课程资源

    共收录17145份资料，累计13个分类，关注成员有19位，主要包括：PHP,网络管理,网页制作,Java,.Net,数据库,3G/移动开发,C/C++,游戏开发,嵌入式,讲义,软件测试,专业指导

    热门标签

    PHP 网络管理 网页制作 Java .Net 数据库 3G/移动开发 C/C++ 游戏开发 嵌入式 讲义 软件测试 专业指导

    最新资料