Introduction to NASM A Study Material for CS2093 - Hardware Labo....pdf-资料库

Introduction to NASM A Study Material for CS2093 - Hardware Laboratory Prepared By: Muhammed Yazar Y BTech, CSE, NIT Calicut Under The Guidance of: Mr. Saidalavi Kalady Assistant Professor CSE, NIT Calicut Department Of Computer Science & Engineering National Institute of Technology, Calicut 2012

Thanks to Saidalavi Sir, Jayaraj Sir, Meera Sudharman Without their support there won't be even a single page in this........ -yazar Introduction to NASM Page 1

Basics of Computer Organization In order to program in assembly language it is necessary to have basic knowledge of Computer organization and processor architecture. This chapter gives you the basic idea of how a processor works, how it access data from main memory, how it reads or writes information from other I/O (Input / Output) devices etc. The basic operational design of a computer is called architecture. 80X86 series of processors follow Von Newmann Architecture which is based on the stored program concept. 1. Processor: Processor is the brain of the computer. It performs all mathematical, logical and control operations of a computer. It is that component of the computer which executes all the instructions given to it in the form of programs. It interacts with I/O devices, memory (RAM) and secondary storage devices and thus implements the instructions given by the user. Fig: 1.1 Basic Operation of a processor 2. Registers Registers are the most immediately accessible memory units for the processor. They are the fastest among all the types of memory. They reside inside the processor and the processor can access the contents of any register in a single clock cycle. It is the working memory for a processor, i.e , if we want the processor to perform any task it needs the data to be present in any of its registers. The series of processors released on or after 80186 like 80186, 80286, 80386, Pentium etc are referred to as x86 or 80x86 processors. The processors released on or after 80386 are called I386 processors. They are 32 bit processors internally and externally. So their register sizes are generally 32 bit. In this section we will go through the I386 registers. Intel maintains its backward compatibility of instruction sets, i.e, we can run a program designed for an old 16 bit machine in a 32bit machine. That is the reason why we can install 32-bit OS in a 64 bit PC. The only problem is that, the program will not use the complete set of registers and other available resources and thus it will be less efficient. Introduction to NASM Page 2

General Purpose Registers i. There are eight general purpose registers. They are EAX, EBX, ECX, EDX, EBP, ESI, EDI, ESP. We can refer to the lower 8 and 16 bits of these registers (E.g.: AX, AH, AL) separately. This is to maintain the backward compatibility of instruction sets. These registers are also known as scratchpad area as they are used by the processor to store intermediate values in a calculation and also for storing address locations. The General Purpose Registers are used for : I-386 General Purpose Registers EAX: Accumulator Register – Contains the value of some operands in some operations (E.g.: multiplication). EBX: Base Register – Pointer to some data in Data Segment. ECX: Counter Register – Acts as loop counter, used in string operations etc. EDX: Used as pointer to I/O ports. ESI: Source Index – Acts as source pointer in string operations. It can also act as a pointer in Data Segment (DS). EDI: Destination Index- Acts as destination pointer in string operations. It can also act as a pointer in Extra Segment (ES) ESP: Stack Pointer – Always points to the top of system stack. EBP: Base Pointer – It points to the starting of system stack (ie. bottom/base of stack). ii. Flags and EIP Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 0 0 I D V IP V IF A C V M R F 1 N T IOPL O F D F IF T F S F Z F 0 A F 0 P F 1 C F Introduction to NASM Page 3

Bit # Abbreviation Description Category Intel x86 FLAGS register 1 on 8086 and 186, should be 0 above Reserved 0 1 2 3 4 5 6 7 8 9 10 11 CF 1 PF 0 AF 0 ZF SF TF IF DF OF 12, 13 1,1 / IOPL 1 / NT 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32-63 RF VM AC VIF VIP ID 0 0 0 0 0 0 0 0 0 0 0 S S S S S X C C S X X X X X X FLAGS Carry flag Reserved Parity flag Reserved Adjust flag Reserved Zero flag Sign flag Trap flag (single step) Interrupt enable flag Direction flag Overflow flag I/O privilege level (286+ only) always 1 on 8086 and 186 Nested task flag (286+ only) always 1 on 8086 and 186 EFLAGS Resume flag (386+ only) Virtual 8086 mode flag (386+ only) Alignment check (486SX+ only) Virtual interrupt flag (Pentium+) Virtual interrupt pending (Pentium+) X Able to use CPUID instruction (Pentium+) X Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RFLAGS Reserved Source : www.wikipedia.org X – System Flags, S – Status Flags, C – Control Flags Introduction to NASM Page 4

FLAGS are special purpose registers inside the CPU that contains the status of CPU / the status of last operation executed by the CPU. Some of the bits in FLAGS need special mention: Carry Flag: When a processor do a calculation, if there is a carry then the Carry Flag will be set to 1. Zero Flag: If the result of the last operation was zero, Zero Flag will be set to 1, else it will be zero. Sign Flag : If the result of the last signed operation is negative then the Sign Flag is set to 1, else it will be zero. Parity Flag: If there are odd number of ones in the result of the last operation, parity flag will be set to 1. Interrupt Flag: If interrupt flag is set to 1, then only it will listen to external interrupts. EIP: EIP is the instruction pointer, it points to the next instruction to be executed. In memory there are basically two classes of things stored: (a) Data. (b)Program. When we start a program, it will be copied into the main memory and EIP is the pointer which points to the starting of this program in memory and execute each instruction sequentially. Branch statements like JMP, RET, CALL, JNZ (we will see this in chapter 3) alter the value of EIP. iii. Segment Registers In x86 processors for accessing the memory basically there are two types of registers used – Segment Register and Offset. Segment register contains the base address of a particular data section and Offset will contain how many bytes should be displaced from the segment register to access the particular data. CS contains the base address of Code Segment and EIP is the offset. It keeps on updating while executing each instruction. SS or Stack Segment contains the address of top most part of system stack. ESP and EBP will be the offset for that. Stack is a data structure that follows LIFO ie. Last-In-First-Out. There are two main operations associated with stack: push and pop. If we need to insert an element into a stack, we will push it and when we give the pop instruction, we will get the last value which we have pushed. Stack grows downward. So SP will always points to the top of stack and if we push an element, ESP (Stack Pointer) will get reduced by sufficient number of bytes and the data to be stored will be pushed over there. DS, ES, FS and GS acts as base registers for a lot of data operations like array addressing, string operations etc. ESI, EDI and EBX can act as offsets for them. Introduction to NASM Page 5

Unlike other registers, Segment registers are still 16 bit wide in 32-bit processors. In modern 32 bit processor the segment address will be just an entry into a descriptor table in memory and using the offset it will get the exact memory locations through some manipulations. This is called segmentation. Here in the memory ,the Stack Segment starts from the memory location 122 and grows downwards. Here the Stack Pointer ESP is pointing to the location 119. Now if we pop 1 byte of data from stack, we will get (01010101)2 and the ESP will get increased by one execute the push command: Then the ESP will get reduced by two units (because we need two store two bytes of data) and ax will be copied over there: Now suppose we have (01101100 11001111)2 in the register ax and we push ax Here we can see that now ESP points to the lower byte of data from the 2 bytes data which we have pushed. In x86 architecture when we push or save some data in memory, the lower bytes of it will be addressed immediately and thus it is said to follow Little Endian Form. MIPS architecture follows Big Endian Form. Introduction to NASM Page 6

IA32-Complete Register Set Introduction to NASM Page 7

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