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vivado约束手册.pdf
Vivado Design Suite User Guide: Using Constraints
Revision History
Table of Contents
Ch. 1: Introduction
Migrating From UCF Constraints to XDC Constraints
About XDC Constraints
Ch. 2: Constraints Methodology
About Constraints Methodology
Organizing Your Constraints
Project Flows
Non-Project Flows
Out-of-Context Constraints
Synthesis and Implementation Constraint Files
Ordering Your Constraints
Recommended Constraints Sequence
Constraints Sequence Editing
Constraint Files Order
Constraint Files Order with IP Cores
Changing Read Order
Entering Constraints
Saving Constraints in Memory
Constraints Editing Flow Options
User Interface Option
Hand Edit Option
Pin Assignment
Floorplanning
Timing Constraints Wizard
Constraints Processing Order and Invalid Constraints
Reporting Features Available when the Wizard is Open
Constraints Editing within the Wizard
Constraints Recommended by the Wizard
Primary Clocks
Generated Clocks
Forwarded Clocks
External Feedback Delays
Input Delays
Output Delays
Combinatorial Delays
Physically Exclusive Clock Groups
Logically Exclusive Clock Groups with no Interaction
Logically Exclusive Clock Groups with Interaction
Asynchronous Clock Domain Crossings
Constraints Summary
Timing Constraints Window
Timing Constraints Spreadsheet
Constraints Creation, Grouped by Category
All Constraints
XDC Templates
XDC Template Contents
Using XDC Templates
Advanced XDC Templates
Creating Synthesis Constraints
RTL Attributes
Timing Constraints
Physical and Configuration Constraints
Elaborated Design Constraints
Single-Bit Register Names
Multi-Bit Register Names
Absorbed Registers and Nets
Hierarchical Names
Creating Implementation Constraints
Adjusting Constraints for Synthesis Logic Replication
Constraints Scoping
XDC File Scoping Properties
Setting XDC File Scoping Properties Example
XDC Scoping Mechanism
IP and Sub-module Constraining with XDC
Scoped Queries Guidelines
Scoped Timing Constraints Guidelines
Recommended Constraints Rules of IP/Sub-Module XDC
Constraints Efficiency
Reviewing Constraints Coverage
Improving Constraints Runtime
Optimizing Pin Queries
Recommended Pin Queries
Example
Replacing all_registers Queries
Ordering Constraints for Better Runtime
Ch. 3: Defining Clocks
About Clocks
Propagated Clocks
Dedicated Hardware Resources
Primary Clocks
Primary Clocks Examples
Virtual Clocks
Generated Clocks
About Generated Clocks
User Defined Generated Clocks
Example One: Simple Division by 2
Example Two: Division by 2 With the -edges Option
Example Three: Duty Cycle Change and Phase Shift with -edges and -edge_shift Options
Example Four: Using Both -divide_by and -multiply_by at the Same Time
Example Five: Tracing the Master Clock through Combinational Arcs Only
Example Six: Forwarded Clock Driven by ODDR
Automatically Derived Clocks
Automatically Derived Clock Example
Local Net Names
Name Conflicts
Renaming Auto-Derived Clocks
Limitations
Clock Groups
About Clock Groups
Clock Categories
Synchronous Clocks
Asynchronous Clocks
Unexpandable Clocks
Asynchronous Clock Groups
Asynchronous Clock Groups Examples
Creating Asynchronous Clock Groups
Exclusive Clock Groups
Exclusive Clock Groups Example
Clock Latency, Jitter, and Uncertainty
Clock Latency
set_clock_latency Example
Clock Uncertainty
Clock Jitter
Input Jitter
System Jitter
Additional Clock Uncertainty
Ch. 4: Constraining I/O Delay
About Constraining I/O Delay
Input Delay
Using Input Delay Options
Min and Max Input Delay Command Options
Clock Fall Input Delay Command Option
Add Delay Input Delay Command Option
Use of set_input_delay Command Options
Input Delay Example One
Input Delay Example Two
Input Delay Example Three
Input Delay Example Four
Input Delay Example Five
Input Delay Example Six
Output Delay
Using Output Delay Options
Min and Max Output Delay Command Options
Clock Fall Output Delay Command Option
Add Delay Output Delay Command Option
Use of set_output_delay Command Options
Output Delay Example One
Output Delay Example Two
Output Delay Example Three
Output Delay Example Four
Ch. 5: Timing Exceptions
About Timing Exceptions
Multicycle Paths
Setting the Path Multipliers and Clock Edges
set_multicycle_path Syntax
Multicycles in Single Clock Domain
Relaxing Setup While Maintaining Hold
Moving the Setup
Example One: Setup=5 / Hold Moved Accordingly
Example Two: Setup=5 / Hold=4
Multicycle Paths and Clock Phase-Shift
Multicycles Between SLOW-to-FAST Clocks
Example One: Setup=3 / Hold Moved Accordingly
Example Two: Setup=3 / Hold=2 (-end)
Multicycles Between FAST-to-SLOW Clocks
Example: Setup=3 (-start) / Hold=2
False Paths
Min/Max Delays
Setting Maximum Delay and Minimum Delay Constraints
Maximum Delay Constraint Syntax
Minimum Delay Constraint Syntax
List of Nodes for the -from Option
List of Nodes for the -to Option
List of Nodes for the -through Option
Consequences of Setting Maximum Delay or Minimum Delay Constraints on a Path
Constraining Input or Output Logic
Constraining Asynchronous Signals
Path Segmentation
Path Segmentation and Timing Exception
Scenario 1
Scenario 2
Case Analysis
Disabling Timing Arcs
Ch. 6: CDC Constraints
About CDC Constraints
Constraining Bus Skew
About Bus Skew Constraints
Syntax of the set_bus_skew Command
set_bus_skew Example One
set_bus_skew Example Two
Set Bus Skew Dialog Box
Ch. 7: XDC Precedence
About XDC Precedence
XDC Constraints Order
Exceptions Priority
Exceptions Priority Example
Exceptions Priority with Multiple -through Options Example
Ch. 8: Physical Constraints
About Physical Constraints
Critical Warning
Netlist Constraints
CLOCK_DEDICATED_ROUTE
MARK_DEBUG
DONT_TOUCH
LOCK_PINS
LOCK_PINS Constraint Example One
LOCK_PINS Constraint Example Two
I/O Constraints
Placement Constraints
Placement Types
Fixed Placement
Unfixed Placement
Placement Constraint Example One
Placement Constraint Example Two
Placement Constraint Example Three
Placement Constraint Example Four
Placement Constraint Example Five
Placement Constraint Example Six
Placement Constraint Example Seven
Routing Constraints
Fixed Routing
Configuration Constraints
Configuration Constraint Example One
Configuration Constraint Example Two
Configuration Constraint Example Three
Ch. 9: Defining Relatively Placed Macros
About Relatively Placed Macros
Defining Sets of Design Elements
Creating an RPM
Assigning Cells to RPM Sets
Explicitly Grouping Design Elements
Explicitly Grouping Design Elements With U_SET
Explicitly Grouping Design Elements With HU_SET
Syntax for Defining RPM Sets in VHDL
Syntax for Defining RPM Sets in Verilog
U_SET Example
HU_SET Example
RPM Definition in the Physical Constraints Window
Viewing RPM Definitions
Preserving RPM through opt_design
Assigning Relative Locations
Relative Slice-Based Coordinates
BEL/LOC Constraints
Absolute RPM Grid-Based Coordinates
RPM_GRID Coordinates VHDL Example
Setting a Property to Invoke the RPM_GRID System
RPM_GRID Coordinate Values
Defining RLOC Properties Directly in the RTL Source File
Assigning a Fixed Location to an RPM
XDC Macros
Specifying Macros
create_macro
create_macro Syntax
create_macro Example
update_macro
update_macro Syntax
update_macro Example One
update_macro Example Two
update_macro Example Three
delete_macros
delete_macros Syntax
delete_macros Example
get_macros
get_macros Syntax
get_macros Examples
Managing Macros
Managing Macros Example One
Managing Macros Example Two
Managing Macros Example Three
Managing Macros Example Four
Macro Properties
Macro Properties Example
ABSOLUTE_GRID
CLASS
NAME
RLOCS
Preserving XDC Macros through opt_design
Advanced XDC Macro Examples
Relative Grid Macro Examples
Absolute Grid Macro Examples
Example: Assign the Variable rloc to the String Value of a Block RAM Cell RLOC
Example: Build an RLOC List for the Example Circuit
Converting RPMs to XDC Macros
Appx. A: Supported XDC and SDC Commands
Valid Commands in an XDC File
Supported SDC Commands
Unsupported SDC Commands
Appx. B: Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Vivado Design Suite User and Reference Guides
Additional Xilinx Resources
Training Resources
Please Read: Important Legal Notices
Vivado Design Suite
User Guide
Using Constraints
UG903 (v2018.3) December 5, 2018
Revision History
The following table shows the revision history for this document.
Section
Revision Summary
12/05/2018 Version 2018.3
About XDC Constraints
Out-of-Context Constraints
Adjusting Constraints for Synthesis Logic Replication
Replacing all_registers Queries
Primary Clocks
About Timing Exceptions
Converting RPMs to XDC Macros
Added an important note about the read_xdc and
source commands.
Added new section.
Added information about the
-include_replicated_objects and -filter
command line options.
Added an important note about the
all_registers command.
Added a note about defining primary clocks.
Updated the table.
Added new section.
General updates
Editorial updates only. No technical content updates.
06/06/2018 Version 2018.2
04/04/2018 Version 2018.1
General updates
Organizing Your Constraints
Constraints Processing Order and Invalid Constraints
About Clock Groups
Constraining Asynchronous Signals
Disabling Timing Arcs
DONT_TOUCH
Preserving XDC Macros through opt_design
Valid Commands in an XDC File
Updated menu commands.
Added information about the command line option
write_xdc -type.
Added information to non-project or design check
point (DCP) modes.
Added clarification about behavior of
set_clock_groups when only one clock group is
left.
Added information about constraining CDC paths.
Added a note about the set_disable_timing
command.
Added a note about reset_property.
Added new section.
Added Waiver constraint to the table.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Migrating From UCF Constraints to XDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
About XDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Constraints Methodology
About Constraints Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Organizing Your Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Your Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Entering Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Creating Synthesis Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Creating Implementation Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Constraints Scoping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Constraints Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 3: Defining Clocks
About Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Primary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Virtual Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Clock Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Clock Latency, Jitter, and Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Chapter 4: Constraining I/O Delay
About Constraining I/O Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Chapter 5: Timing Exceptions
About Timing Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Multicycle Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Using Constraints
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Min/Max Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Case Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Disabling Timing Arcs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Chapter 6: CDC Constraints
About CDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Constraining Bus Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Chapter 7: XDC Precedence
About XDC Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
XDC Constraints Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Exceptions Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 8: Physical Constraints
About Physical Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Netlist Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
I/O Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Placement Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Routing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Configuration Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 9: Defining Relatively Placed Macros
About Relatively Placed Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Defining Sets of Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Creating an RPM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Assigning Cells to RPM Sets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Assigning Relative Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Assigning a Fixed Location to an RPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
XDC Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Converting RPMs to XDC Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Appendix A: Supported XDC and SDC Commands
Valid Commands in an XDC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Supported SDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Unsupported SDC Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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Chapter 1
Introduction
Migrating From UCF Constraints to XDC Constraints
The Xilinx® Vivado® Integrated Design Environment (IDE) uses Xilinx Design Constraints
(XDC), and does not support the legacy User Constraints File (UCF) format.
There are key differences between Xilinx Design Constraints (XDC) and User Constraints File
(UCF) constraints. XDC constraints are based on the standard Synopsys Design Constraints
(SDC) format. SDC has been in use and evolving for more than 20 years, making it the most
popular and proven format for describing design constraints.
VIDEO: For training on migrating UCF constraints to XDC, see the Vivado Design Suite QuickTake
Video: Migrating UCF Constraints to XDC.
If you are familiar with UCF but new to XDC, see the "Differences Between XDC and UCF
Constraints" section in the Migrating UCF Constraints to XDC chapter of the ISE to Vivado
Design Suite Migration Guide (UG911) [Ref 1]. That chapter also describes how to convert
existing UCF files to XDC as a starting point for creating XDC constraints.
IMPORTANT: XDC has fundamental differences from UCF that must be understood in order to properly
constrain a design. The UCF to XDC conversion utility is not a replacement for properly understanding
and creating XDC constraints. Each XDC constraint is described in this User Guide.
About XDC Constraints
XDC constraints are a combination of industry standard Synopsys Design Constraints (SDC
version 1.9) and Xilinx proprietary physical constraints.
XDC constraints have the following properties:
•
•
•
They are not simple strings, but are commands that follow the Tcl semantic.
They can be interpreted like any other Tcl command by the Vivado Tcl interpreter.
They are read in and parsed sequentially the same as other Tcl commands.
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Chapter 1:
Introduction
You can enter XDC constraints in several ways, at different points in the flow.
•
Store the constraints in one or more XDC files.
To load the XDC file in memory, do one of the following:
° Use the read_xdc command.
°
Add it to one of your project constraints sets. XDC files only accept the set, list,
and expr built-in Tcl commands. See Appendix A, Supported XDC and SDC
Commands for a complete list of supported commands.
• Generate the constraints with an unmanaged Tcl script.
To execute the Tcl script, do one of the following:
Run the source command.
°
° Use the read_xdc -unmanaged command.
°
Add the Tcl script to one of your project constraints sets.
TIP: Unlike XDC files, unmanaged Tcl scripts can include any common Tcl command for selecting
design objects and defining design constraints, including conditional and looping control structures.
IMPORTANT: The Vivado Design Suite allows you to mix XDC files and Tcl scripts in the same
constraints set. Modified constraints are saved back to their original location only if they originally
came from an XDC file, and not from an unmanaged Tcl script. A constraint generated by a Tcl script is
not managed by the Vivado Design Suite and cannot be interactively modified. For more information,
see Chapter 2, Constraints Methodology.
IMPORTANT: For XDC constraints, there is a difference in behavior between the commands source
and read_xdc. The constraints imported with the source command are not saved in the checkpoint
in the same order as they are imported. The constraints imported with read_xdc are saved first and
then those imported with source. To save all the constraints in the same order as they are applied to
the design, use read_xdc -unmanaged instead of source.
To validate the syntax or impact of a particular constraint after loading your design in
memory, use the Tcl console and the Vivado Design Suite reporting features. This is
particularly powerful for analyzing and debugging timing constraints and physical
constraints.
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Constraints Methodology
Chapter 2
About Constraints Methodology
Design constraints define the requirements that must be met by the compilation flow in
order for the design to be functional on the board. Not all constraints are used by all steps
in the compilation flow. For example, physical constraints are used only during the
implementation steps (that is, by the placer and the router).
Because the Xilinx® Vivado® Integrated Design Environment (IDE) synthesis and
implementation algorithms are timing-driven, you must create proper timing constraints.
Over-constraining or under-constraining your design makes timing closure difficult. You
must use reasonable constraints that correspond to your application requirements.
Organizing Your Constraints
The Vivado IDE allows you to use one or many constraint files. While using a single
constraint file for the entire compilation flow might seem more convenient, it can be a
challenge to maintain all the constraints as the design becomes more complex. This is
usually the case for designs that use several IP cores or large blocks developed by different
teams.
After the timing and physical constraints have been imported, independent of the number
of source files or whether the design is in Project/Non-Project mode, all the constraints can
be exported as a single file with the write_xdc command. The constraints are written to
the specified output file in the same order that they were read into the project or design.
The command line option write_xdc -type can be used to select a sub-set of
constraints (timing, physical, or waiver) to export.
RECOMMENDED: Xilinx recommends that you separate timing constraints and physical constraints by
saving them into two distinct files. You can also keep the constraints specific to a certain module in a
separate file.
Using Constraints
UG903 (v2018.3) December 5, 2018
www.xilinx.com
8
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