da14580数据手册.pdf

发布时间：2022-05-30 发布人：admin 分类：说明书资料大小：1.40M 资料格式：pdf 举报版权申诉

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1. Block diagram

2. Pinout

Table 1: Ordering information (samples)

Table 2: Ordering information (production)

Table 3: Pin Description

3. System overview

3.1 ARM Cortex-M0 CPU

3.2 Bluetooth Smart

3.2.1 BLE Core

3.2.2 Radio Transceiver

3.2.3 SmartSnippetsä

3.3 Memories

3.4 Functional Modes

3.5 Power Modes

3.6 Interfaces

3.6.1 UARTs

3.6.2 SPI+

3.6.3 I2C interface

3.6.4 General purpose ADC

3.6.5 Quadrature decoder

3.6.6 Keyboard controller

3.6.7 Input/output ports

3.7 Timers

3.7.1 General purpose timers

3.7.2 Wake-Up timer

3.7.3 Watchdog timer

3.8 Clock/Reset

3.8.1 Clocks

3.8.2 Reset

3.9 Power Management

4. Registers

Table 4: Register map

Table 5: OTPC_MODE_REG (0x40008000)

Table 6: OTPC_PCTRL_REG (0x40008004)

Table 7: OTPC_STAT_REG (0x40008008)

Table 8: OTPC_AHBADR_REG (0x4000800C)

Table 9: OTPC_CELADR_REG (0x40008010)

Table 10: OTPC_NWORDS_REG (0x40008014)

Table 11: OTPC_FFPRT_REG (0x40008018)

Table 12: OTPC_FFRD_REG (0x4000801C)

Table 13: PATCH_VALID_REG (0x40008400)

Table 14: PATCH_VALID_SET_REG (0x40008404)

Table 15: PATCH_VALID_RESET_REG (0x40008408)

Table 16: PATCH_ADDR0_REG (0x40008410)

Table 17: PATCH_DATA0_REG (0x40008414)

Table 18: PATCH_ADDR1_REG (0x40008418)

Table 19: PATCH_DATA1_REG (0x4000841C)

Table 20: PATCH_ADDR2_REG (0x40008420)

Table 21: PATCH_DATA2_REG (0x40008424)

Table 22: PATCH_ADDR3_REG (0x40008428)

Table 23: PATCH_DATA3_REG (0x4000842C)

Table 24: PATCH_ADDR4_REG (0x40008430)

Table 25: PATCH_DATA4_REG (0x40008434)

Table 26: PATCH_ADDR5_REG (0x40008438)

Table 27: PATCH_DATA5_REG (0x4000843C)

Table 28: PATCH_ADDR6_REG (0x40008440)

Table 29: PATCH_DATA6_REG (0x40008444)

Table 30: PATCH_ADDR7_REG (0x40008448)

Table 31: PATCH_DATA7_REG (0x4000844C)

Table 32: CLK_AMBA_REG (0x50000000)

Table 33: CLK_FREQ_TRIM_REG (0x50000002)

Table 34: CLK_PER_REG (0x50000004)

Table 35: CLK_RADIO_REG (0x50000008)

Table 36: CLK_CTRL_REG (0x5000000A)

Table 37: PMU_CTRL_REG (0x50000010)

Table 38: SYS_CTRL_REG (0x50000012)

Table 39: SYS_STAT_REG (0x50000014)

Table 40: TRIM_CTRL_REG (0x50000016)

Table 41: CLK_32K_REG (0x50000020)

Table 42: CLK_16M_REG (0x50000022)

Table 43: CLK_RCX20K_REG (0x50000024)

Table 44: BANDGAP_REG (0x50000028)

Table 45: ANA_STATUS_REG (0x5000002A)

Table 46: WKUP_CTRL_REG (0x50000100)

Table 47: WKUP_COMPARE_REG (0x50000102)

Table 48: WKUP_RESET_IRQ_REG (0x50000104)

Table 49: WKUP_COUNTER_REG (0x50000106)

Table 50: WKUP_RESET_CNTR_REG (0x50000108)

Table 51: WKUP_SELECT_P0_REG (0x5000010A)

Table 52: WKUP_SELECT_P1_REG (0x5000010C)

Table 53: WKUP_SELECT_P2_REG (0x5000010E)

Table 54: WKUP_SELECT_P3_REG (0x50000110)

Table 55: WKUP_POL_P0_REG (0x50000112)

Table 56: WKUP_POL_P1_REG (0x50000114)

Table 57: WKUP_POL_P2_REG (0x50000116)

Table 58: WKUP_POL_P3_REG (0x50000118)

Table 59: QDEC_CTRL_REG (0x50000200)

Table 60: QDEC_XCNT_REG (0x50000202)

Table 61: QDEC_YCNT_REG (0x50000204)

Table 62: QDEC_CLOCKDIV_REG (0x50000206)

Table 63: QDEC_CTRL2_REG (0x50000208)

Table 64: QDEC_ZCNT_REG (0x5000020A)

Table 65: UART_RBR_THR_DLL_REG (0x50001000)

Table 66: UART_IER_DLH_REG (0x50001004)

Table 67: UART_IIR_FCR_REG (0x50001008)

Table 68: UART_LCR_REG (0x5000100C)

Table 69: UART_MCR_REG (0x50001010)

Table 70: UART_LSR_REG (0x50001014)

Table 71: UART_MSR_REG (0x50001018)

Table 72: UART_SCR_REG (0x5000101C)

Table 73: UART_LPDLL_REG (0x50001020)

Table 74: UART_LPDLH_REG (0x50001024)

Table 75: UART_SRBR_STHR0_REG (0x50001030)

Table 76: UART_SRBR_STHR1_REG (0x50001034)

Table 77: UART_SRBR_STHR2_REG (0x50001038)

Table 78: UART_SRBR_STHR3_REG (0x5000103C)

Table 79: UART_SRBR_STHR4_REG (0x50001040)

Table 80: UART_SRBR_STHR5_REG (0x50001044)

Table 81: UART_SRBR_STHR6_REG (0x50001048)

Table 82: UART_SRBR_STHR7_REG (0x5000104C)

Table 83: UART_SRBR_STHR8_REG (0x50001050)

Table 84: UART_SRBR_STHR9_REG (0x50001054)

Table 85: UART_SRBR_STHR10_REG (0x50001058)

Table 86: UART_SRBR_STHR11_REG (0x5000105C)

Table 87: UART_SRBR_STHR12_REG (0x50001060)

Table 88: UART_SRBR_STHR13_REG (0x50001064)

Table 89: UART_SRBR_STHR14_REG (0x50001068)

Table 90: UART_SRBR_STHR15_REG (0x5000106C)

Table 91: UART_USR_REG (0x5000107C)

Table 92: UART_TFL_REG (0x50001080)

Table 93: UART_RFL_REG (0x50001084)

Table 94: UART_SRR_REG (0x50001088)

Table 95: UART_SRTS_REG (0x5000108C)

Table 96: UART_SBCR_REG (0x50001090)

Table 97: UART_SDMAM_REG (0x50001094)

Table 98: UART_SFE_REG (0x50001098)

Table 99: UART_SRT_REG (0x5000109C)

Table 100: UART_STET_REG (0x500010A0)

Table 101: UART_HTX_REG (0x500010A4)

Table 102: UART_CPR_REG (0x500010F4)

Table 103: UART_UCV_REG (0x500010F8)

Table 104: UART_CTR_REG (0x500010FC)

Table 105: UART2_RBR_THR_DLL_REG (0x50001100)

Table 106: UART2_IER_DLH_REG (0x50001104)

Table 107: UART2_IIR_FCR_REG (0x50001108)

Table 108: UART2_LCR_REG (0x5000110C)

Table 109: UART2_MCR_REG (0x50001110)

Table 110: UART2_LSR_REG (0x50001114)

Table 111: UART2_MSR_REG (0x50001118)

Table 112: UART2_SCR_REG (0x5000111C)

Table 113: UART2_LPDLL_REG (0x50001120)

Table 114: UART2_LPDLH_REG (0x50001124)

Table 115: UART2_SRBR_STHR0_REG (0x50001130)

Table 116: UART2_SRBR_STHR1_REG (0x50001134)

Table 117: UART2_SRBR_STHR2_REG (0x50001138)

Table 118: UART2_SRBR_STHR3_REG (0x5000113C)

Table 119: UART2_SRBR_STHR4_REG (0x50001140)

Table 120: UART2_SRBR_STHR5_REG (0x50001144)

Table 121: UART2_SRBR_STHR6_REG (0x50001148)

Table 122: UART2_SRBR_STHR7_REG (0x5000114C)

Table 123: UART2_SRBR_STHR8_REG (0x50001150)

Table 124: UART2_SRBR_STHR9_REG (0x50001154)

Table 125: UART2_SRBR_STHR10_REG (0x50001158)

Table 126: UART2_SRBR_STHR11_REG (0x5000115C)

Table 127: UART2_SRBR_STHR12_REG (0x50001160)

Table 128: UART2_SRBR_STHR13_REG (0x50001164)

Table 129: UART2_SRBR_STHR14_REG (0x50001168)

Table 130: UART2_SRBR_STHR15_REG (0x5000116C)

Table 131: UART2_USR_REG (0x5000117C)

Table 132: UART2_TFL_REG (0x50001180)

Table 133: UART2_RFL_REG (0x50001184)

Table 134: UART2_SRR_REG (0x50001188)

Table 135: UART2_SRTS_REG (0x5000118C)

Table 136: UART2_SBCR_REG (0x50001190)

Table 137: UART2_SDMAM_REG (0x50001194)

Table 138: UART2_SFE_REG (0x50001198)

Table 139: UART2_SRT_REG (0x5000119C)

Table 140: UART2_STET_REG (0x500011A0)

Table 141: UART2_HTX_REG (0x500011A4)

Table 142: UART2_CPR_REG (0x500011F4)

Table 143: UART2_UCV_REG (0x500011F8)

Table 144: UART2_CTR_REG (0x500011FC)

Table 145: SPI_CTRL_REG (0x50001200)

Table 146: SPI_RX_TX_REG0 (0x50001202)

Table 147: SPI_RX_TX_REG1 (0x50001204)

Table 148: SPI_CLEAR_INT_REG (0x50001206)

Table 149: SPI_CTRL_REG1 (0x50001208)

Table 150: I2C_CON_REG (0x50001300)

Table 151: I2C_TAR_REG (0x50001304)

Table 152: I2C_SAR_REG (0x50001308)

Table 153: I2C_DATA_CMD_REG (0x50001310)

Table 154: I2C_SS_SCL_HCNT_REG (0x50001314)

Table 155: I2C_SS_SCL_LCNT_REG (0x50001318)

Table 156: I2C_FS_SCL_HCNT_REG (0x5000131C)

Table 157: I2C_FS_SCL_LCNT_REG (0x50001320)

Table 158: I2C_INTR_STAT_REG (0x5000132C)

Table 159: I2C_INTR_MASK_REG (0x50001330)

Table 160: I2C_RAW_INTR_STAT_REG (0x50001334)

Table 161: I2C_RX_TL_REG (0x50001338)

Table 162: I2C_TX_TL_REG (0x5000133C)

Table 163: I2C_CLR_INTR_REG (0x50001340)

Table 164: I2C_CLR_RX_UNDER_REG (0x50001344)

Table 165: I2C_CLR_RX_OVER_REG (0x50001348)

Table 166: I2C_CLR_TX_OVER_REG (0x5000134C)

Table 167: I2C_CLR_RD_REQ_REG (0x50001350)

Table 168: I2C_CLR_TX_ABRT_REG (0x50001354)

Table 169: I2C_CLR_RX_DONE_REG (0x50001358)

Table 170: I2C_CLR_ACTIVITY_REG (0x5000135C)

Table 171: I2C_CLR_STOP_DET_REG (0x50001360)

Table 172: I2C_CLR_START_DET_REG (0x50001364)

Table 173: I2C_CLR_GEN_CALL_REG (0x50001368)

Table 174: I2C_ENABLE_REG (0x5000136C)

Table 175: I2C_STATUS_REG (0x50001370)

Table 176: I2C_TXFLR_REG (0x50001374)

Table 177: I2C_RXFLR_REG (0x50001378)

Table 178: I2C_SDA_HOLD_REG (0x5000137C)

Table 179: I2C_TX_ABRT_SOURCE_REG (0x50001380)

Table 180: I2C_SDA_SETUP_REG (0x50001394)

Table 181: I2C_ACK_GENERAL_CALL_REG (0x50001398)

Table 182: I2C_ENABLE_STATUS_REG (0x5000139C)

Table 183: I2C_IC_FS_SPKLEN_REG (0x500013A0)

Table 184: GPIO_IRQ0_IN_SEL_REG (0x50001400)

Table 185: GPIO_IRQ1_IN_SEL_REG (0x50001402)

Table 186: GPIO_IRQ2_IN_SEL_REG (0x50001404)

Table 187: GPIO_IRQ3_IN_SEL_REG (0x50001406)

Table 188: GPIO_IRQ4_IN_SEL_REG (0x50001408)

Table 189: GPIO_DEBOUNCE_REG (0x5000140C)

Table 190: GPIO_RESET_IRQ_REG (0x5000140E)

Table 191: GPIO_INT_LEVEL_CTRL_REG (0x50001410)

Table 192: KBRD_IRQ_IN_SEL0_REG (0x50001412)

Table 193: KBRD_IRQ_IN_SEL1_REG (0x50001414)

Table 194: KBRD_IRQ_IN_SEL2_REG (0x50001416)

Table 195: GP_ADC_CTRL_REG (0x50001500)

Table 196: GP_ADC_CTRL2_REG (0x50001502)

Table 197: GP_ADC_OFFP_REG (0x50001504)

Table 198: GP_ADC_OFFN_REG (0x50001506)

Table 199: GP_ADC_CLEAR_INT_REG (0x50001508)

Table 200: GP_ADC_RESULT_REG (0x5000150A)

Table 201: GP_ADC_DELAY_REG (0x5000150C)

Table 202: GP_ADC_DELAY2_REG (0x5000150E)

Table 203: CLK_REF_SEL_REG (0x50001600)

Table 204: CLK_REF_CNT_REG (0x50001602)

Table 205: CLK_REF_VAL_L_REG (0x50001604)

Table 206: CLK_REF_VAL_H_REG (0x50001606)

Table 207: P0_DATA_REG (0x50003000)

Table 208: P0_SET_DATA_REG (0x50003002)

Table 209: P0_RESET_DATA_REG (0x50003004)

Table 210: P00_MODE_REG (0x50003006)

Table 211: P01_MODE_REG (0x50003008)

Table 212: P02_MODE_REG (0x5000300A)

Table 213: P03_MODE_REG (0x5000300C)

Table 214: P04_MODE_REG (0x5000300E)

Table 215: P05_MODE_REG (0x50003010)

Table 216: P06_MODE_REG (0x50003012)

Table 217: P07_MODE_REG (0x50003014)

Table 218: P1_DATA_REG (0x50003020)

Table 219: P1_SET_DATA_REG (0x50003022)

Table 220: P1_RESET_DATA_REG (0x50003024)

Table 221: P10_MODE_REG (0x50003026)

Table 222: P11_MODE_REG (0x50003028)

Table 223: P12_MODE_REG (0x5000302A)

Table 224: P13_MODE_REG (0x5000302C)

Table 225: P14_MODE_REG (0x5000302E)

Table 226: P15_MODE_REG (0x50003030)

Table 227: P2_DATA_REG (0x50003040)

Table 228: P2_SET_DATA_REG (0x50003042)

Table 229: P2_RESET_DATA_REG (0x50003044)

Table 230: P20_MODE_REG (0x50003046)

Table 231: P21_MODE_REG (0x50003048)

Table 232: P22_MODE_REG (0x5000304A)

Table 233: P23_MODE_REG (0x5000304C)

Table 234: P24_MODE_REG (0x5000304E)

Table 235: P25_MODE_REG (0x50003050)

Table 236: P26_MODE_REG (0x50003052)

Table 237: P27_MODE_REG (0x50003054)

Table 238: P28_MODE_REG (0x50003056)

Table 239: P29_MODE_REG (0x50003058)

Table 240: P01_PADPWR_CTRL_REG (0x50003070)

Table 241: P2_PADPWR_CTRL_REG (0x50003072)

Table 242: P3_PADPWR_CTRL_REG (0x50003074)

Table 243: P3_DATA_REG (0x50003080)

Table 244: P3_SET_DATA_REG (0x50003082)

Table 245: P3_RESET_DATA_REG (0x50003084)

Table 246: P30_MODE_REG (0x50003086)

Table 247: P31_MODE_REG (0x50003088)

Table 248: P32_MODE_REG (0x5000308A)

Table 249: P33_MODE_REG (0x5000308C)

Table 250: P34_MODE_REG (0x5000308E)

Table 251: P35_MODE_REG (0x50003090)

Table 252: P36_MODE_REG (0x50003092)

Table 253: P37_MODE_REG (0x50003094)

Table 254: WATCHDOG_REG (0x50003100)

Table 255: WATCHDOG_CTRL_REG (0x50003102)

Table 256: CHIP_ID1_REG (0x50003200)

Table 257: CHIP_ID2_REG (0x50003201)

Table 258: CHIP_ID3_REG (0x50003202)

Table 259: CHIP_SWC_REG (0x50003203)

Table 260: CHIP_REVISION_REG (0x50003204)

Table 261: CHIP_CONFIG1_REG (0x50003205)

Table 262: CHIP_CONFIG2_REG (0x50003206)

Table 263: CHIP_CONFIG3_REG (0x50003207)

Table 264: CHIP_TEST1_REG (0x5000320A)

Table 265: CHIP_TEST2_REG (0x5000320B)

Table 266: SET_FREEZE_REG (0x50003300)

Table 267: RESET_FREEZE_REG (0x50003302)

Table 268: DEBUG_REG (0x50003304)

Table 269: GP_STATUS_REG (0x50003306)

Table 270: GP_CONTROL_REG (0x50003308)

Table 271: TIMER0_CTRL_REG (0x50003400)

Table 272: TIMER0_ON_REG (0x50003402)

Table 273: TIMER0_RELOAD_M_REG (0x50003404)

Table 274: TIMER0_RELOAD_N_REG (0x50003406)

Table 275: PWM2_DUTY_CYCLE (0x50003408)

Table 276: PWM3_DUTY_CYCLE (0x5000340A)

Table 277: PWM4_DUTY_CYCLE (0x5000340C)

Table 278: TRIPLE_PWM_FREQUENCY (0x5000340E)

Table 279: TRIPLE_PWM_CTRL_REG (0x50003410)

5. Specifications

Table 280: Absolute maximum ratings

Table 281: Recommended operating conditions

Table 282: DC characteristics

Table 283: Timing characteristics

Table 284: 16 MHz Crystal Oscillator: Recommended operating conditions

Table 285: 16 MHz Crystal Oscillator: Timing characteristics

Table 286: 32 kHz Crystal Oscillator: Recommended operating conditions

Table 287: 32 kHz Crystal Oscillator: Timing characteristics

Table 288: DC-DC converter: Recommended operating conditions

Table 289: DC-DC converter: DC characteristics

Table 290: Digital Input/Output: DC characteristics

Table 291: General purpose ADC: Recommended operating conditions

Table 292: General purpose ADC: DC characteristics

Table 293: General purpose ADC: Timing characteristics

Table 294: Radio: DC characteristics

Table 295: Radio: AC characteristics

Table 296: Stable low frequency RCX Oscillator: Timing characteristics

6. Package information

6.1 Moisture sensitivity level (MSL)

6.2 WLCSP handling

6.3 Soldering information

6.4 Package outlines

DATASHEET - FINAL DA14580 Low Power Bluetooth Smart SoC JANUARY 29, 2015 V3.1 D A 1 4 5 8 0 General description The DA14580 integrated circuit has a fully integrated radio transceiver and baseband processor for Blue- tooth® Smart. It can be used as a standalone applica- tion processor or as a data pump in hosted systems. The DA14580 supports a flexible memory architecture for storing Bluetooth profiles and custom application code, which can be updated over the air (OTA). The qualified Bluetooth Smart protocol stack is stored in a dedicated ROM. All software runs on the ARM® Cor- tex®-M0 processor via a simple scheduler. The Bluetooth Smart firmware includes the L2CAP ser- vice layer protocols, Security Manager (SM), Attribute Protocol (ATT), the Generic Attribute Profile (GATT) and the Generic Access Profile (GAP). All profiles pub- lished by the Bluetooth SIG as well as custom profiles are supported. The transceiver interfaces directly to the antenna and is fully compliant with the Bluetooth 4.1 standard. The DA14580 has dedicated hardware for the Link Layer implementation of Bluetooth Smart and interface controllers for enhanced connectivity capabilities. Features  Complies with Bluetooth V4.1, ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan)  Processing power  16 MHz 32 bit ARM Cortex-M0 with SWD inter- face  Dedicated Link Layer Processor  AES-128 bit encryption Processor  Memories  32 kB One-Time-Programmable (OTP) memory  42 kB System SRAM  84 kB ROM  8 kB Retention SRAM  Power management  Integrated Buck/Boost DC-DC converter  P0, P1, P2 and P3 ports with 3.3 V tolerance  Easy decoupling of only 4 supply pins  Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) battery cells  10-bit ADC for battery voltage measurement  Digital controlled oscillators  16 MHz crystal (±20 ppm max) and RC oscillator  32 kHz crystal (±50 ppm, ±500 ppm max) and RCX oscillator  General purpose, Capture and Sleep timers  Digital interfaces  General purpose I/Os: 14 (WLCSP34 package), 24 (QFN40 package), 32 (QFN48 package)  2 UARTs with hardware flow control up to 1 MBd  SPI+™ interface  I2C bus at 100 kHz, 400 kHz  3-axes capable Quadrature Decoder  Analog interfaces  4-channel 10-bit ADC  Radio transceiver  Fully integrated 2.4 GHz CMOS transceiver  Single wire antenna: no RF matching or RX/TX switching required  Supply current at VBAT3V: TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)  0 dBm transmit output power  -20 dBm output power in “Near Field Mode”  -93 dBm receiver sensitivity  Packages:  WLCSP 34 pins, 2.436 mm x 2.436 mm  QFN 40 pins, 5 mm x 5 mm  QFN 48 pins, 6 mm x 6 mm  KGD (wafer, dice) ________________________________________________________________________________________________ System diagram L o w P o w e r B u e t o o t h S m a r t l © 2014 Dialog Semiconductor 1 www.dialog-semiconductor.com S o C

1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 ARM CORTEXM0 CPU. . . . . . . . . . . . . . . . . . 9 3.2 BLUETOOTH SMART. . . . . . . . . . . . . . . . . . . . 9 3.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . 10 3.2.3 SmartSnippets   3.3 MEMORIES. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 11 3.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . 12 3.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6.3 I2C interface . . . . . . . . . . . . . . . . . . . . . 12 3.6.4 General purpose ADC . . . . . . . . . . . . . . 13 3.6.5 Quadrature decoder. . . . . . . . . . . . . . . . 13 3.6.6 Keyboard controller . . . . . . . . . . . . . . . . 13 3.6.7 Input/output ports. . . . . . . . . . . . . . . . . . 13 3.7 TIMERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7.1 General purpose timers . . . . . . . . . . . . . 13 3.7.2 Wake-Up timer. . . . . . . . . . . . . . . . . . . . 14 3.7.3 Watchdog timer . . . . . . . . . . . . . . . . . . . 14 3.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 15 4. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6. Package information . . . . . . . . . . . . . . . . . . . . . . 154 6.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 154 6.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 154 6.3 SOLDERING INFORMATION . . . . . . . . . . . . 154 6.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 155 D A 1 4 5 8 0 L o w P o w e r B u e t o o t h S m a r t l © 2014 Dialog Semiconductor 2 Final - January 29, 2015 v3.1 S o C

l i © 2 0 1 4 D a o g S e m c o n d u c t o r i 1. Block diagram 24 April 2012 ARM Cortex M0 CORE SWD (JTAG) System/ Exchange RAM 42 KB Ret. RAM 2 KB Ret. RAM2 3 KB Ret. RAM3 2 KB Ret. RAM4 1 KB OTP 32 KB ROM 84 KB 3 i F n a l - J a n u a r y 2 9 , 2 0 1 5 v 3 . 1 r e l l o r t n o C y r o m e M DMA OTPC XTAL 32.768 kHz XTAL 16 MHz BLE Core DCDC (BUCK/BOOST) LDO SYS LDO RET LDO LDO LDO SYS SYS RF AES-128 LINK LAYER HARDWARE RC 16 MHz RC 32 kHz RCX POReset Radio Transceiver e g d i r b B P A / K C O L C R E W O P ) U M P ( t n e m e g a n a M P U E K A W R E M T I SW TIMER Timer 0 1xPWM Timer 2 3xPWM D R A O B Y E K L R T C T R A U 2 T R A U I P S C 2 I O F F I O F F I O F F I C D A P G GPIO MULTIPLEXING D A U Q R E D O C E D Figure 1 DA14580 block diagram Low Power Bluetooth Smart SoC DA14580

Pinout 2. The DA14580 comes in three packages: 2. A Quad Flat Package No Leads (QFN) with 48 pins 3. A Quad Flat Package No Leads (QFN) with 40 pins 1. A Wafer Level Chip Scale Package (WLCSP) with 34 balls The actual pin/ball assignment is depicted in the follow- ing figures: D A 1 4 5 8 0 A B C D E F P0_0 P0_1 P0_2 P0_3 P3_0 P0_4 P0_5 P2_1 P0_6 P3_1 P0_7 P3_2 Pin 0: GND plane 1 2 3 RFIO m 4 RFIOp GND P1_2 P0_1 VDCDC_RF P1_3 XTAL16M m XTAL16Mp S W_CLK S W DIO VBAT1V S WITCH Figure 2 WLCSP34 ball assignment GND VBAT_RF VBAT3V P0_7 XTAL32Kp P1_0 VDCDC P0_2 P0_4 RST GND GND GND P1_1 5 GND 6 VPP P0_0 P0_3 P0_5 P0_6 XTAL32Km 0 _ 2 P 9 _ 2 P P P V 8 _ 2 P 7 _ 2 P C N p O F R I m O F R I 7 _ 3 P 6 _ 2 P 5 _ 2 P F R _ C D C D V 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 DA14580 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 3 2 4 2 m K 2 3 L A T X p K 2 3 L A T X 3 _ 3 P 2 _ 2 P 4 _ 3 P F R _ T A B V V 3 T A B V D N G T S R 3 _ 2 P 4 _ 2 P C D C D V Figure 3 QFN48 pin assignment 36 35 34 33 32 31 30 29 28 27 26 25 P3_6 XTAL16Mm XTAL16Mp P1_3 P1_2 SW_CLK SWDIO P1_1 VBAT1V P1_0 SWITCH P3_5 l L o w P o w e r B u e t o o t h S m a r t © 2014 Dialog Semiconductor 4 Final - January 29, 2015 v3.1 S o C

D A 1 4 5 8 0 0 _ 2 P 9 _ 2 P P P V 8 _ 2 P 7 _ 2 P p O F R I m O F R I 6 _ 2 P 5 _ 2 P F R _ C D C D V 0 4 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 DA14580 (Top View) P0_0 P0_1 P0_2 P0_3 NC P0_4 P0_5 P2_1 P0_6 P0_7 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 XTAL16Mm XTAL16Mp P1_3 P1_2 SW_CLK SWDIO P1_1 VBAT1V P1_0 SWITCH 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 Pin 0: GND plane m K 2 3 L A T X p K 2 3 L A T X 2 _ 2 P F R _ T A B V V 3 T A B V D N G T S R 3 _ 2 P 4 _ 2 P C D C D V Figure 4 QFN40 pin assignment Table 1: Ordering information (samples) Part number DA14580-01UNA DA14580-01A31 DA14580-01AT1 Package WLSCP34 QFN48 QFN40 Size (mm) 2.436 x 2.436 6 x 6 5 x 5 Shipment form Mini-reel Tray Tray Pack quantity 50/100/1000 50 50 Table 2: Ordering information (production) Part number DA14580-01UNA DA14580-01A32 DA14580-01AT2 DA14580-01WO4 DA14580-01WC4 Package WLSCP34 QFN48 QFN40 KGD KGD Size (mm) 2.436 x 2.436 6 x 6 5 x 5 wafer dice Shipment form Pack quantity Mini-reel Reel Reel 5000 4000 5000 Contact Dialog Semiconductor sales office Contact Dialog Semiconductor sales office L o w P o w e r B u e t o o t h S m a r t l © 2014 Dialog Semiconductor 5 Final - January 29, 2015 v3.1 S o C

Table 3: Pin Description PIN NAME TYPE General Purpose I/Os P0_0 DIO P0_1 DIO P0_2 DIO P0_3 DIO P0_4 DIO P0_5 DIO P0_6 DIO P0_7 DIO P1_0 DIO P1_1 DIO P1_2 DIO P1_3 DIO P1_4/SWCLK DIO P1_5/SW_DIO DIO P2_0 DIO P2_1 DIO P2_2 DIO P2_3 DIO P2_4 DIO P2_5 DIO P2_6 DIO P2_7 DIO P2_8 DIO P2_9 DIO P3_0 DIO P3_1 DIO P3_2 DIO P3_3 DIO P3_4 DIO P3_5 DIO P3_6 DIO P3_7 DIO Debug interface SWDIO/P1_5 DIO DIO SW_CLK/ P1_4 Clocks XTAL16Mp XTAL16Mm XTAL32kp XTAL32km Quadrature decoder QD_CHA_X QD_CHB_X QD_CHA_Y QD_CHB_Y AI AO AI AO DI DI DI DI Drive (mA) 4.8 4.8 4.8 4.8 4.8 4.8 Reset state (Note ) I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PU I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PU I-PD DESCRIPTION INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. This signal is the JTAG clock by default This signal is the JTAG data I/O by default INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. NOTE: This port is only available on the QFN40/QFN48 pack- ages. INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contain state retention mechanism dur- ing power down. NOTE: This port is only available on the QFN48 package. INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Can also be used as a GPIO INPUT JTAG clock signal. Can also be used as a GPIO INPUT. Crystal input for the 16 MHz XTAL OUTPUT. Crystal output for the 16 MHz XTAL INPUT. Crystal input for the 32.768 kHz XTAL OUTPUT. Crystal output for the 32.768 kHz XTAL INPUT. Channel A for the X axis. Mapped on Px ports INPUT. Channel B for the X axis. Mapped on Px ports INPUT. Channel A for the Y axis. Mapped on Px ports INPUT. Channel B for the Y axis. Mapped on Px ports D A 1 4 5 8 0 l L o w P o w e r B u e t o o t h S m a r t S o C © 2014 Dialog Semiconductor 6 Final - January 29, 2015 v3.1

Table 3: Pin Description PIN NAME TYPE Drive (mA) Reset state (Note ) DI DI DO DI DO DI QD_CHA_Z QD_CHB_Z SPI bus interface SPI_CLK SPI_DI SPI_DO SPI_EN I2C bus interface SDA DIO/DIOD SCL DIO/DIOD UART interface UTX URX URTS UCTS UTX2 URX2 URTS2 UCTS2 Analog interface ADC[0] ADC[1] ADC[2] ADC[3] Radio transceiver RFIOp RFIOm Miscellaneous RST VBAT_RF VDCDC_RF VPP Power supply VBAT3V DO DI DO DI DO DI DO DI AI AI AI AI AIO AIO DI AIO AIO AI AIO DESCRIPTION INPUT. Channel A for the Z axis. Mapped on Px ports INPUT. Channel B for the Z axis. Mapped on Px ports INPUT/OUTPUT. SPI Clock. Mapped on Px ports INPUT. SPI Data input. Mapped on Px ports OUTPUT. SPI Data output. Mapped on Px ports INPUT. SPI Clock enable (active LOW). Mapped on Px ports INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on Px ports INPUT/OUTPUT. I2C bus Clock with open drain port. In open drain mode, SCL is monitored to support bit stretching by a slave. Mapped on Px ports. OUTPUT. UART transmit data. Mapped on Px ports INPUT. UART receive data. Mapped on Px ports OUTPUT. UART Request to Send. Mapped on Px ports INPUT. UART Clear to Send. Mapped on Px ports OUTPUT. UART 2 transmit data. Mapped on Px ports INPUT. UART 2 receive data. Mapped on Px ports OUTPUT. UART 2 Request to Send. Mapped on Px ports INPUT. UART 2 Clear to Send. Mapped on Px ports INPUT. Analog to Digital Converter input 0. Mapped on P0[0] INPUT. Analog to Digital Converter input 1. Mapped on P0[1] INPUT. Analog to Digital Converter input 2. Mapped on P0[2] INPUT. Analog to Digital Converter input 3. Mapped on P0[3] RF input/output. Impedance 50  RF ground INPUT. Reset signal (active high). Must be connected to GND if not used. Connect to VBAT3V on the PCB Connect to VDCDC on the PCB INPUT. This pin is used while OTP programming and testing. OTP programming: VPP = 6.8 V ± 0.25 V OTP Normal operation: leave VPP floating INPUT/OUTPUT. Battery connection. Used for a single coin bat- tery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to pin VBAT1V, this is the second output of the DC-DC converter. D A 1 4 5 8 0 L o w P o w e r B u e t o o t h S m a r t l © 2014 Dialog Semiconductor 7 Final - January 29, 2015 v3.1 S o C

Table 3: Pin Description PIN NAME TYPE Drive (mA) Reset state (Note ) VBAT1V SWITCH VDCDC GND AI AIO AO AIO - - DESCRIPTION INPUT. Battery connection. Used for an alkaline or a NiMh bat- tery (1.5 V). If a single coin battery (3 V) is attached to pin VBAT3V,this pin must be connected to GND. INPUT/OUTPUT. Connection for the external DC-DC converter inductor. Output of the DC-DC converter Ground D A 1 4 5 8 0 L o w P o w e r B u e t o o t h S m a r t l © 2014 Dialog Semiconductor 8 Final - January 29, 2015 v3.1 S o C

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