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EDA实验七人表决器（代码+连线图）.doc
七人表决器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ch IS
PORT (
A: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
AG,DISAG: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
CO: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ch;
ARCHITECTURE A OF ch IS
BEGIN
PROCESS(A)
VARIABLE B,C: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
B:="0000";
C:="0000";
FOR N IN 0 TO 6 LOOP
IF(A(N)='1')THEN
B:=B+1;
END IF;
END LOOP;
C:=7-B;
AG<=B;
DISAG<=C;
IF AG>=4 THEN
CO<="0001";
ELSE
CO<="0000";
END IF;
END PROCESS;
END A;
Cnt6a
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt6a is
port(
cp,reset:in std_logic;
sel:out std_logic_vector(2 downto 0)
);
end cnt6a;
architecture b of cnt6a is
signal sec:std_logic_vector(2 downto 0);
begin
process(reset,cp)
begin
if(reset='0') then
sec<="000";
elsif(cp'event and cp='1') then
if(sec="101")then
sec<="000";
else
sec<=sec+1;
end if;
end if;
end process;
sel<=sec;
end b;
六选一计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MUX6 is
port(
hh,hl,mh,ml,sh,sl:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
cntout:out std_logic_vector(3 downto 0)
);
end MUX6;
architecture a of MUX6 is
begin
PROCESS(sel)
begin
CASE sel IS
WHEN"000"=>cntout<=sl(3 downto 0);
WHEN"001"=>cntout<=sh(3 downto 0);
WHEN"010"=>cntout<=ml(3 downto 0);
WHEN"011"=>cntout<=mh(3 downto 0);
WHEN"100"=>cntout<=hl(3 downto 0);
WHEN"101"=>cntout<=hh(3 downto 0);
when others=>cntout<="0000";
END CASE;
END PROCESS;
END a;
BCD 七段显示器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity BCD is
port(
bcd1 :in std_logic_vector(3 downto 0);
SEGOUT:out std_logic_vector(0 TO 6)
);
end BCD;
ARCHITECTURE A OF BCD IS
BEGIN
PROCESS(bcd1)
BEGIN
CASE bcd1 IS
WHEN "0000"=>SEGOUT<="1111110";
WHEN "0001"=>SEGOUT<="0110000";
WHEN "0010"=>SEGOUT<="1101101";
WHEN "0011"=>SEGOUT<="1111001";
WHEN "0100"=>SEGOUT<="0110011";
WHEN "0101"=>SEGOUT<="1011011";
WHEN "0110"=>SEGOUT<="1011111";
WHEN "0111"=>SEGOUT<="1110000";
WHEN "1000"=>SEGOUT<="1111111";
WHEN "1001"=>SEGOUT<="1111011";
WHEN OTHERS=>SEGOUT<="0000000";
END CASE;
END PROCESS;
END A;
数字钟
MUX2
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MUX2 is
port(
CLK,SEL,Y0,Y1:IN STD_LOGIC;
OUT1: OUT STD_LOGIC
);
END MUX2;
ARCHITECTURE A OF MUX2 IS
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF (SEL='0')THEN
OUT1<=Y0;
ELSE OUT1<=Y1;
END IF;
END IF;
END PROCESS;
END A;
Cnt64
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt24 is
port(
CLK,EN,CR:in std_logic;
CO:out std_logic;
QH,QL:out std_logic_vector(3 downto 0)
);
end cnt24;
architecture a of cnt24 is
signal QNH,QNL:std_logic_vector(3 downto 0);
begin
CO<='1'when(QNL=3 AND QNH=2 AND EN='1')
ELSE'0';
PROCESS(CLK,CR)
BEGIN
IF(CR='0') THEN
QNH<="0000";
QNL<="0000";
ELSIF (CLK'EVENT AND CLK='1') THEN
IF(EN='1') THEN
IF (QNL=3 AND QNH=2)THEN
QNH<="0000";
QNL<="0000";
ELSIF QNL=9 THEN
QNL<="0000";
IF QNH=5 THEN
QNH<="0000";
ELSE
QNH<=QNH+1;
END IF;
ELSE
QNL<=QNL+1;
END IF ;
END IF;
END IF;
END PROCESS;
QH<=QNH;
QL<=QNL;
END a;
Cnt60
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port(
CLK,EN,CR:in std_logic;
CO:out std_logic;
QH,QL:out std_logic_vector(3 downto 0)
);
end cnt60;
architecture a of cnt60 is
signal QNH,QNL:std_logic_vector(3 downto 0);
begin
PROCESS(CLK,CR)
BEGIN
IF(CR='0') THEN
QNH<="0000";
QNL<="0000";
ELSIF (CLK'EVENT AND CLK='1') THEN
IF(EN='1') THEN
IF QNL=9 THEN
QNL<="0000";CO<='0';
IF QNH=5 THEN
QNH<="0000";CO<='1';
ELSE
QNH<=QNH+1;CO<='0';
END IF;
ELSE
QNL<=QNL+1;CO<='0';
END IF ;
END IF;
END IF;
END PROCESS;
QH<=QNH;
QL<=QNL;
END a;
MUX6
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MUX6 is
port(
hh,hl,mh,ml,sh,sl:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
cntout:out std_logic_vector(3 downto 0)
);
end MUX6;
architecture a of MUX6 is
begin
PROCESS(sel)
begin
CASE sel IS
WHEN"000"=>cntout<=sl(3 downto 0);
WHEN"001"=>cntout<=sh(3 downto 0);
WHEN"010"=>cntout<=ml(3 downto 0);
WHEN"011"=>cntout<=mh(3 downto 0);
WHEN"100"=>cntout<=hl(3 downto 0);
WHEN"101"=>cntout<=hh(3 downto 0);
when others=>cntout<="0000";
END CASE;
END PROCESS;
END a;
Cnt6a
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cnt6a is
port(
cp,reset:in std_logic;
sel:out std_logic_vector(2 downto 0)
);
end cnt6a;
architecture b of cnt6a is
signal sec:std_logic_vector(2 downto 0);
begin
process(reset,cp)
begin
if(reset='0') then
sec<="000";
elsif(cp'event and cp='1') then
if(sec="101")then
sec<="000";
else
sec<=sec+1;
end if;
end if;
end process;
sel<=sec;
end b;
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