STM32F103RBT6芯片资料.pdf

发布时间：2022-05-30 发布人：admin 分类：说明书资料大小：1.06M 资料格式：pdf 举报版权申诉

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Table 1. Device summary

1 Introduction

2 Description

2.1 Device overview

Table 2. Device features and peripheral counts (STM32F103xx performance line)

2.2 Overview

Figure 1. STM32F103xx performance line block diagram

3 Pin descriptions

Figure 2. STM32F103xx performance line LQFP100 pinout

Figure 3. STM32F103xx performance line LQFP64 pinout

Figure 4. STM32F103xx performance line LQFP48 pinout

Figure 5. STM32F103xx performance line BGA100 ballout

Table 3. Pin definitions

4 Memory mapping

Figure 6. Memory map

5 Electrical characteristics

5.1 Test conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

Figure 7. Pin loading conditions

Figure 8. Pin input voltage

5.1.6 Power supply scheme

Figure 9. Power supply scheme

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

5.2 Absolute maximum ratings

Table 4. Voltage characteristics

Table 5. Current characteristics

Table 6. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 7. General operating conditions

5.3.2 Operating conditions at power-up / power-down

Table 8. Operating conditions at power-up / power-down

5.3.3 Embedded reset and power control block characteristics

Table 9. Embedded reset and power control block characteristics

5.3.4 Embedded reference voltage

Table 10. Embedded internal reference voltage

5.3.5 Supply current characteristics

Table 11. Maximum current consumption in Run and Sleep modes

Table 12. Maximum current consumption in Stop and Standby modes

Table 13. Typical current consumption in Run and Sleep modes

Table 14. Typical current consumption in Stop and Standby modes

5.3.6 External clock source characteristics

Table 15. High-speed external (HSE) user clock characteristics

Table 16. Low-speed external user clock characteristics

Figure 11. High-speed external clock source AC timing diagram

Figure 12. Low-speed external clock source AC timing diagram

Table 17. HSE 4-16 MHz oscillator characteristics

Figure 13. Typical application with a 8-MHz crystal

Table 18. LSE oscillator characteristics (fLSE = 32.768 kHz)

Figure 14. Typical application with a 32.768 kHz crystal

5.3.7 Internal clock source characteristics

Table 19. HSI oscillator characteristics

Table 20. LSI oscillator characteristics

Table 21. Low-power mode wakeup timings

5.3.8 PLL characteristics

Table 22. PLL characteristics

5.3.9 Memory characteristics

Table 23. Flash memory characteristics

Table 24. Flash memory endurance and data retention

5.3.10 EMC characteristics

Table 25. EMS characteristics

Table 26. EMI characteristics

5.3.11 Absolute maximum ratings (electrical sensitivity)

Table 27. ESD absolute maximum ratings

Table 28. Electrical sensitivities

5.3.12 I/O port pin characteristics

Table 29. I/O static characteristics

Figure 15. Unused I/O pin connection

Table 30. Output voltage characteristics

Table 31. I/O AC characteristics

Figure 16. I/O AC characteristics definition

5.3.13 NRST pin characteristics

Table 32. NRST pin characteristics

Figure 17. Recommended NRST pin protection

5.3.14 TIM timer characteristics

Table 33. TIMx characteristics

5.3.15 Communications interfaces

Table 34. I2C characteristics

Figure 18. I2C bus AC waveforms and measurement circuit

Table 35. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)

Table 36. SPI characteristics

Figure 19. SPI timing diagram - slave mode and CPHA = 0

Figure 20. SPI timing diagram - slave mode and CPHA = 11)

Figure 21. SPI timing diagram - master mode

Table 37. USB DC electrical characteristics

Figure 22. USB timings: definition of data signal rise and fall time

Table 38. USB: Full speed electrical characteristics

5.3.16 CAN (controller area network) interface

5.3.17 12-bit ADC characteristics

Table 39. ADC characteristics

Table 40. ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 kW, VDDA = 3.3 V)

Figure 23. ADC accuracy characteristics

Figure 24. Typical connection diagram using the ADC

Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA)

Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA)

5.3.18 Temperature sensor characteristics

Table 41. TS characteristics

6 Package characteristics

Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline

Table 42. LFBGA100 - low profile fine pitch ball grid array package mechanical data

Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

Figure 29. LQFP100 - 100-pin low-profile quad flat package outline

Table 43. LQFP100 - 100-pin low-profile quad flat package mechanical data

Figure 30. LQFP64 - 64 pin low-profile quad flat package outline

Table 44. LQFP64 - 64 pin low-profile quad flat package mechanical data

Figure 31. LQFP48 - 48 pin low-profile quad flat package outline

Table 45. LQFP48 - 48 pin low-profile quad flat package mechanical data

6.1 Thermal characteristics

Table 46. Thermal characteristics

7 Order codes

Table 47. Order codes

7.1 Future family enhancements

8 Revision history

STM32F103x6 STM32F103x8 STM32F103xB Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces Preliminary Data Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware division – Nested interrupt controller with 43 maskable interrupt channels – Interrupt processing (down to 6 CPU cycles) with tail chaining ■ Memories – 32-to-128 Kbytes of Flash memory – 6-to-20 Kbytes of SRAM ■ Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz quartz oscillator – Internal 8 MHz factory-trimmed RC – Internal 32 kHz RC – PLL for CPU clock – Dedicated 32 kHz oscillator for RTC with calibration Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers 2 x 12-bit, 1 µs A/D converters (16-channel) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Synchronizable with advanced control timer – Temperature sensor ■ DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs LQFP48 7 x 7 mm LQFP100 14 x 14 mm LQFP64 10 x 10 mm BGA100 10 x 10 mm ■ Debug mode – Serial wire debug (SWD) & JTAG interfaces ■ Up to 80 fast I/O ports – 32/49/80 5 V-tolerant I/Os – All mappable on 16 external interrupt vectors – Atomic read/modify/write operations ■ Up to 7 timers – Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter – 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output Dead time generation and emergency stop – 2 x 16-bit watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter ■ Up to 9 communication interfaces – Up to 2 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 2 SPIs (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full speed interface Table 1. Device summary Reference Root part number STM32F103x6 STM32F103C6, STM32F103R6 STM32F103C8, STM32F103R8 STM32F103V8 STM32F103x8 STM32F103xB STM32F103RB STM32F103VB July 2007 Rev 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/67 www.st.com 1 ■ ■

Contents Contents STM32F103xx 1 2 3 4 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 5.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.4 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.1 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27 5.3.2 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.4 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.6 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.7 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.10 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 42 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3.12 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/67

STM32F103xx Contents 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 54 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6 7 8 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.1 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3/67

List of tables List of tables STM32F103xx Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Device features and peripheral counts (STM32F103xx performance line). . . . . . . . . . . . . . 7 Table 2. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 5. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 7. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 8. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9. Table 10. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Maximum current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12. Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Table 17. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 18. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 20. Table 21. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 22. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 23. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24. Table 25. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 26. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 27. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 28. Table 29. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 30. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 31. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 32. Table 33. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 34. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 35. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 36. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 37. Table 38. USB: Full speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 39. ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 kΩ, VDDA = 3.3 V). . . . . . . . . 55 Table 40. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 41. Table 42. LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 59 LQFP100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 61 Table 43. LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 62 Table 44. LQFP48 – 48 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 63 Table 45. Table 46. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 47. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4/67

STM32F103xx List of figures List of figures STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 1. STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 2. STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. STM32F103xx performance line BGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 8. Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 12. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 13. Typical application with a 8-MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 14. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 15. Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 16. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 17. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 18. Figure 19. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 20. SPI timing diagram - slave mode and CPHA = 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 21. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 22. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 23. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 57 Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 57 Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 59 Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 60 Figure 29. LQFP100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 61 LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 30. Figure 31. LQFP48 – 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5/67

Introduction 1 Introduction STM32F103xx This datasheet provides the STM32F103xx performance line ordering information and mechanical device characteristics. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming reference manual, pm0042, available from www.st.com. For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference Manual. 2 Description The STM32F103xx performance line family incorporates the high-performance ARM Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 128Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx performance line family operates in the −40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows to design low-power applications. The complete STM32F103xx performance line family includes devices in 4 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx performance line microcontroller family suitable for a wide range of applications: Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC Figure 1 shows the general block diagram of the device family. 6/67 ● ● ● ● ●

STM32F103xx Description 2.1 Device overview Table 2. Device features and peripheral counts (STM32F103xx performance line) STM32F103Vx STM32F103Rx Peripheral STM32F103Cx Flash - Kbytes SRAM - Kbytes s General purpose r e m T Advanced Control i i n o i t a c n u m m o C SPI I2C USART USB CAN GPIOs 12-bit synchronized ADC Number of channels CPU frequency Operating voltage 32 10 2 1 1 2 1 1 64 20 3 2 2 3 1 1 32 10 2 1 1 2 1 1 1 32 2 10 channels 64 128 64 128 20 3 2 2 3 1 1 1 49 20 3 1 2 2 3 1 1 80 2 16 channels 72 MHz 2.0 to 3.6 V Operating temperature -40 to +85 °C / -40 to +105 °C Packages LQFP48 LQFP64 LQFP100, BGA100 7/67

Description 2.2 STM32F103xx Overview ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. Embedded Flash memory Up to 128 Kbytes of embedded Flash is available for storing programs and data. Embedded SRAM Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex- M3) and 16 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16 external interrupt lines. 8/67 ● ● ● ● ● ● ● ● ●

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