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S5P6818芯片手册.pdf
S5P6818
Important Notice
Trademarks
Chip Handling Guide
Revision History
Table of Contents
List of Figures
List of Tables
List of Examples
List of Conventions
List of Acronyms
1 Product Overview
1.1 Introduction
1.2 Features
1.3 Block Diagram
1.4 Brief Functional Specification
1.4.1 CPU
1.4.2 Clock & Power Management
1.4.3 DMA
1.4.4 Interrupt Controller
1.4.5 Timer & Watchdog Timer
1.4.6 RTC
1.4.7 Memory Controller
1.4.8 GPIO Controller
1.4.9 Ethernet MAC Controller
1.4.10 SD/MMC Controller
1.4.11 PPM
1.4.12 PWM
1.4.13 ADC
1.4.14 DAC
1.4.15 I2C
1.4.16 SPI/SSP
1.4.17 MPEG-TS
1.4.18 UART& ISO7816 Sim Card Interface
1.4.19 USB
1.4.20 I2S
1.4.21 AC97
1.4.22 SPDIF Tx, Rx
1.4.23 PDM
1.4.24 Display Controller
1.4.25 Video Post Processor
1.4.26 Video Input Processor
1.4.27 Multi Format MPEG codec
1.4.28 3D Graphic Controller
1.4.29 Security IP
1.4.30 Unique Chip ID
1.4.31 Operating Conditions
1.4.32 Package
2 Mechanical Dimension & IO Function Description
2.1 Mechanical Dimension
2.2 FCBGA Ball Map
2.3 I/O Function Description
2.3.1 Ball List Table
2.4 Ball List Table: sorted by Function
2.4.1 MCU-A
2.4.2 MCU-S
2.4.3 Digital RGB
2.4.4 HDMI
2.4.5 LVDS
2.4.6 MIPI DSI
2.4.7 MIPI CSI
2.4.8 VIP
2.4.9 Ethernet MAC
2.4.10 MPEG-TS Interface
2.4.11 UART_ISO7816
2.4.12 I2C
2.4.13 SPI/SSP
2.4.14 PWM
2.4.15 PPM
2.4.16 PDM
2.4.17 SPDIF
2.4.18 SD/MMC
2.4.19 USB 2.0Host
2.4.20 USB 2.0 HSIC HOST
2.4.21 USB 2.0 OTG
2.4.22 I2S & AC97
2.4.23 ADC
2.4.24 ALIVE GPIO
2.4.25 JTAG
2.4.26 Crystal PLL & RTC
2.4.27 Miscellaneous
2.4.28 Not Connect (NC)
2.4.29 Video DAC
2.4.30 TMU (Temperature Monitor Unit)
2.4.31 Power: VDD
2.4.32 Power: GND
3 System Boot
3.1 Overview
3.2 Functional Description
3.2.1 System Configuration
3.3 External Static Memory Boot
3.3.1 External Static Memory Boot Features
3.3.2 External Static Memory Boot System Configuration
3.3.3 External Static Memory Boot Operation
3.4 Internal ROM Boot
3.4.1 Features
3.4.2 System Configuration for the Internal ROM Booting
3.4.3 SPI Boot
3.4.3.1 Features
3.4.3.2 Operation
3.4.4 UART Boot
3.4.4.1 Features
3.4.4.2 Operation
3.4.5 USB Boot
3.4.5.1 Features
3.4.5.2 Operation
3.4.5.3 USB Descriptors
3.4.6 SDHC Boot
3.4.6.1 Features
3.4.6.2 Operation
3.4.7 SDFS Boot
3.4.8 NANDBOOT with Error Correction
3.4.8.1 Features
3.4.8.2 Operation
3.4.8.3 How to store User boot code into the NAND Flash Memory
3.4.9 Additional Information
3.4.9.1 Boot Header
3.4.9.2 ALIVE Power Control
3.4.9.3 Exception Vector Redirection
3.4.9.4 CRC32 Error Check
3.4.9.5 Data Decryption with AES128 ECB mode to use Hidden Key
3.4.9.6 Boot Scenario
3.4.9.7 Multi CPU Boot
4 System Control
4.1 Overview
4.2 Features
4.3 Block Diagram
4.4 Clock Manager Functional Description
4.4.1 PLL (Phase Locked Loop)
4.4.1.1 PMS Value
4.4.1.2 Setting Guide of SSCG_EN, SEL_PF, MFR and MRR
4.4.1.3 PDIV/ MDIV/ SDIV Values for PLL0, PLL1
4.4.1.4 PDIV/ MDIV/ SDIV Values for PLL2, PLL3
4.4.1.5 PLL Power Down
4.4.2 Change PLL Value
4.4.3 Clock Generator
4.4.3.1 Clocks Summary
4.4.3.2 CPU0 Clock
4.4.3.3 System Bus Clock (Core clock)
4.4.3.4 Memory Bus Clock (MCU Clock)
4.4.3.5 GPU (Graphic Processing Unit) Clock
4.4.3.6 MFC (Multi Function Codec) Clock
4.5 Power Manager
4.5.1 Power Manager Overview
4.5.2 Power Down Mode Operation
4.5.2.1 IDLE Mode
4.5.2.2 STOP Mode
4.5.2.3 SLEEP Mode 1, SLEEP Mode 2
4.5.2.4 GPIO as a Wake up Source
4.6 Reset Generation
4.6.1 Power On Reset Sequence
4.6.2 Sleep Mode Wakeup Sequence
4.6.3 Power off sequence
4.6.4 Software Reset and GPIO Reset
4.6.5 Watchdog Reset
4.6.6 nPORST, Software Reset, Watchdog Reset and GPIO Reset
4.7 Tie Off
4.8 AXI BUS
4.8.1 Programmable Quality of Service (ProgQoS)
4.8.2 Arbitration Scheme
4.8.2.1 RR Schemes
4.9 Register Description
4.9.1 Register Map Summary
4.9.1.1 CLKMODEREG0
4.9.1.2 CLKMODEREG1
4.9.1.3 PLLSETREG0
4.9.1.4 PLLSETREG1
4.9.1.5 PLLSETREG2
4.9.1.6 PLLSETREG3
4.9.1.7 CLKDIVREG0
4.9.1.8 CLKDIVREG1
4.9.1.9 CLKDIVREG2
4.9.1.10 CLKDIVREG3
4.9.1.11 CLKDIVREG4
4.9.1.12 CLKDIVREG5
4.9.1.13 CLKDIVREG6
4.9.1.14 CLKDIVREG7
4.9.1.15 CLKDIVREG8
4.9.1.16 PLLSETREG0_SSCG
4.9.1.17 PLLSETREG1_SSCG
4.9.1.18 PLLSETREG2_SSCG
4.9.1.19 PLLSETREG3_SSCG
4.9.1.20 GPIOWAKEUPRISEENB
4.9.1.21 GPIOWAKEUPFALLENB
4.9.1.22 GPIORSTENB
4.9.1.23 GPIOWKENB
4.9.1.24 INTENB
4.9.1.25 GPIOINTPEND
4.9.1.26 RESETSTATUS
4.9.1.27 INTENABLE
4.9.1.28 INTPEND
4.9.1.29 PWRCONT
4.9.1.30 PWRMODE
4.9.1.31 PADSTRENGTHGPIOAL
4.9.1.32 SYSRSTCONFIG
4.9.2 Tieoff
4.9.2.1 TIEOFFREG00
4.9.2.2 TIEOFFREG01
4.9.2.3 TIEOFFREG02
4.9.2.4 TIEOFFREG03
4.9.2.5 TIEOFFREG04
4.9.2.6 TIEOFFREG05
4.9.2.7 TIEOFFREG06
4.9.2.8 TIEOFFREG07
4.9.2.9 TIEOFFREG08
4.9.2.10 TIEOFFREG09
4.9.2.11 TIEOFFREG10
4.9.2.12 TIEOFFREG11
4.9.2.13 TIEOFFREG12
4.9.2.14 TIEOFFREG13
4.9.2.15 TIEOFFREG14
4.9.2.16 TIEOFFREG15
4.9.2.17 TIEOFFREG16
4.9.2.18 TIEOFFREG17
4.9.2.19 TIEOFFREG18
4.9.2.20 TIEOFFREG19
4.9.2.21 TIEOFFREG20
4.9.2.22 TIEOFFREG21
4.9.2.23 TIEOFFREG22
4.9.2.24 TIEOFFREG23
4.9.2.25 TIEOFFREG24
4.9.2.26 TIEOFFREG25
4.9.2.27 TIEOFFREG26
4.9.2.28 TIEOFFREG27
4.9.2.29 TIEOFFREG28
4.9.2.30 TIEOFFREG29
4.9.2.31 TIEOFFREG30
4.9.2.32 TIEOFFREG31
4.9.2.33 TIEOFFREG32
4.9.2.34 TIEOFFREG41
4.9.2.35 TIEOFFREG42
4.9.2.36 TIEOFFREG43
4.9.2.37 TIEOFFREG44
4.9.2.38 TIEOFFREG45
4.9.2.39 TIEOFFREG46
4.9.2.40 TIEOFFREG47
4.9.2.41 TIEOFFREG48
4.9.2.42 TIEOFFREG49
4.9.2.43 TIEOFFREG50
4.9.2.44 TIEOFFREG51
4.9.2.45 TIEOFFREG52
4.9.2.46 TIEOFFREG53
4.9.2.47 TIEOFFREG54
4.9.2.48 TIEOFFREG55
4.9.2.49 TIEOFFREG56
4.9.2.50 TIEOFFREG57
4.9.2.51 TIEOFFREG58
4.9.2.52 TIEOFFREG59
4.9.2.53 TIEOFFREG60
4.9.2.54 TIEOFFREG61
4.9.2.55 TIEOFFREG62
4.9.2.56 TIEOFFREG63
4.9.2.57 TIEOFFREG64
4.9.2.58 TIEOFFREG65
4.9.2.59 TIEOFFREG66
4.9.2.60 TIEOFFREG67
4.9.2.61 TIEOFFREG68
4.9.2.62 TIEOFFREG69
4.9.2.63 TIEOFFREG70
4.9.2.64 TIEOFFREG71
4.9.2.65 TIEOFFREG72
4.9.2.66 TIEOFFREG73
4.9.2.67 TIEOFFREG74
4.9.2.68 TIEOFFREG75
4.9.2.69 TIEOFFREG76
4.9.2.70 TIEOFFREG77
4.9.2.71 TIEOFFREG78
4.9.2.72 TIEOFFREG79
4.9.2.73 TIEOFFREG80
4.9.2.74 TIEOFFREG81
4.9.2.75 TIEOFFREG82
4.9.2.76 TIEOFFREG83
4.9.2.77 TIEOFFREG84
4.9.2.78 TIEOFFREG85
4.9.2.79 TIEOFFREG86
4.9.2.80 TIEOFFREG87(Write)
4.9.2.81 TIEOFFREG87(Read)
4.9.2.82 TIEOFFREG88(Write)
4.9.2.83 TIEOFFREG88(Read)
4.9.2.84 TIEOFFREG89
4.9.2.85 TIEOFFREG90
4.9.2.86 TIEOFFREG91
4.9.2.87 TIEOFFREG92
4.9.2.88 TIEOFFREG93
4.9.2.89 TIEOFFREG94
4.9.2.90 TIEOFFREG95
4.9.2.91 TIEOFFREG96
4.9.2.92 TIEOFFREG97
4.9.2.93 TIEOFFREG98
4.9.2.94 TIEOFFREG99
4.9.2.95 TIEOFFREG100
4.9.2.96 TIEOFFREG101
4.9.2.97 TIEOFFREG102
4.9.2.98 TIEOFFREG103
4.9.2.99 TIEOFFREG104 (Write)
4.9.2.100 TIEOFFREG104 (Read)
4.9.2.101 TIEOFFREG105 (Read)
4.9.2.102 TIEOFFREG106
4.9.2.103 TIEOFFREG107
4.9.2.104 TIEOFFREG108
4.9.2.105 TIEOFFREG109
4.9.2.106 TIEOFFREG110
4.9.2.107 TIEOFFREG111
4.9.2.108 TIEOFFREG112
4.9.2.109 TIEOFFREG113
4.9.2.110 TIEOFFREG114
4.9.2.111 TIEOFFREG115
4.9.2.112 TIEOFFREG116
4.9.2.113 TIEOFFREG117
4.9.2.114 TIEOFFREG118
4.9.2.115 TIEOFFREG119
4.9.2.116 TIEOFFREG120
4.9.2.117 TIEOFFREG121
4.9.2.118 TIEOFFREG122
4.9.2.119 TIEOFFREG123
4.9.2.120 TIEOFFREG124
4.9.2.121 TIEOFFREG125
4.9.2.122 TIEOFFREG126
4.9.2.123 TIEOFFREG127
4.9.2.124 TIEOFFREG128
4.9.2.125 TIEOFFREG129
4.9.2.126 TIEOFFREG130
4.9.2.127 TIEOFFREG131
4.9.3 AXI BUS
4.9.3.1 Programmable Quality of Service (ProgQoS)
4.9.3.2 Arbitration Control
4.9.4 IP Reset
4.9.4.1 IP RESET REGISTER 0
4.9.4.2 IP RESET REGISTER 1
4.9.4.3 IP RESET REGISTER 2
5 Clock Generator
5.1 IP Clock Generator Overview
5.2 Clock Generator Level 0
5.2.1 Block Diagram
5.2.2 Register Description
5.2.2.1 Register Map Summary
5.2.2.1.1 CODA960CLKENB
5.2.2.1.2 CRYPTOCLKENB
5.2.2.1.3 I2CCLKENB
5.2.2.1.4 3D GPCLKENB
5.2.2.1.5 MPEGTSICLKENB
5.2.2.1.6 PDMCLKENB
5.2.2.1.7 SCALERCLKENB
5.2.2.1.8 DEINTERLACECLKENB
5.2.2.1.9 MLCCLKENB
5.3 Clock Generator Level 1
5.3.1 Block Diagram
5.3.2 Register Description
5.3.2.1 Register MAP Summary
5.3.2.1.1 MIPICSICLKENB
5.3.2.1.2 MIPICSICLKGEN0L
5.3.2.1.3 PPMCLKENB
5.3.2.1.4 PPMCLKGEN0L
5.3.2.1.5 PWMTIMERCLKENB
5.3.2.1.6 PWMTIMERCLKGEN0L
5.3.2.1.7 SDMMCCLKENB
5.3.2.1.8 SDMMCCLKGEN0L
5.3.2.1.9 SPDIFTXCLKENB
5.3.2.1.10 SPDIFTXCLKGEN0L
5.3.2.1.11 SSPCLKENB
5.3.2.1.12 SSPCLKEN0L
5.3.2.1.13 UARTCLKENB
5.3.2.1.14 UARTCLKGEN0L
5.3.2.1.15 VIPCLKENB
5.3.2.1.16 VIPCLKGEN0L
5.4 Clock Generator Level 2
5.4.1 Block Diagram
5.4.2 Register Description
5.4.2.1 Register Map Summary
5.4.2.1.1 GMACCLKENB
5.4.2.1.2 GMACCLKGEN0L
5.4.2.1.3 GMACCLKGEN1L
5.4.2.1.4 I2SCLKENB
5.4.2.1.5 I2SCLKGEN0L
5.4.2.1.6 I2SCLKGEN1L
5.4.2.1.7 USBHOSTOTGCLKENB
5.4.2.1.8 USBHOSTOTGCLKGEN0L
5.4.2.1.9 USBHOSTOTGCLKGEN1L
5.4.2.1.10 DPCCLKENB
5.4.2.1.11 DPCCLKGEN0L
5.4.2.1.12 DPCCLKGEN1L
5.4.2.1.13 LVDSCLKENB
5.4.2.1.14 LVDSCLKGEN0L
5.4.2.1.15 LVDSCLKGEN1L
5.4.2.1.16 HDMICLKENB
5.4.2.1.17 HDMICLKGEN0L
5.4.2.1.18 HDMICLKGEN1L
5.4.2.1.19 MIPIDSICLKENB
5.4.2.1.20 MIPIDSICLKGEN0L
5.4.2.1.21 MIPIDSICLKGEN1L
6 BUS
6.1 Overview
6.2 Features
6.3 Description
6.3.1 AXI BUS Description
6.3.2 Programmable Quality of Service (ProgQoS)
6.4 Register Description
6.4.1 Register Map Summary
6.4.1.1 AXI BUS
6.4.1.1.1 Address Map
6.4.1.1.2 QoS Tidemark Register
6.4.1.1.3 QoS Access Control Register
6.4.1.2 CCI BUS
6.4.1.2.1 Control Override
6.4.1.2.2 Speculation Control
6.4.1.2.3 Secure Access
6.4.1.2.4 Status
6.4.1.2.5 Imprecise Error
6.4.1.2.6 PMCR
6.4.1.2.7 PeripherallD4
6.4.1.2.8 PeripherallD5
6.4.1.2.9 PeripherallD6
6.4.1.2.10 PeripherallD7
6.4.1.2.11 PeripherallD0
6.4.1.2.12 PeripherallD1
6.4.1.2.13 PeripherallD2
6.4.1.2.14 PeripherallD3
6.4.1.2.15 ComponentlD0
6.4.1.2.16 ComponentlD1
6.4.1.2.17 ComponentlD2
6.4.1.2.18 ComponentlD3
6.4.1.2.19 Snoop Control Slave 0
6.4.1.2.20 Snoop Control Slave 1
6.4.1.2.21 Snoop Control Slave 2
6.4.1.2.22 Snoop Control Slave 3
6.4.1.2.23 Snoop Control Slave 4
6.4.1.2.24 Shareable Override Slave0
6.4.1.2.25 Shareable Override Slave1
6.4.1.2.26 Shareable Override Slave2
6.4.1.2.27 Shareable Override Slave3
6.4.1.2.28 Shareable Override Slave4
6.4.1.2.29 Read QoS Slave0
6.4.1.2.30 Read QoS Slave1
6.4.1.2.31 Read QoS Slave2
6.4.1.2.32 Read QoS Slave3
6.4.1.2.33 Read QoS Slave4
6.4.1.2.34 Write QoS Slave0
6.4.1.2.35 Write QoS Slave1
6.4.1.2.36 Write QoS Slave2
6.4.1.2.37 Write QoS Slave3
6.4.1.2.38 Write QoS Slave4
6.4.1.2.39 QoS Control Slave0
6.4.1.2.40 QoS Control Slave1
6.4.1.2.41 QoS Control Slave2
6.4.1.2.42 QoS Control Slave3
6.4.1.2.43 QoS Control Slave4
6.4.1.2.44 MaxOT Slave0
6.4.1.2.45 MaxOT Slave1
6.4.1.2.46 MaxOT Slave2
6.4.1.2.47 MaxOT Slave3
6.4.1.2.48 MaxOT Slave4
6.4.1.2.49 Regulator Target Slave0
6.4.1.2.50 Regulator Target Slave1
6.4.1.2.51 Regulator Target Slave2
6.4.1.2.52 Regulator Target Slave3
6.4.1.2.53 Regulator Target Slave4
6.4.1.2.54 Regulator Scale Slave0
6.4.1.2.55 Regulator Scale Slave1
6.4.1.2.56 Regulator Scale Slave2
6.4.1.2.57 Regulator Scale Slave3
6.4.1.2.58 Regulator Scale Slave4
6.4.1.2.59 Range Slave0
6.4.1.2.60 Range Slave1
6.4.1.2.61 Range Slave2
6.4.1.2.62 Range Slave3
6.4.1.2.63 Range Slave4
6.4.1.2.64 Cycle Counter
6.4.1.2.65 Counter Control
6.4.1.2.66 Overflow
6.4.1.2.67 Event Select Counter0
6.4.1.2.68 Event Select Counter1
6.4.1.2.69 Event Select Counter2
6.4.1.2.70 Event Select Counter3
6.4.1.2.71 PERF_EVENT Counter0
6.4.1.2.72 PERF_EVENT Counter1
6.4.1.2.73 PERF_EVENT Counter2
6.4.1.2.74 PERF_EVENT Counter3
6.4.1.2.75 PERF_CONTROL Counter0
6.4.1.2.76 PERF_CONTROL Counter1
6.4.1.2.77 PERF_CONTROL Counter2
6.4.1.2.78 PERF_CONTROL Counter3
6.4.1.2.79 PERF_OVERFLOW Counter0
6.4.1.2.80 PERF_OVERFLOW Counter1
6.4.1.2.81 PERF_OVERFLOW Counter2
6.4.1.2.82 PERF_OVERFLOW Counter3
7 TrustZone Protection Controller (TZPC)
7.1 Overview
7.2 Features
7.3 TZPC Configuration
7.3.1 TZPC0
7.3.2 TZPC1
7.3.3 TZPC2
7.3.4 TZPC3
7.3.5 TZPC4
7.3.6 TZPC5
7.3.7 TZPC6
7.4 Register Descriptions
7.4.1 Register Map Summary
7.4.1.1 TZPCR0SIZE
7.4.1.2 TZPCDECPROTnSTAT (n = 0 to 3)
7.4.1.3 TZPCDECPROnTSET (n = 0 to 3)
7.4.1.4 TZPCDECPROnTCLR (n = 0 to 3)
8 System L2 Cache (PL-310 L2C)
8.1 Overview
8.2 Features
8.3 Block Diagram
8.4 Functional Description
8.4.1 L2 Cache User Configure
8.4.2 Initialization Sequence
8.5 Register Description
8.5.1 Register Map Summary
8.5.1.1 REG0_CACHE_ID
8.5.1.2 REG0_CACHE_TYPE
8.5.1.3 REG1_CONTROL
8.5.1.4 AUX_CONTROL
8.5.1.5 REG1_TAG_RAM_CONTROL/REG1_DATA_RAM_CONTROL
8.5.1.6 REG2_EV_COUNTER_CTRL
8.5.1.7 REG2_EV_COUNTER1_CFG/REG2_EV_COUNTER0_CFG
8.5.1.8 REG2_EV_COUNTER1/ REG2_EV_COUNTER0
8.5.1.9 REG2_INT_MASK
8.5.1.10 REG2_INT_MASK_STATUS
8.5.1.11 REG2_INT_RAW_STATUS
8.5.1.12 REG2_INT_CLEAR
8.5.1.13 REG7_CACHE_SYNC
8.5.1.14 REG7_INV_PA
8.5.1.15 REG7_INV_WAY
8.5.1.16 REG7_CLEAN_PA
8.5.1.17 REG7_CLEAN_INDEX
8.5.1.18 REG7_CLEAN_WAY
8.5.1.19 REG7_CLEAN_INV_PA
8.5.1.20 REG7_CLEAN_INV_INDEX
8.5.1.21 REG7_CLEAN_INV_WAY
8.5.1.22 REG9_D_LOCKDOWNn (n = 0 to 7)
8.5.1.23 REG9_I_LOCKDOWNn (n = 0 to 7)
8.5.1.24 REG9_LOCK_LINE_EN
8.5.1.25 REG9_UNLOCK_WAY
8.5.1.26 REG12_ADDR_FILTERING_START
8.5.1.27 REG12_ADDR_FILTERING_END
8.5.1.28 REG15_DEBUG_CTRL
8.5.1.29 REG15_PREFETCH_CTRL
8.5.1.30 REG15_POWER_CTRL
9 DMA
9.1 Overview
9.2 Features
9.3 Block Diagram
9.4 Functional Description
9.4.1 Software Considerations
9.4.2 Programmer's Model
9.4.2.1 About the Programmer's Model
9.4.2.2 Programming the DMAC
9.4.2.3 Register Name Description
9.4.2.4 Peripheral DMA Request ID
9.4.2.5 Address Generation
9.4.2.6 Scatter/Gather
9.4.2.7 Interrupt Requests
9.4.2.8 DMAC Data Flow
9.5 Register Description
9.5.1 Register Map Summary
9.5.1.1 Interrupt Status Register
9.5.1.2 Interrupt Terminal Count Status Register
9.5.1.3 Interrupt Terminal Count Clear Register
9.5.1.4 Interrupt Error Status Register
9.5.1.5 Interrupt Error Clear Register
9.5.1.6 Raw Interrupt Terminal Count Status Register
9.5.1.7 Raw Error Interrupt Status Register
9.5.1.8 Enabled Channel Register
9.5.1.9 Software Burst Request Register
9.5.1.10 Software Single Request Register
9.5.1.11 Software Last Burst Request Register
9.5.1.12 Software Last Single Request Register
9.5.1.13 Configuration Register
9.5.1.14 Synchronization Register
9.5.1.15 Channel Source Address Registers (0 to 7)
9.5.1.16 Channel Destination Address Registers (0 to 7)
9.5.1.17 Channel Linked List Item Registers (0 to 7)
9.5.1.18 Channel Control Registers (0 to 7)
9.5.1.19 Channel Configuration Registers (0 to 7)
10 Interrupt Controller
10.1 Overview
10.2 Features
10.3 Security Extensions Support
10.4 Virtualization Support
10.5 Terminology
10.5.1 Interrupt States
10.5.2 Interrupt Type
10.5.3 Model for Handling Interrupt
10.5.4 Spurious Interrupts
10.5.5 Processor Security State and Secure and Non-Secure GIC Accesses
10.5.6 Banking
10.6 Functional Overview
10.6.1 Functional Interface
10.6.1.1 AMBA Slave Interface
10.6.1.2 Distributor
10.6.1.3 CPU Interface
10.6.1.4 Virtual Interface
10.6.2 The Distributor
10.6.2.1 Interrupt IDs
10.6.3 CPU Interfaces
10.7 Interrupt Handling and Prioritization
10.7.1 About Interrupt Handling and Prioritization
10.7.1.1 Handling Different Interrupt Types in a Multiprocessor System
10.7.1.2 Identifying the Supported Interrupt
10.7.2 General Handling of Interrupts
10.7.2.1 Priority Drop and Interrupt Deactivation
10.7.2.2 Interrupt Controls in the GIC
10.7.2.3 Implications of the 1-N Model
10.7.2.4 Interrupt Handling State Machine
10.7.2.5 Special Interrupt Numbers
10.8 Interrupt Source
10.9 Register Description
10.9.1 Register Map Summary
10.9.1.1 GICD_CTRL
10.9.1.2 GICD_TYPER
10.9.1.3 GICD_IIDR
10.9.1.4 GICD_IGROUPRn (n = 0 to 4)
10.9.1.5 GICD_ISENABLERn (n = 0 to 4)
10.9.1.6 GICD_ISCENABLERn (n = 0 to 4)
10.9.1.7 GICD_ISPENDRn (n = 0 to 4)
10.9.1.8 GICD_ICPENDERn (n = 0 to 4)
10.9.1.9 GICD_ISACTIVERn (n = 0 to 4)
10.9.1.10 GICD_ISCCTIVERn (n = 0 to 4)
10.9.1.11 GICD_IPRIORITYRn (n = 0 to 39)
10.9.1.12 GICD_ITARGETSRn (n = 0 to 39)
10.9.1.13 GICD_ICFGRn (n = 0 to 9)
10.9.1.14 GICD_PPISR
10.9.1.15 GICD_SPISRn (n = 0 to 3)
10.9.1.16 GICD_SGIR
10.9.1.17 GICD_CPENDSGIRn (n = 0 to 3)
10.9.1.18 GICD_SPENDSGIRn (n = 0 to 3)
10.9.1.19 GICC_CTRL
10.9.1.20 GICC_PMR
10.9.1.21 GICC_BPR
10.9.1.22 GICC_IAR
10.9.1.23 GICC_EOIR
10.9.1.24 GICC_RPR
10.9.1.25 GICC_HPPIR
10.9.1.26 GICC_ABPR
10.9.1.27 GICC_AIAR
10.9.1.28 GICC_AEOIR
10.9.1.29 GICC_AHIPPIR
10.9.1.30 GICC_APR0
10.9.1.31 GICC_NSAPR0
10.9.1.32 GICC_DIR
11 Watch Dog Timer
11.1 Overview
11.2 Features
11.3 Functional Description
11.3.1 Watchdog Timer Operation
11.3.2 WTDAT & WTCNT
11.3.3 Consideration of Debugging Environment
11.3.4 Special Function Register
11.3.4.1 Memory map
11.3.4.2 Watchdog Timer Control (WTCON) Register
11.3.4.3 Watchdog Timer Data (WTDAT) Register
11.3.4.4 Watchdog Timer Count (WTCNT) Register
11.3.4.5 Watchdog Timer Interrupt (WTCLRINT) Register
11.4 Register Description
11.4.1 Register Map Summary
11.4.1.1 WTCON
11.4.1.2 WTDAT
11.4.1.3 WTCNT
11.4.1.4 WTCLRINT
12 RTC
12.1 Overview
12.2 Features
12.3 Block Diagram
12.4 Functional Description
12.4.1 Backup Battery Operation
12.4.2 RTC Operation
12.4.3 Accessing the RTC Time Counter Setting/Read Register
12.4.4 Interrupt Pending Register
12.4.5 Power Manager Reset Time Control
12.5 Register Description
12.5.1 Register Map Summary
12.5.1.1 RTCCNTWRITE
12.5.1.2 RTCCNTREAD
12.5.1.3 RTCALARM
12.5.1.4 RTCCTRL
12.5.1.5 RTCINTENB
12.5.1.6 RTCINTPND
12.5.1.7 RTCCORERSTIMESEL
12.5.1.8 WTCON
13 Alive
13.1 Overview
13.2 Features
13.3 Power Isolation
13.3.1 Core Power Off
13.3.2 Power Gating
13.4 Alive Registers
13.4.1 Alive GPIO Detect Registers
13.4.2 Scratch Register
13.4.3 Alive GPIO Control Registers
13.5 Momentary Power Control
13.5.1 CoreVDD Powering On
13.5.2 CoreVDD Powering Off
13.6 SLEEP Mode
13.7 PMU (Power management Unit)
13.7.1 Overview
13.7.2 Power Mode Table
13.7.3 Power Switch Control Sequence
13.8 Register Description
13.8.1 Register Map Summary
13.8.1.1 ALIVEPWRGATEREG
13.8.1.2 ALIVEGPIOASYNCDETECTMODERSTREG0
13.8.1.3 ALIVEGPIOASYNCDETECTMODERSTREG1
13.8.1.4 ALIVEGPIOASYNCDETECTMODESETREG0
13.8.1.5 ALIVEGPIOASYNCDETECTMODESETREG1
13.8.1.6 ALIVEGPIOLOWASYNCDETECTMODEREADREG
13.8.1.7 ALIVEGPIOHIGHASYNCDETECTMODEREADREG
13.8.1.8 ALIVEGPIODETECTMODERSTREG0
13.8.1.9 ALIVEGPIODETECTMODERSTREG1
13.8.1.10 ALIVEGPIODETECTMODERSTREG2
13.8.1.11 ALIVEGPIODETECTMODERSTREG3
13.8.1.12 ALIVEGPIODETECTMODESETREG0
13.8.1.13 ALIVEGPIODETECTMODESETREG1
13.8.1.14 ALIVEGPIODETECTMODESETREG2
13.8.1.15 ALIVEGPIODETECTMODESETREG3
13.8.1.16 ALIVEGPIOFALLDETECTMODEREADREG
13.8.1.17 ALIVEGPIORISEDETECTMODEREADREG
13.8.1.18 ALIVEGPIOLOWDETECTMODEREADREG
13.8.1.19 ALIVEGPIOHIGHDETECTMODEREADREG
13.8.1.20 ALIVEGPIODETECTENBRSTREG
13.8.1.21 ALIVEGPIODETECTENBSETREG
13.8.1.22 ALIVEGPIODETECTENBREADREG
13.8.1.23 ALIVEGPIOINTENBRSTREG
13.8.1.24 ALIVEGPIODETECTENABLESETREG
13.8.1.25 ALIVEGPIOINTENBREADREG
13.8.1.26 ALIVEGPIODETECTPENDREG
13.8.1.27 ALIVESCRATCHRSTREG
13.8.1.28 ALIVESCRATCHSETREG
13.8.1.29 ALIVESCRATCHREADREG
13.8.1.30 ALIVEGPIOPADOUTENBRSTREG
13.8.1.31 ALIVEGPIOPADOUTENBSETREG
13.8.1.32 ALIVEGPIOPADOUTENBREADREG
13.8.1.33 ALIVEGPIOPADPULLUPRSTREG
13.8.1.34 ALIVEGPIOPADPULLUPSETREG
13.8.1.35 ALIVEGPIOPADPULLUPREADREG
13.8.1.36 ALIVEGPIOPADOUTRSTREG
13.8.1.37 ALIVEGPIOPADOUTSETREG
13.8.1.38 ALIVEGPIOPADOUTREADREG
13.8.1.39 VDDCTRLRSTREG
13.8.1.40 VDDCTRLSETREG
13.8.1.41 VDDCTRLREADREG
13.8.1.42 ALIVECLEARWAKEUPSTATUSREGISTER
13.8.1.43 ALIVESLEEPWAKEUPSTATUSREGISTER
13.8.1.44 ALIVESCRATCHRSTREG1
13.8.1.45 ALIVESCRATCHRSTREG2
13.8.1.46 ALIVESCRATCHRSTREG3
13.8.1.47 ALIVESCRATCHRSTREG4
13.8.1.48 ALIVESCRATCHRSTREG5
13.8.1.49 ALIVESCRATCHRSTREG6
13.8.1.50 ALIVESCRATCHRSTREG7
13.8.1.51 ALIVESCRATCHRSTREG8
13.8.1.52 ALIVESCRATCHSETREG1
13.8.1.53 ALIVESCRATCHSETREG2
13.8.1.54 ALIVESCRATCHSETREG3
13.8.1.55 ALIVESCRATCHSETREG4
13.8.1.56 ALIVESCRATCHSETREG5
13.8.1.57 ALIVESCRATCHSETREG6
13.8.1.58 ALIVESCRATCHSETREG7
13.8.1.59 ALIVESCRATCHSETREG8
13.8.1.60 ALIVESCRATCHREADREG1
13.8.1.61 ALIVESCRATCHREADREG2
13.8.1.62 ALIVESCRATCHREADREG3
13.8.1.63 ALIVESCRATCHREADREG4
13.8.1.64 ALIVESCRATCHREADREG5
13.8.1.65 ALIVESCRATCHREADREG6
13.8.1.66 ALIVESCRATCHREADREG7
13.8.1.67 ALIVESCRATCHREADREG8
13.8.1.68 VDDOFFDELAYRSTREGISTER
13.8.1.69 VDDOFFDELAYSETREGISTER
13.8.1.70 VDDOFFDELAYVALUEREGISTER
13.8.1.71 VDDOFFDELAYTIMEREGISTER
13.8.1.72 ALIVEGPIOINPUTVALUE
13.8.1.73 PMUNISOLATE
13.8.1.74 PMUNPWRUPPRE
13.8.1.75 PMUNPWRUP
13.8.1.76 PMUNPWRUPACK
14 ID Register
14.1 Overview
14.2 Features
14.3 Functional Description
14.3.1 AC Timing
14.3.2 Sense Mode Timing
14.3.3 Scan-Latch Mode Timing
14.3.4 Stand-by Mode Timing
14.3.5 Program Mode Timing
14.4 Register Description
14.4.1 Register Map Summary
14.4.1.1 ECID0
14.4.1.2 ECID1
14.4.1.3 ECID2
14.4.1.4 ECID3
14.4.1.5 CHIP_NAME_03_00
14.4.1.6 CHIP_NAME_07_04
14.4.1.7 CHIP_NAME_11_08
14.4.1.8 CHIP_NAME_15_12
14.4.1.9 CHIP_NAME_19_16
14.4.1.10 CHIP_NAME_23_20
14.4.1.11 CHIP_NAME_27_24
14.4.1.12 CHIP_NAME_31_28
14.4.1.13 CHIP_NAME_35_32
14.4.1.14 CHIP_NAME_39_36
14.4.1.15 CHIP_NAME_43_40
14.4.1.16 CHIP_NAME_47_44
14.4.1.17 GUID0
14.4.1.18 GUID1_2
14.4.1.19 GUID3_0
14.4.1.20 GUID3_1
14.4.1.21 EC0
14.4.1.22 EC1
14.4.1.23 EC2
14.5 Application Notes
15 Memory Controller
15.1 Overview
15.1.1 Unified Memory Architecture (UMA)
15.2 Block Diagram
15.3 Functional Description
15.3.1 MCU-A Bank Feature
15.3.2 MCU-S Bank Feature
15.3.3 Memory Map
15.3.4 MCU-A Address Mapping
15.3.4.1 Split Column Interleaved Mapping
15.3.4.2 Randomized Interleaved Mapping
15.3.4.3 Rank Interleaved Mapping
15.3.5 Low Power Operation
15.3.5.1 AXI Low Power Channel
15.3.5.2 Dynamic Power Down
15.3.5.3 Dynamic Self Refresh
15.3.5.4 Clock Stop
15.3.5.5 Direct Command
15.3.6 Precharge Policy
15.3.6.1 Post Selective Precharge
15.3.6.2 Timeout Precharge
15.3.7 Quality of Service
15.3.7.1 BRB Arbitration
15.3.7.2 AxQoS Base QoS
15.3.7.3 BRB Space Reservation
15.3.7.4 Emergency Priority Escalation
15.3.8 Trust Zone Address Space Control (TZASC)
15.3.8.1 Regions
15.3.8.2 Denied AXI Transactions
15.3.8.3 Preventing Writes to Registers and Using SECURE_BOOT_LOCK
15.3.8.4 Using Exclusive Access
15.3.9 MCU-A Application Note
15.3.9.1 DREX Initialization
15.3.9.2 DDR-PHY Initialization
15.3.9.2.1 Write Leveling
15.3.9.2.2 CA Calibration
15.3.9.2.3 Gate Leveling
15.3.9.2.4 Read DQ Calibration (= Read Leveling, Read Deskewing)
15.3.9.2.5 Write Latency Calibration
15.3.9.2.6 Write DQ Calibration (= Write Deskewing)
15.3.9.3 Low Frequency Operation
15.3.9.4 Offset Control
15.3.9.5 DLL Lock Procedure
15.3.9.6 ZQ I/O Control Procedure
15.3.10 MCU-S
15.3.10.1 Static Memory Map Shadow
15.3.10.2 Interface
15.3.11 NAND Overview
15.3.11.1 Normal Access Sequence
15.3.11.2 ECC (BCH)
15.4 Register Description
15.4.1 Register Map Summary
15.4.1.1 DREX
15.4.1.1.1 CONCONTROL
15.4.1.1.2 MEMCONTROL
15.4.1.1.3 CGCONTROL
15.4.1.1.4 DIRECTCMD
15.4.1.1.5 PRECHCONFIG0
15.4.1.1.6 PHYCONTROL0
15.4.1.1.7 PRECHCONFIG1
15.4.1.1.8 TIMINGRFCBP
15.4.1.1.9 PWRDNCONFIG
15.4.1.1.10 TIMINGPZQ
15.4.1.1.11 TIMINGAREF
15.4.1.1.12 TIMINGROW
15.4.1.1.13 TIMINGDATA
15.4.1.1.14 TIMINGPOWERn
15.4.1.1.15 PHYSTATUS
15.4.1.1.16 ETCTIMING
15.4.1.1.17 CHIPSTATUS
15.4.1.1.18 MRSTATUS
15.4.1.1.19 QOSCONTROL n (n = 0 to 15)
15.4.1.1.20 TIMINGSETSW
15.4.1.1.21 WRTRACONFIG
15.4.1.1.22 RDLVLCONFIG
15.4.1.1.23 BRBRSVCONTROL
15.4.1.1.24 BRBRSVCONFIG
15.4.1.1.25 BRBQOSCONFIG
15.4.1.1.26 WRLVLCONFIG0
15.4.1.1.27 WRLVLCONFIG1
15.4.1.1.28 WRLVLSTATUS
15.4.1.1.29 CTRL_IO_RDATA
15.4.1.1.30 CACAL_CONFIG0
15.4.1.1.31 CACAL_CONFIG1
15.4.1.1.32 CACAL_STATUS
15.4.1.1.33 EMERGENT_CONFIG0
15.4.1.1.34 EMERGENT_CONFIG1
15.4.1.1.35 BP_CONTROLn (Back Pressure control Register for Port n)
15.4.1.1.36 BP_CONFIGRn (Back Pressure Configuration Register for Read Port n)
15.4.1.1.37 BP_CONFIGWn (Back Pressure Configuration Register for Write Port n)
15.4.1.2 TZASC Configuration
15.4.1.2.1 TZCONFIG
15.4.1.2.2 TZACTION
15.4.1.2.3 TZLDRANGE
15.4.1.2.4 TZLDSELECT
15.4.1.2.5 TZINTSTATUS
15.4.1.2.6 TZINTCLEAR
15.4.1.2.7 TZFAILADDRLOWRn
15.4.1.2.8 TZFAILADDRHIGHRn
15.4.1.2.9 TZFAILCTRLRn
15.4.1.2.10 TZFAILIDRn
15.4.1.2.11 TZFAILADDRLOWWn
15.4.1.2.12 TZFAILCTRLWn
15.4.1.2.13 TZFAILADDRHIGHWn
15.4.1.2.14 TZFAILIDW n
15.4.1.2.15 TZRSLOW n
15.4.1.2.16 TZRSHIGH n
15.4.1.2.17 TZRSATTR n
15.4.1.2.18 TZITCRG
15.4.1.2.19 TZITIP
15.4.1.2.20 TZITOP
15.4.1.2.21 MEMBASECONFIG 0
15.4.1.2.22 MEMBASECONFIG 1
15.4.1.2.23 MEMCONFIG 0
15.4.1.2.24 MEMCONFIG 1
15.4.1.3 DDRPHY
15.4.1.3.1 PHY_CON0
15.4.1.3.2 PHY_CON1
15.4.1.3.3 PHY_CON2
15.4.1.3.4 PHY_CON3
15.4.1.3.5 PHY_CON4
15.4.1.3.6 PHY_CON5
15.4.1.3.7 LP_CON0
15.4.1.3.8 RODT_CON0
15.4.1.3.9 OFFSETR_CON0
15.4.1.3.10 OFFSETR_CON1
15.4.1.3.11 OFFSETR_CON2
15.4.1.3.12 OFFSETW_CON0
15.4.1.3.13 OFFSETW_CON1
15.4.1.3.14 OFFSETW_CON2
15.4.1.3.15 OFFSETC_CON0
15.4.1.3.16 OFFSETC_CON1
15.4.1.3.17 OFFSETC_CON2
15.4.1.3.18 SHIFTC_CON0
15.4.1.3.19 OFFSETD_CON0
15.4.1.3.20 LP_DDR_CON0
15.4.1.3.21 LP_DDR_CON1
15.4.1.3.22 LP_DDR_CON2
15.4.1.3.23 LP_DDR_CON3
15.4.1.3.24 LP_DDR_CON4
15.4.1.3.25 WR_LVL_CON0
15.4.1.3.26 WR_LVL_CON1
15.4.1.3.27 WR_LVL_CON2
15.4.1.3.28 WR_LVL_CON3
15.4.1.3.29 CA_DSKEW_CON0
15.4.1.3.30 CA_DSKEW_CON1
15.4.1.3.31 CA_DSKEW_CON2
15.4.1.3.32 CA_DSKEW_CON3
15.4.1.3.33 CA_DSKEW_CON4
15.4.1.3.34 DRVDS_CON0
15.4.1.3.35 DRVDS_CON1
15.4.1.3.36 MDLL_CON0
15.4.1.3.37 MDLL_CON1
15.4.1.3.38 ZQ_CON0
15.4.1.3.39 ZQ_CON1
15.4.1.3.40 ZQ_CON2
15.4.1.3.41 ZQ_CON3
15.4.1.3.42 T_RDDATA_CON0
15.4.1.3.43 T_RDDATA_CON1
15.4.1.3.44 T_RDDATA_CON2
15.4.1.3.45 CAL_WL_STAT
15.4.1.3.46 CAL_FAIL_STAT0
15.4.1.3.47 CAL_FAIL_STAT1
15.4.1.3.48 CAL_FAIL_STAT2
15.4.1.3.49 CAL_FAIL_STAT3
15.4.1.3.50 CAL_GT_VWMC0
15.4.1.3.51 CAL_GT_VWMC1
15.4.1.3.52 CAL_GT_VWMC2
15.4.1.3.53 CAL_GT_CYC
15.4.1.3.54 CAL_RD_VWMC0
15.4.1.3.55 CAL_RD_VWMC1
15.4.1.3.56 CAL_RD_VWMC2
15.4.1.3.57 CAL_RD_VWML0
15.4.1.3.58 CAL_RD_VWML1
15.4.1.3.59 CAL_RD_VWML2
15.4.1.3.60 CAL_RD_VWMR0
15.4.1.3.61 CAL_RD_VWMR1
15.4.1.3.62 CAL_RD_VWMR2
15.4.1.3.63 CAL_WR_VWMC0
15.4.1.3.64 CAL_WR_VWMC1
15.4.1.3.65 CAL_WR_VWMC2
15.4.1.3.66 CAL_WR_VWML0
15.4.1.3.67 CAL_WR_VWML1
15.4.1.3.68 CAL_WR_VWML2
15.4.1.3.69 CAL_WR_VWMR0
15.4.1.3.70 CAL_WR_VWMR1
15.4.1.3.71 CAL_WR_VWMR2
15.4.1.3.72 CAL_DM_VWMR0
15.4.1.3.73 CAL_DM_VWMR1
15.4.1.3.74 CAL_DM_VWMR2
15.4.1.3.75 CAL_DM_VWML0
15.4.1.3.76 CAL_DM_VWML1
15.4.1.3.77 CAL_DM_VWML2
15.4.1.3.78 CAL_DM_VWMR0
15.4.1.3.79 CAL_DM_VWMR1
15.4.1.3.80 CAL_DM_VWMR2
15.4.1.4 MCU-S
15.4.1.4.1 MEMBW
15.4.1.4.2 MEMTIMEACSL
15.4.1.4.3 MEMTIMEACSH
15.4.1.4.4 MEMTIMECOSL
15.4.1.4.5 MEMTIMECOSH
15.4.1.4.6 MEMTIMEACC0
15.4.1.4.7 MEMTIMEACC1
15.4.1.4.8 MEMTIMEACC2
15.4.1.4.9 MEMTIMEACC3
15.4.1.4.10 MEMTIMESACC0
15.4.1.4.11 MEMTIMESACC1
15.4.1.4.12 MEMTIMESACC2
15.4.1.4.13 MEMTIMESACC3
15.4.1.4.14 MEMTIMECOHL
15.4.1.4.15 MEMTIMECOHH
15.4.1.4.16 MEMTIMECAHL
15.4.1.4.17 MEMTIMECAHH
15.4.1.4.18 MEMBURSTL
15.4.1.4.19 MEMWAIT
15.4.1.4.20 NFCONTROL
15.4.1.4.21 NFECCTRL
15.4.1.4.22 NFCNT
15.4.1.4.23 NFECCSTATUS
15.4.1.4.24 NFTIMEACS
15.4.1.4.25 NFTIMECOS
15.4.1.4.26 NFTIMEACC0
15.4.1.4.27 NFTIMEOCH
15.4.1.4.28 NFTIMECAH
15.4.1.4.29 NFECCn (n = 0 to 26)
15.4.1.4.30 NFORGECCn (n = 0 to 26)
15.4.1.4.31 NFSYNDROMEn (n = 0 to 29)
15.4.1.4.32 NFELPn (n = 0 to 29)
15.4.1.4.33 NFERRORLOCATIONn (n = 0 to 59)
15.4.1.4.34 AUTO SYNDROME REGISTER (AUTOSYND)
15.4.1.4.35 NFWSYNDRONEn (n = 0 to 29)
15.4.1.5 MCUS_ADDR
15.4.1.5.1 NFDATA
15.4.1.5.2 NFCMD
15.4.1.5.3 NFADDR
16 GPIO Controller
16.1 Overview
16.2 Features
16.3 Block Diagram
16.4 Functional Description
16.4.1 Input Operation
16.4.2 Output Operation
16.4.3 Alternate Function Operation
16.5 Register Description
16.5.1 Register Map Summary
16.5.1.1 GPIOxOUT
16.5.1.2 GPIOxOUTENB
16.5.1.3 GPIOxDETMODE0
16.5.1.4 GPIOxDETMODE1
16.5.1.5 GPIOxINTENB
16.5.1.6 GPIOxDET
16.5.1.7 GPIOxPAD
16.5.1.8 GPIOxALTFN0
16.5.1.9 GPIOxALTFN1
16.5.1.10 GPIOxDETMODEEX
16.5.1.11 GPIOxDETENB
16.5.1.12 GPIOx_SLEW
16.5.1.13 GPIOx_SLEW_DISABLE_DEFAULT
16.5.1.14 GPIOx_DRV1
16.5.1.15 GPIOx_DRV1_DISABLE_DEFAULT
16.5.1.16 GPIOx_DRV0
16.5.1.17 GPIOx_DRV0_DISABLE_DEFAULT
16.5.1.18 GPIOx_PULLSEL
16.5.1.19 GPIOx_PULLSEL_DISABLE_DEFAULT
16.5.1.20 GPIOx_PULLENB
16.5.1.21 GPIOx_PULLENB_DISABLE_DEFAULT
17 Ethernet MAC
17.1 Overview
17.2 Features
17.2.1 MAC Core Features
17.2.2 DMA Block Features
17.3 Block Diagram
17.4 Register Description
17.4.1 Register Map Summary
17.4.1.1 MAC DMA
17.4.1.1.1 Ethernet MAC DMA Register 0
17.4.1.1.2 Ethernet MAC DMA Register 1
17.4.1.1.3 Ethernet MAC DMA Register 2
17.4.1.1.4 Ethernet MAC DMA Register 3
17.4.1.1.5 Ethernet MAC DMA Register 4
17.4.1.1.6 Ethernet MAC DMA Register 5
17.4.1.1.7 Ethernet MAC DMA Register 6
17.4.1.1.8 Ethernet MAC DMA Register 7
17.4.1.1.9 Ethernet MAC DMA Register 8
17.4.1.1.10 Ethernet MAC DMA Register 18
17.4.1.1.11 Ethernet MAC DMA Register 19
17.4.1.1.12 Ethernet MAC DMA Register 20
17.4.1.1.13 Ethernet MAC DMA Register 21
17.4.1.2 MAC Core
17.4.1.2.1 Ethernet MAC Register 0
17.4.1.2.2 Ethernet MAC Register 1
17.4.1.2.3 Ethernet MAC Register 2
17.4.1.2.4 Ethernet MAC Register 3
17.4.1.2.5 Ethernet MAC Register 4
17.4.1.2.6 Ethernet MAC Register 5
17.4.1.2.7 Ethernet MAC Register 6
17.4.1.2.8 Ethernet MAC Register 7
17.4.1.2.9 Ethernet MAC Register 8
17.4.1.2.10 Ethernet MAC Register 9
17.4.1.2.11 Ethernet MAC Register 14
17.4.1.2.12 Ethernet MAC Register 15
17.4.1.2.13 Ethernet MAC Register 16
17.4.1.2.14 Ethernet MAC Register 17
17.4.1.2.15 Ethernet MAC Register 18
17.4.1.2.16 Ethernet MAC Register 19
17.4.1.2.17 Ethernet MAC Register 20 to 47
17.4.1.2.18 Ethernet MAC Register 48
17.4.1.2.19 Ethernet MAC Register 49
17.4.1.2.20 Ethernet MAC Register 50
17.4.1.2.21 Ethernet MAC Register 51
17.4.1.2.22 Ethernet MAC Register 52
17.4.1.2.23 Ethernet MAC Register 53
17.4.1.2.24 Ethernet MAC Register 54
17.4.1.2.25 Ethernet MAC Register 448
17.4.1.2.26 Ethernet MAC Register 449
17.4.1.2.27 Ethernet MAC Register 450
17.4.1.2.28 Ethernet MAC Register 451
17.4.1.2.29 Ethernet MAC Register 452
17.4.1.2.30 Ethernet MAC Register 453
17.4.1.2.31 Ethernet MAC Register 454
17.4.1.2.32 Ethernet MAC Register 455
17.4.1.2.33 Ethernet MAC Register 456
17.4.1.2.34 Ethernet MAC Register 457
17.4.1.2.35 Ethernet MAC Register 458
17.4.1.2.36 Ethernet MAC Register 512 to 543
18 SD/MMC Controller
18.1 Overview
18.2 Features
18.2.1 Features of Mobile Storage Host
18.3 Block Diagram
18.3.1 Clock Phase Shifter
18.4 Register Description
18.4.1 Register Map Summary
18.4.1.1 CTRL
18.4.1.2 POWER_ENABLE
18.4.1.3 CLKDIV
18.4.1.4 CLK_SOURCE
18.4.1.5 CLKENA
18.4.1.6 TMOUT
18.4.1.7 CTYPE
18.4.1.8 BLKSIZ
18.4.1.9 BYTCNT
18.4.1.10 INTMASK
18.4.1.11 CMDARG
18.4.1.12 CMD
18.4.1.13 RESP0
18.4.1.14 RESP1
18.4.1.15 RESP2
18.4.1.16 RESP3
18.4.1.17 MINTSTS
18.4.1.18 RINTSTS
18.4.1.19 STATUS
18.4.1.20 FIFOTH
18.4.1.21 CDETECT
18.4.1.22 WRTPRT
18.4.1.23 TCBCNT
18.4.1.24 TBBCNT
18.4.1.25 DEBNCE
18.4.1.26 USRID
18.4.1.27 VERID
18.4.1.28 UHS_REG
18.4.1.29 RST_n
18.4.1.30 BMODE
18.4.1.31 PLDMND
18.4.1.32 DBADDR
18.4.1.33 IDSTS
18.4.1.34 IDINTEN
18.4.1.35 DSCADDR
18.4.1.36 BUFADDR
18.4.1.37 CARDTHRCTL
18.4.1.38 BACK_END_POWER
18.4.1.39 EMMC_DDR_REG
18.4.1.40 EMMC_DDR_REG
18.4.1.41 Data
19 Pulse Period Measurement (PPM)
19.1 Overview
19.2 Features
19.3 Block Diagram
19.4 Functional Description
19.4.1 IR Remote Protocol Example
19.4.2 Timing
19.4.3 Flowchart
19.5 Register Description
19.5.1 Register Map Summary
19.5.1.1 PPMCTRL
19.5.1.2 PPMSTATUS
19.5.1.3 PPMLOWPERIOD
19.5.1.4 PPMHIGHPERIOD
20 Pulse Width Modulation (PWM) Timer
20.1 Overview
20.2 Features
20.3 PWM Operation
20.3.1 Prescaler & Divider
20.3.2 Basic Timer Operation
20.3.3 Auto-Reload and Double Buffering
20.3.4 Timer Operation
20.3.5 Initialize Timer (Setting Manual-Up Data and Inverter)
20.3.6 Dead Zone Generator
20.4 Register Description
20.4.1 Register Map Summary
20.4.1.1 TCFG0
20.4.1.2 TCFG1
20.4.1.3 TCON
20.4.1.4 TCNTB0
20.4.1.5 TCMPB0
20.4.1.6 TCNTO0
20.4.1.7 TCNTB1
20.4.1.8 TCMPB1
20.4.1.9 TCNTO1
20.4.1.10 TCNTB2
20.4.1.11 TCMPB2
20.4.1.12 TCNTO2
20.4.1.13 TCNTB3
20.4.1.14 TCMPB3
20.4.1.15 TCNTO3
20.4.1.16 TCNTB4
20.4.1.17 TCNTO4
20.4.1.18 TINT_CSTAT
21 Analog Digital Converter (ADC)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Functional Description
21.4.1 I/O Chart
21.4.2 Timing Diagram
21.4.3 Analog Input Selection Table
21.4.4 Flowchart
21.5 Register Description
21.5.1 Register Map Summary
21.5.1.1 ADCCON
21.5.1.2 ADCDAT
21.5.1.3 ADCINTENB
21.5.1.4 ADCINTCLR
21.5.1.5 PRESCALERCON
22 I2C Controller
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Functional Description
22.4.1 The Concept of the I2C-Bus
22.4.2 IC Protocol
22.4.3 Start/Stop Operation
22.4.4 Data Transfer Format
22.4.5 ACK Signal Transmission
22.4.6 Read-Write Operation
22.4.7 Bus Arbitration Procedures
22.4.8 Abort Conditions
22.4.9 Configuring IIC-BUS
22.5 Programming Guide
22.5.1 Flowcharts of Operations in Each Mode
22.6 Register Description
22.6.1 Register Map Summary
22.6.1.1 I2CCON
22.6.1.2 I2CSTAT
22.6.1.3 I2CADD
22.6.1.4 I2CDS
22.6.1.5 I2CLC
22.6.1.6 I2CVR
23 SPI/SSP
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Functional Description
23.4.1 Clock/Reset Configuration
23.4.1.1 Reset Configuration
23.4.1.2 Clock Configuration
23.4.2 Operation of Serial Peripheral Interface
23.4.3 FIFO Access
23.4.4 Trailing Byte Interrupt
23.4.5 Packet Number Control
23.4.6 Chip Select Control
23.4.7 High Speed Operation as Slave
23.4.8 Feedback Clock Selection
23.4.9 SPI Transfer Format
23.5 Register Description
23.5.1 Register Map Summary
23.5.1.1 SPI/SSP CONFIGURE
23.5.1.2 SPI/SSP FIFO CON
23.5.1.3 SPI/SSP SEL SIGNAL CON
23.5.1.4 SPI/SSP INT EN
23.5.1.5 SPI/SSP STATUS
23.5.1.6 SPI/SSP TX DATA
23.5.1.7 SPI/SSP RX DATA
23.5.1.8 SPI/SSP PACKET COUNT
23.5.1.9 SPI/SSP STATUS PENDING CLEAR
23.5.1.10 SPI/SSP SWAP CONFIGURE
23.5.1.11 SPI/SSP FEEDBACK CLOCK SEL
24 MPEG-TS Interface
24.1 Overview
24.2 Features
24.3 Functional Description
24.3.1 Timing
24.4 Register Description
24.4.1 Register Map Summary
24.4.1.1 CAP_CTRL0
24.4.1.2 CAP_CTRL1
24.4.1.3 CAP_WR_PID_VAL
24.4.1.4 CAP_WR_PID_ADDR
24.4.1.5 CAP0_CAPDATA
24.4.1.6 CAP1_CAPDATA
24.4.1.7 CORE_TRDATA
24.4.1.8 CORE_CTRL
24.4.1.9 IDMA_STATUS
24.4.1.10 IDMA_CON
24.4.1.11 IDMA_INT
24.4.1.12 IDMA0_ADDR
24.4.1.13 IDMA1_ADDR
24.4.1.14 IDMA2_ADDR
24.4.1.15 IDMA3_ADDR
24.4.1.16 IDMA0_LEN
24.4.1.17 IDMA1_LEN
24.4.1.18 IDMA2_LEN
24.4.1.19 IDMA3_LEN
24.5 PID Filter Data Structure
25 UART_ISO7816
25.1 Overview
25.2 Features
25.3 UART Description
25.3.1 Data Transmission
25.3.2 Data Reception
25.3.3 Auto Flow Control (AFC)
25.3.4 Non Auto-Flow Control (Controlling nRTS and nCTS by Software)
25.3.4.1 Rx Operation with FIFO
25.3.4.2 Tx Operation with FIFO
25.3.5 Interrupt/DMA Request Generation
25.3.6 UART Error Status FIFO
25.3.6.1 Infra-Red Mode
25.3.7 UART Baud Rate
25.3.7.1 UART Baud Rate Configuration
25.3.7.2 Baud Rate Error Tolerance
25.3.7.3 UART Clock and PCLK Relation
25.3.8 ISO-7816
25.4 Register Description
25.4.1 Register Map Summary
25.4.1.1 ULCONn
25.4.1.2 UCONn
25.4.1.3 UFCONn
25.4.1.4 UMCONn
25.4.1.5 UTRSTATn
25.4.1.6 UERSTATn
25.4.1.7 UFSTATn
25.4.1.8 UMSTATn
25.4.1.9 UTXHn
25.4.1.10 URXHn
25.4.1.11 UBRDIVn
25.4.1.12 UFRACVALn
25.4.1.13 UINTPn
25.4.1.14 UINTSn
25.4.1.15 UINTMn
26 USB2.0 OTG
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 I/O Pin Description
26.5 Functional Description
26.5.1 End Point Packet Size
26.5.2 USB 5V Power Detection
26.5.3 Force Power Down
26.5.4 External Charge Pump
26.5.5 Modes of Operation
26.5.5.1 DMA Mode
26.5.5.2 Slave Mode
26.6 Programming User Configure of PHY and OTG LINK
26.7 Register Description
26.7.1 Register Map Summary
26.7.1.1 Core Global Register
26.7.1.1.1 GOTGCTL
26.7.1.1.2 GOTGINT
26.7.1.1.3 GAHBCFG
26.7.1.1.4 GUSBCFG
26.7.1.1.5 GRSTCTL
26.7.1.1.6 GINTSTS
26.7.1.1.7 GINTMSK
26.7.1.1.8 GRXSTSR (Host Mode)
26.7.1.1.9 GRXSTSP (Device Mode)
26.7.1.1.10 GRXFSIZ
26.7.1.1.11 GNPTXFSIZ
26.7.1.1.12 GNPTXSTS
26.7.1.1.13 HPTXFSIZ
26.7.1.1.14 DPTXFSIZn (n = 1 to 15)
26.7.1.2 Host Mode Register
26.7.1.2.1 HCFG
26.7.1.2.2 HFIR
26.7.1.2.3 HFNUM
26.7.1.2.4 HPTXSTS
26.7.1.2.5 HAINT
26.7.1.2.6 HAINTMSK
26.7.1.2.7 HPRT
26.7.1.2.8 HCCHARn (n= 0 to 15)
26.7.1.2.9 HCSPLTn (n= 0 to 15)
26.7.1.2.10 HCINTn (n= 0 to 15)
26.7.1.2.11 HCINTMSKn (n= 0 to 15)
26.7.1.2.12 HCTSIZn (n= 0 to 15)
26.7.1.2.13 HCDMAn (n= 0 to 15)
26.7.1.3 Device Mode Register
26.7.1.3.1 USB_OTG_DMCSR
26.7.1.3.2 DCTL
26.7.1.3.3 DSTS
26.7.1.3.4 DIEPMSK
26.7.1.3.5 DOEPMSK
26.7.1.3.6 DAINT
26.7.1.3.7 DAINTMSK
26.7.1.3.8 DTKNQR1
26.7.1.3.9 DTKNQR2
26.7.1.3.10 DVBUSDIS
26.7.1.3.11 DVBUSPULSE
26.7.1.3.12 DTKNQR3
26.7.1.3.13 DTKNQR4
26.7.1.3.14 DIEPCTL0
26.7.1.3.15 DIEPINT0
26.7.1.3.16 DIEPTSIZ0
26.7.1.3.17 DIEPDMA0
26.7.1.3.18 DIEPCTLn (n = 1 to 7)
26.7.1.3.19 DIEPINTn (n = 1 to 7)
26.7.1.3.20 DIEPTSIZn (n = 1 to 7)
26.7.1.3.21 DIEPDMAn (n = 1 to 7)
26.7.1.3.22 DOEPCTL0
26.7.1.3.23 DOEPINT0
26.7.1.3.24 DOEPTSIZ0
26.7.1.3.25 DOEPDMA0
26.7.1.3.26 DOEPCTLn (n = 1 to 7)
26.7.1.3.27 DOEPINTn (n = 1 to 7)
26.7.1.3.28 DOEPTSIZn (n = 1 to 7)
26.7.1.3.29 DOEPDMAn (n = 1 to 7)
26.7.1.4 Power and Clock Gating Register
26.7.1.4.1 PCGCCTL
26.7.1.5 Device EP n/Host Channel n FIFO Register
26.7.1.5.1 USBOTG_EPFIFOn (n = 0 to 15)
27 USB2.0 HOST
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Functional Description
27.4.1 Programming User Configure of PHY and LINK in EHCI or OHCI
27.4.2 Programming User Configure of PHY and LINK in HSIC
27.4.3 Attention Point of HSIC Programming
27.5 Register Description
27.5.1 Register Map Summary
27.5.1.1 HCCAPBASE
27.5.1.2 HCSPARAMS
27.5.1.3 HCCPARAMS
27.5.1.4 USBCMD
27.5.1.5 USBSTS
27.5.1.6 USBINTR
27.5.1.7 FRINDEX
27.5.1.8 CTRLDSSEGMEN
27.5.1.9 PERIODICLISTBASE
27.5.1.10 ASYNCLISTADDR
27.5.1.11 CONFIGFLAG
27.5.1.12 PORTSC_1 to 15
27.5.1.13 INSNREG00
27.5.1.14 INSNREG01
27.5.1.15 INSNREG02
27.5.1.16 INSNREG03
27.5.1.17 INSNREG04
27.5.1.18 INSNREG05
27.5.1.19 INSNREG06
27.5.1.20 INSNREG07
27.5.1.21 INSNREG08
28 I2S
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Functional Description
28.4.1 Master/Slave Mode
28.4.2 DMA Transfer
28.4.3 Audio Serial Data Format
28.4.3.1 IIS-Bus Format
28.4.3.2 MSB (Left) Justified
28.4.3.3 LSB (Right) Justified
28.4.3.4 Sampling Frequency and Master Clock
28.4.4 PCM Word Length and BFS Driver
28.4.5 DFS Divider and RFS Divider
28.4.6 RFS Divider and ROOT Clock
28.5 Programming Guide
28.5.1 Initialization
28.5.2 Play Mode (TX Mode) with DMA
28.5.3 Recording Mode (Rx Mode) with DMA
28.5.4 Example Code
28.5.4.1 Tx Channel
28.5.4.2 Rx Channel
28.6 Register Description
28.6.1 Register Map Summary
28.6.1.1 IISCON
28.6.1.2 IISMOD
28.6.1.3 IISFIC
28.6.1.4 I2STXD
28.6.1.5 I2SRXD
29 AC97
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Functional Description
29.4.1 Internal Data Path
29.4.2 Operation Flow Chart
29.4.3 AC-link Digital Interface Protocol
29.4.3.1 AC-Link Output Frame (SDATA_OUT)
29.4.3.2 AC-Link Input Frame (SDATA_IN)
29.4.4 AC97 Power-Down
29.4.4.1 Powering Down the AC-Link
29.4.4.2 Waking Up the AC-Link - Wake Up Triggered by the AC97 Controller
29.4.4.3 Cold AC97 Reset
29.4.4.4 Warm AC97 Reset
29.4.4.5 AC97 State Diagram
29.5 Register Description
29.5.1 Register Map Summary
29.5.1.1 AC_GLBCTRL
29.5.1.2 AC_GLBSTAT
29.5.1.3 AC_CODEC_CMD
29.5.1.4 AC_CODEC_STAT
29.5.1.5 AC_PCMADDR
29.5.1.6 AC_MICADDR
29.5.1.7 AC_PCMDATA
29.5.1.8 AC_MICDATA
30 SPDIF TX
30.1 Overview
30.2 Features
30.3 Block Diagram
30.4 Functional Description
30.4.1 Data Format of SPDIF
30.4.2 Frame Format
30.4.3 Sub-frame Format (IEC 60958)
30.5 Channel Coding
30.6 Preamble
30.7 Non-Linear PCM Encoded Source (IEC 61937)
30.8 SPDIF Operation
30.9 Shadowed Register
30.10 Register Description
30.10.1 Register Map Summary
30.10.1.1 SPDCLKCON
30.10.1.2 SPDCON
30.10.1.3 SPDBSTAS
30.10.1.4 SPDCSTAS
30.10.1.5 SPDDAT
30.10.1.6 SPDCNT
30.10.1.7 SPDBSTAS_SHD
30.10.1.8 SPDCNT_SHD
30.10.1.9 USERBIT1
30.10.1.10 USERBIT2
30.10.1.11 USERBIT3
30.10.1.12 USERBIT1_SHD
30.10.1.13 USERBIT2_SHD
30.10.1.14 USERBIT3_SHD
30.10.1.15 VERSION_INFO
31 SPDIF RX
31.1 Overview
31.2 Features
31.3 Block Diagram
31.4 Functional Description
31.5 Register Description
31.5.1 Register Map Summary
31.5.1.1 SPDIF_CTRL
31.5.1.2 SPDIF_ENBIRQ
31.5.1.3 REGUSERA0
31.5.1.4 REGUSERA1
31.5.1.5 REGUSERA2
31.5.1.6 REGUSERA3
31.5.1.7 REGUSERA4
31.5.1.8 REGUSERA5
31.5.1.9 REGUSERB0
31.5.1.10 REGUSERB1
31.5.1.11 REGUSERB2
31.5.1.12 REGUSERB3
31.5.1.13 REGUSERB4
31.5.1.14 REGUSERB5
31.5.1.15 REGSTATA0
31.5.1.16 REGSTATA1
31.5.1.17 REGSTATA2
31.5.1.18 REGSTATA3
31.5.1.19 REGSTATA4
31.5.1.20 REGSTATA5
31.5.1.21 REGSTATB0
31.5.1.22 REGSTATB1
31.5.1.23 REGSTATB2
31.5.1.24 REGSTATB3
31.5.1.25 REGSTATB4
31.5.1.26 REGSTATB5
32 PDM
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 PDM Application Note
32.4.1 Butterworth Filter Configuration
32.5 Register Description
32.5.1 Register Map Summary
32.5.1.1 PDM_CTRL
32.5.1.2 PDM_GAIN0
32.5.1.3 PDM_GAIN1
32.5.1.4 PDM_COEFF
32.5.1.5 PDM_DATA
32.5.1.6 PDM_CTRL1
32.5.1.7 PDM_IRQCTRLl
33 Display Architecture
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 TFT/MPU Interface
33.5 Register Description
33.5.1 Register Map Summary
33.5.1.1 HDMI_MUXCTRL
33.5.1.2 LVDS_MUXCTRL
33.5.1.3 HDMI_SYNCCTRL0
33.5.1.4 HDMI_SYNCCTRL1
33.5.1.5 HDMI_SYNCCTRL2
33.5.1.6 HDMI_SYNCCTRL3
33.5.1.7 TFT_MUXCTRL
34 Multi Layer Controller (MLC)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Dual Register Set Architecture
34.5 MLC Global Parameters
34.5.1 Screen Size
34.5.2 Priority
34.5.3 Field Mode
34.5.4 Background Color
34.5.5 Per-layer Parameters
34.5.6 Enable
34.5.7 Lock Control
34.5.8 Position
34.5.9 Pixel Format
34.5.9.1 RGB Layer Format
34.5.9.2 Video Layer Format
34.5.9.3 Layer Blending
34.5.10 Address Generation
34.5.10.1 RGB Layer Address Generation
34.5.10.2 Video Layer Address Generation
34.5.11 Video Layer Specific Parameters
34.5.12 Scale Function
34.5.12.1 Color Control
34.5.12.2 Luminance Enhancement
34.5.12.3 Chrominance Enhancement
34.5.13 Gamma Correction
34.6 Clock Generation
34.7 Register Description
34.7.1 Register Map Summary
34.7.1.1 MLCCONTROLT
34.7.1.2 MLCSCREENSIZE
34.7.1.3 MLCBGCOLOR
34.7.1.4 MLCLEFTRIGHT0
34.7.1.5 MLCTOPBOTTOM0
34.7.1.6 MLCLEFTRIGHT0_0
34.7.1.7 MLCTOPBOTTOM0_0
34.7.1.8 MLCLEFTRIGHT0_1
34.7.1.9 MLCTOPBOTTOM0_1
34.7.1.10 MLCCONTROL0
34.7.1.11 MLCHSTRIDE0
34.7.1.12 MLCVSTRIDE0
34.7.1.13 MLCTPCOLOR0
34.7.1.14 MLCINVCOLOR0
34.7.1.15 MLCADDRESS0
34.7.1.16 MLCLEFTright1
34.7.1.17 MLCtopBOTTOM1
34.7.1.18 MLCLEFTRIGHT1_0
34.7.1.19 MLCTOPBOTTOM1_0
34.7.1.20 MLCLEFTRIGHT1_1
34.7.1.21 MLCTOPBOTTOM1_1
34.7.1.22 MLCCONTROL1
34.7.1.23 MLCHSTRIDE1
34.7.1.24 MLCVSTRIDE1
34.7.1.25 MLCTPCOLOR1
34.7.1.26 MLCINVCOLOR1
34.7.1.27 MLCADDRESS1
34.7.1.28 MLCLEFright2
34.7.1.29 MLCtopBOTTOM2
34.7.1.30 MLCCONTROL2
34.7.1.31 MLCVSTRIDE3
34.7.1.32 MLCTPCOLOR3
34.7.1.33 MLCADDRESS3
34.7.1.34 MLCADDRESSCB
34.7.1.35 MLCADDRESSCR
34.7.1.36 MLCVSTRIDECB
34.7.1.37 MLCVSTRIDECR
34.7.1.38 MLCHScALE
34.7.1.39 MLCVSCALE
34.7.1.40 MLCLUENH
34.7.1.41 MLCCHENH0
34.7.1.42 MLCCHENH1
34.7.1.43 MLCCHENH2
34.7.1.44 MLCCHENH3
34.7.1.45 MLCGAMMACONT
34.7.1.46 MLCRGAMMATABLEWRITE
34.7.1.47 MLCGGAMMATABLEWRITE
34.7.1.48 MLCBGAMMATABLEWRITE
34.7.1.49 MLCCLKENB
35 Display Controller (DPC)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Sync Generator
35.4.1 Clock Generation
35.4.1.1 Peripheral Clock Generation
35.4.1.2 Video Clock Generation
35.4.2 Format
35.4.2.1 RGB Format
35.4.2.2 YCbCr Format
35.4.3 Sync Signals
35.4.3.1 Horizontal Timing Interface
35.4.3.2 Vertical Timing Interface
35.4.3.3 AC Timing
35.4.3.4 UPSCALER (Only Secondary Display)
35.4.3.5 Embedded Sync
35.4.4 Scan Mode
35.4.5 Delay
35.4.6 Interrupt
35.4.7 MPU (i80) Type Sync Signals
35.4.8 Odd/Even Field Flag
35.4.9 Internal Video encoder and DAC
35.4.9.1 Features
35.4.9.2 General Description
35.4.9.3 Video Encoder Reset Sequence
35.4.9.4 Block Diagram
35.4.9.5 Timing Interface
35.4.9.6 Video Standard Selection
35.4.9.7 Basic Video Adjustments
35.4.9.8 Programmable Bandwidth
35.4.9.9 Analog Video Output Configuration
35.5 Register Description
35.5.1 Register Map Summary
35.5.1.1 DPCHTOTAL
35.5.1.2 DPCHSWIDTH
35.5.1.3 DPCHASTART
35.5.1.4 DPCHAEND
35.5.1.5 DPCVTOTAL
35.5.1.6 DPCVSWIDTH
35.5.1.7 DPCVASTART
35.5.1.8 DPCVAEND
35.5.1.9 DPCCTRL0
35.5.1.10 DPCCTRL1
35.5.1.11 DPCEVTOTAL
35.5.1.12 DPCEVSWIDTH
35.5.1.13 DPCEVASTART
35.5.1.14 DPCEVAEND
35.5.1.15 DPCCTRL2
35.5.1.16 DPCVSEOFFSET
35.5.1.17 DPCVSSOFFSET
35.5.1.18 DPCEVSEOFFSET
35.5.1.19 DPCEVSSOFFSET
35.5.1.20 DPCDELAY0
35.5.1.21 DPUPSCALECON0
35.5.1.22 DPUPSCALECON1
35.5.1.23 DPCDELAY1
35.5.1.24 DPCMPUTIME0
35.5.1.25 DPCMPUTIME1
35.5.1.26 DPCMPUWRDATAL
35.5.1.27 DPCMPUINDEX
35.5.1.28 DPCMPUSTATUS
35.5.1.29 DPCMPUDATAH
35.5.1.30 DPCMPURDATAL
35.5.1.31 DPCCMDBUFFERRDATAL
35.5.1.32 DPCCMDBUFFERRDATAH
35.5.1.33 DPCMPUTIME1
35.5.1.34 DPCPADPOSITION0
35.5.1.35 DPCPADPOSITION1
35.5.1.36 DPCPADPOSITION2
35.5.1.37 DPCPADPOSITION3
35.5.1.38 DPCPADPOSITION4
35.5.1.39 DPCPADPOSITION5
35.5.1.40 DPCPADPOSITION6
35.5.1.41 DPCPADPOSITION7
35.5.1.42 DPCRGBMASK0
35.5.1.43 DPCRGBMASK1
35.5.1.44 DPCRGBSHIFT
35.5.1.45 DPCDATAFLUSH
35.5.1.46 DPCCLKENB
35.5.1.47 DPCCLKGEN0L
35.5.1.48 DPCCLKGEN0H
35.5.1.49 DPCCLKGEN1L
35.5.1.50 DPCCLKGEN1H
36 De-Interlace
36.1 Overview
36.2 Features
36.3 Operation
36.3.1 Even Operation
36.3.2 Odd Operation
36.3.3 Y, Cb, Cr Operation
36.3.4 De-Interlace Operation Flow
36.4 Register Description
36.4.1 Register Map Summary
36.4.1.1 CONTROL
36.4.1.2 CONFIG
36.4.1.3 INTENB
36.4.1.4 INTPEN
36.4.1.5 TSPARA
36.4.1.6 TMPARA
36.4.1.7 TIPARA
36.4.1.8 TPARA
36.4.1.9 BLENDPARA
36.4.1.10 SRCSIZE_Y
36.4.1.11 SRCADDRP_Y
36.4.1.12 SRCADDRC_Y
36.4.1.13 SRCADDRN_Y
36.4.1.14 SRCSTRD_Y
36.4.1.15 DESTADDRF_Y
36.4.1.16 DESTADDRD_Y
36.4.1.17 DESTSTRD_Y
36.4.1.18 SRCSIZE_CB
36.4.1.19 SRCADDRC_CB
36.4.1.20 SRCSTRD_CB
36.4.1.21 DESTADDRF_CB
36.4.1.22 DESTADDRD_CB
36.4.1.23 DESTSTRD_CB
36.4.1.24 SRCSIZE_CR
36.4.1.25 SRCADDRC_CR
36.4.1.26 SRCSTRD_CR
36.4.1.27 DESTSTRD_CR
37 Scaler
37.1 Overview
37.2 Features
37.3 Block Diagram
37.4 Functional Description
37.4.1 Digital Filter Characteristics
37.4.1.1 Horizontal Filter (5-Tab FIR Filter) Frequency Response and Group Delay
37.4.1.2 Vertical Filter (3-Tab FIR Filter) Frequency Response and Group Delay
37.5 Programming Guide
37.5.1 Configuration
37.5.2 RUN
37.6 Register Description
37.6.1 Register Map Summary
37.6.1.1 SCRUNREG
37.6.1.2 SCCFGREG
37.6.1.3 SCINTREG
37.6.1.4 SCSRCADDRREG
37.6.1.5 SCSRCADDRREG
37.6.1.6 SCSRCSIZEREG
37.6.1.7 SCDESTADDR0
37.6.1.8 SCDESTSTREDE0
37.6.1.9 SCDESTADDR1
37.6.1.10 SCDESTADDR1
37.6.1.11 SCDESTSIZE
37.6.1.12 DELTAXREG
37.6.1.13 DELTAYREG
37.6.1.14 HVSOFTREG
37.6.1.15 CMDBUFADDR
37.6.1.16 CMDBUFCON
37.6.1.17 YVFILTER[N]_00_03
37.6.1.18 YVFILTER[N]_04_07
37.6.1.19 YVFILTER[N]_08_11
37.6.1.20 YVFILTER[N]_12_15
37.6.1.21 YVFILTER[N]_16_19
37.6.1.22 YVFILTER[N]_20_23
37.6.1.23 YVFILTER[N]_24_27
37.6.1.24 YVFILTER[N]_28_31
37.6.1.25 YHFILTER[N]_00_01
37.6.1.26 YHFILTER[N]_02_03
37.6.1.27 YHFILTER[N]_04_05
37.6.1.28 YHFILTER[N]_06_07
37.6.1.29 YHFILTER[N]_08_09
37.6.1.30 YHFILTER[N]_10_11
37.6.1.31 YHFILTER[N]_12_13
37.6.1.32 YHFILTER[N]_14_15
37.6.1.33 YHFILTER[N]_16_17
37.6.1.34 YHFILTER[N]_18_19
37.6.1.35 YHFILTER[N]_20_21
37.6.1.36 YHFILTER[N]_22_23
37.6.1.37 YHFILTER[N]_24_25
37.6.1.38 YHFILTER[N]_26_27
37.6.1.39 YHFILTER[N]_28_29
37.6.1.40 YHFILTER[N]_30_31
38 LVDS
38.1 Overview
38.2 Features
38.3 Block Diagram
38.4 Functional Description
38.4.1 LVDS Data Packing Format
38.4.2 LVDS Application Note
38.4.3 Skew Control between Output Data and Clock
38.4.4 Electrical Characteristics
38.5 Register Description
38.5.1 Register Map Summary
38.5.1.1 LVDSCTRL0
38.5.1.2 LVDSCTRL1
38.5.1.3 LVDSCTRL2
38.5.1.4 LVDSCTRL3
38.5.1.5 LVDSCTRL4
38.5.1.6 LVDSLOC0
38.5.1.7 LVDSLOC1
38.5.1.8 LVDSLOC2
38.5.1.9 LVDSLOC3
38.5.1.10 LVDSLOC4
38.5.1.11 LVDSLOC5
38.5.1.12 LVDSLOC6
38.5.1.13 LVDSLOCMASK0
38.5.1.14 LVDSLOCMASK1
38.5.1.15 LVDSLOCPOL0
38.5.1.16 LVDSLOCPOL1
38.5.1.17 LVDSTMODE0
38.5.1.18 LVDSTMODE1
38.5.2 DisplayTop Register
38.5.2.1 LVDS_MUXCTRL
39 HDMI
39.1 Overview
39.2 Features
39.3 Block Diagram
39.4 Functional Description
39.4.1 Select RGB Video data for HDMI
39.4.2 HDMI Converter
39.4.3 HDMI LINK
39.4.3.1 Video Input Interface
39.4.3.2 Audio Input Interface
39.4.3.3 HPD
39.4.3.4 CEC
39.4.3.5 Interrupt Timing
39.4.3.6 HDCP KEY Management
39.4.3.7 HDMI Interlace Mode
39.5 Register Description
39.5.1 Register Map Summary
39.5.1.1 Control
39.5.1.1.1 INTC_CON_0
39.5.1.1.2 INTC_FLAG_0
39.5.1.1.3 AESKEY_VALID
39.5.1.1.4 HPD
39.5.1.1.5 INTC_CON_1
39.5.1.1.6 INTC_FLAG_1
39.5.1.1.7 PHY_STATUS_0
39.5.1.1.8 PHY_STATUS_CMU
39.5.1.1.9 PHY_STATUS_PLL
39.5.1.1.10 PHY_CON_0
39.5.1.1.11 HPD_CTRL
39.5.1.1.12 HPD_STATUS
39.5.1.1.13 HPD_TH_x
39.5.1.2 Core
39.5.1.2.1 HDMI_CON_0
39.5.1.2.2 HDMI_CON_1
39.5.1.2.3 HDMI_CON_2
39.5.1.2.4 STATUS
39.5.1.2.5 STATUS_EN
39.5.1.2.6 MODE_SEL
39.5.1.2.7 ENC_EN
39.5.1.2.8 HDMI_YMAX
39.5.1.2.9 HDMI_YMIN
39.5.1.2.10 HDMI_CMAX
39.5.1.2.11 HDMI_CMIN
39.5.1.2.12 H_BLANK_0
39.5.1.2.13 H_BLANK_1
39.5.1.2.14 V2_BLANK_0
39.5.1.2.15 V2_BLANK_1
39.5.1.2.16 V1_BLANK_0
39.5.1.2.17 V1_BLANK_1
39.5.1.2.18 V_LINE_0
39.5.1.2.19 V_LINE_1
39.5.1.2.20 H_LINE_0
39.5.1.2.21 H_LINE_1
39.5.1.2.22 HSYNC_POL
39.5.1.2.23 VSYNC_POL
39.5.1.2.24 INT_PRO_MODE
39.5.1.2.25 V_BLANK_F0_0
39.5.1.2.26 V_BLANK_F0_1
39.5.1.2.27 V_BLANK_F1_0
39.5.1.2.28 V_BLANK_F1_1
39.5.1.2.29 H_SYNC_START_0
39.5.1.2.30 H_SYNC_START_1
39.5.1.2.31 H_SYNC_END_0
39.5.1.2.32 H_SYNC_END_1
39.5.1.2.33 V_SYNC_LINE_BEF_2_0
39.5.1.2.34 V_SYNC_LINE_BEF_2_1
39.5.1.2.35 V_SYNC_LINE_BEF_1_0
39.5.1.2.36 V_SYNC_LINE_BEF_1_1
39.5.1.2.37 V_SYNC_LINE_AFT_2_0
39.5.1.2.38 V_SYNC_LINE_AFT_2_1
39.5.1.2.39 V_SYNC_LINE_AFT_1_0
39.5.1.2.40 V_SYNC_LINE_AFT_1_1
39.5.1.2.41 V_SYNC_LINE_AFT_PXL_2_0
39.5.1.2.42 V_SYNC_LINE_AFT_PXL_2_1
39.5.1.2.43 V_SYNC_LINE_AFT_PXL_1_0
39.5.1.2.44 V_SYNC_LINE_AFT_PXL_1_1
39.5.1.2.45 V_BLANK_F2_0
39.5.1.2.46 V_BLANK_F2_1
39.5.1.2.47 V_BLANK_F3_0
39.5.1.2.48 V_BLANK_F3_1
39.5.1.2.49 V_BLANK_F4_0
39.5.1.2.50 V_BLANK_F4_1
39.5.1.2.51 V_BLANK_F5_0
39.5.1.2.52 V_BLANK_F5_1
39.5.1.2.53 V_SYNC_LINE_AFT_3_0
39.5.1.2.54 V_SYNC_LINE_AFT_3_1
39.5.1.2.55 V_SYNC_LINE_AFT_4_0
39.5.1.2.56 V_SYNC_LINE_AFT_4_1
39.5.1.2.57 V_SYNC_LINE_AFT_5_0
39.5.1.2.58 V_SYNC_LINE_AFT_5_1
39.5.1.2.59 V_SYNC_LINE_AFT_6_0
39.5.1.2.60 V_SYNC_LINE_AFT_6_1
39.5.1.2.61 V_SYNC_LINE_AFT_PXL_3_0
39.5.1.2.62 V_SYNC_LINE_AFT_PXL_3_1
39.5.1.2.63 V_SYNC_LINE_AFT_PXL_4_0
39.5.1.2.64 V_SYNC_LINE_AFT_PXL_4_1
39.5.1.2.65 V_SYNC_LINE_AFT_PXL_5_0
39.5.1.2.66 V_SYNC_LINE_AFT_PXL_5_1
39.5.1.2.67 V_SYNC_LINE_AFT_PXL_6_0
39.5.1.2.68 V_SYNC_LINE_AFT_PXL_6_1
39.5.1.2.69 VACT_SPACE1_0
39.5.1.2.70 VACT_SPACE1_1
39.5.1.2.71 VACT_SPACE2_0
39.5.1.2.72 VACT_SPACE2_1
39.5.1.2.73 VACT_SPACE3_0
39.5.1.2.74 VACT_SPACE3_1
39.5.1.2.75 VACT_SPACE4_0
39.5.1.2.76 VACT_SPACE4_1
39.5.1.2.77 VACT_SPACE5_0
39.5.1.2.78 VACT_SPACE5_1
39.5.1.2.79 VACT_SPACE6_0
39.5.1.2.80 VACT_SPACE6_1
39.5.1.2.81 GCP_CON
39.5.1.2.82 GCP_BYTE1
39.5.1.2.83 GCP_BYTE2
39.5.1.2.84 GCP_BYTE3
39.5.1.2.85 ASP_CON
39.5.1.2.86 ASP_SP_FLAT
39.5.1.2.87 ASP_CHCFG0
39.5.1.2.88 ASP_CHCFG1
39.5.1.2.89 ASP_CHCFG2
39.5.1.2.90 ASP_CHCFG3
39.5.1.2.91 ACR_CON
39.5.1.2.92 ACR_MCTS0
39.5.1.2.93 ACR_MCTS1
39.5.1.2.94 ACR_MCTS2
39.5.1.2.95 ACR_N0
39.5.1.2.96 ACR_N1
39.5.1.2.97 ACR_N2
39.5.1.2.98 ACP_CON
39.5.1.2.99 ACP_TYPE
39.5.1.2.100 ACP_DATAx
39.5.1.2.101 ISRC_CON
39.5.1.2.102 ISRC1_HEADER1
39.5.1.2.103 ISRC1_DATAx
39.5.1.2.104 ISRC2_DATAx
39.5.1.2.105 AVI_CON
39.5.1.2.106 AVI_HEADER0
39.5.1.2.107 AVI_HEADER1
39.5.1.2.108 AVI_HEADER2
39.5.1.2.109 AVI_CHECK_SUM
39.5.1.2.110 AVI_BYTEx
39.5.1.2.111 AUI_CON
39.5.1.2.112 AUI_HEADER0
39.5.1.2.113 AUI_HEADER1
39.5.1.2.114 AUI_HEADER2
39.5.1.2.115 AUI_CHECK_SUM
39.5.1.2.116 AUI_BYTEx
39.5.1.2.117 MPG_CON
39.5.1.2.118 MPG_CHECK_SUM
39.5.1.2.119 MPG_DATAx
39.5.1.2.120 SPD_CON
39.5.1.2.121 SPD_HEADER0
39.5.1.2.122 SPD_HEADER1
39.5.1.2.123 SPD_HEADER2
39.5.1.2.124 SPD_DATAx
39.5.1.2.125 GAMUT_CON
39.5.1.2.126 GAMUT_HEADER0
39.5.1.2.127 GAMUT_HEADER1
39.5.1.2.128 GAMUT_HEADER2
39.5.1.2.129 GAMUT_METADATAx
39.5.1.2.130 VSI_CON
39.5.1.2.131 VSI_HEADER0
39.5.1.2.132 VSI_HEADER1
39.5.1.2.133 VSI_HEADER2
39.5.1.2.134 VSI_DATAx
39.5.1.2.135 DC_CONTROL
39.5.1.2.136 VIDEO_PATTERN_GEN
39.5.1.2.137 AN_SEED_SEL
39.5.1.2.138 AN_SEED_0
39.5.1.2.139 AN_SEED_1
39.5.1.2.140 An_Seed_2
39.5.1.2.141 An_Seed_3
39.5.1.2.142 HDCP_SHA1_x
39.5.1.2.143 HDCP_KSV_LIST_x
39.5.1.2.144 HDCP_KSV_LIST_CON
39.5.1.2.145 HDCP_SHA_RESULT
39.5.1.2.146 HDCP_CTRL1
39.5.1.2.147 HDCP_CTRL2
39.5.1.2.148 HDCP_CHECK_RESULT
39.5.1.2.149 HDCP_BKSV_x
39.5.1.2.150 HDCP_AKSV_x
39.5.1.2.151 HDCP_AN_x
39.5.1.2.152 HDCP_BCAPS
39.5.1.2.153 HDCP_BSTATUS_0
39.5.1.2.154 HDCP_BSTATUS_1
39.5.1.2.155 HDCP_RI_0
39.5.1.2.156 HDCP_Ri_1
39.5.1.2.157 HDCP_I2C_INT
39.5.1.2.158 HDCP_AN_INT
39.5.1.2.159 HDCP_WATCGDOG_INT
39.5.1.2.160 HDCP_RI_INT
39.5.1.2.161 HDCP_RI_COMPARE_0
39.5.1.2.162 HDCP_RI_COMPARE_1
39.5.1.2.163 HDCP_FRAME_COUNT
39.5.1.2.164 RGB_ROUND_EN
39.5.1.2.165 VACT_SPACE_R_0
39.5.1.2.166 VACT_SPACE_R_1
39.5.1.2.167 VACT_SPACE_G_0
39.5.1.2.168 VACT_SPACE_G_1
39.5.1.2.169 VACT_SPACE_B_0
39.5.1.2.170 VACT_SPACE_B_1
39.5.1.2.171 BLUE_SCREEN_R_0
39.5.1.2.172 BLUE_SCREEN_R_1
39.5.1.2.173 BLUE_SCREEN_G_0
39.5.1.2.174 BLUE_SCREEN_G_1
39.5.1.2.175 BLUE_SCREEN_B_0
39.5.1.2.176 BLUE_SCREEN_B_1
39.5.1.3 ASE
39.5.1.3.1 AES_START
39.5.1.3.2 AES_DATA_SIZE_L
39.5.1.3.3 AES_DATA_SIZE_H
39.5.1.3.4 AES_DATA
39.5.1.4 SPDIF
39.5.1.4.1 SPDIFIN_CLK_CTRL
39.5.1.4.2 SPDIFIN_OP_CTRL
39.5.1.4.3 SPDIFIN_IRQ_MASK
39.5.1.4.4 SPDIFIN_IRQ_STATUS
39.5.1.4.5 SPDIFIN_CONFIG_1
39.5.1.4.6 SPDIFIN_CONFIG_2
39.5.1.4.7 _USER_VALUE_1
39.5.1.4.8 SPDIFIN_USER_VALUE_2
39.5.1.4.9 SPDIFIN_USER_VALUE_3
39.5.1.4.10 SPDIFIN_USER_VALUE_4
39.5.1.4.11 SPDIFIN_CH_STATUS_0_1
39.5.1.4.12 SPDIFIN_CH_STATUS_0_2
39.5.1.4.13 SPDIFIN_CH_STATUS_0_3
39.5.1.4.14 SPDIFIN_CH_STATUS_0_4
39.5.1.4.15 SPDIFIN_CH_STATUS_1
39.5.1.4.16 SPDIFIN_FRAME_PERIOD_1
39.5.1.4.17 SPDIFIN_FRAME_PERIOD_2
39.5.1.4.18 SPDIFIN_Pc_INFO_1
39.5.1.4.19 SPDIFIN_Pc_INFO_2
39.5.1.4.20 SPDIFIN_Pd_INFO_1
39.5.1.4.21 SPDIFIN_Pd_INFO_2
39.5.1.4.22 SPDIFIN_DATA_BUF_0_1
39.5.1.4.23 SPDIFIN_DATA_BUF_0_2
39.5.1.4.24 SPDIFIN_DATA_BUF_0_3
39.5.1.4.25 SPDIFIN_USER_BUF_0
39.5.1.4.26 SPDIFIN_DATA_BUF_1_1
39.5.1.4.27 SPDIFIN_DATA_BUF_1_2
39.5.1.4.28 SPDIFIN_DATA_BUF_1_3
39.5.1.4.29 SPDIFIN_USER_BUF_1
39.5.1.5 I2S
39.5.1.5.1 I2S_CLK_CON
39.5.1.5.2 I2S_CON_1
39.5.1.5.3 I2S_CON_2
39.5.1.5.4 I2S_PIN_SEL_0
39.5.1.5.5 I2S_PIN_SEL_1
39.5.1.5.6 I2S_PIN_SEL_2
39.5.1.5.7 I2S_PIN_SEL_3
39.5.1.5.8 I2S_DSD_CON
39.5.1.5.9 I2S_MUX_CON
39.5.1.5.10 I2S_CH_ST_CON
39.5.1.5.11 I2S_CH_ST_0
39.5.1.5.12 I2S_CH_ST_1
39.5.1.5.13 I2S_CH_ST_2
39.5.1.5.14 I2S_CH_ST_3
39.5.1.5.15 I2S_CH_ST_4
39.5.1.5.16 I2S_CH_ST_SH_0
39.5.1.5.17 I2S_CH_ST_SH_1
39.5.1.5.18 I2S_CH_ST_SH_2
39.5.1.5.19 I2S_CH_ST_SH_3
39.5.1.5.20 I2S_CH_ST_SH_4
39.5.1.5.21 I2S_VD_DATA
39.5.1.5.22 I2S_MUX_CH
39.5.1.5.23 I2S_MUX_CUV
39.5.1.5.24 I2S_CH0_L_0
39.5.1.5.25 I2S_CH0_L_1
39.5.1.5.26 I2S_CH0_L_2
39.5.1.5.27 I2S_CH0_R_0
39.5.1.5.28 I2S_CH0_R_1
39.5.1.5.29 I2S_CH0_R_2
39.5.1.5.30 I2S_CH0_R_3
39.5.1.5.31 I2S_CH1_L_0
39.5.1.5.32 I2S_CH1_L_1
39.5.1.5.33 I2S_CH1_L_2
39.5.1.5.34 I2S_CH1_L_3
39.5.1.5.35 I2S_CH1_R_0
39.5.1.5.36 I2S_CH1_R_1
39.5.1.5.37 I2S_CH1_R_2
39.5.1.5.38 I2S_CH1_R_3
39.5.1.5.39 I2S_CH2_L_0
39.5.1.5.40 I2S_CH2_L_1
39.5.1.5.41 I2S_CH2_L_2
39.5.1.5.42 I2S_CH2_L_3
39.5.1.5.43 I2S_CH2_R_0
39.5.1.5.44 I2S_CH2_R_1
39.5.1.5.45 I2S_CH2_R_2
39.5.1.5.46 I2S_Ch2_R_3
39.5.1.5.47 I2S_CH3_L_0
39.5.1.5.48 I2S_CH3_L_1
39.5.1.5.49 I2S_CH3_L_2
39.5.1.5.50 I2S_CH3_R_0
39.5.1.5.51 I2S_CH3_R_1
39.5.1.5.52 I2S_CH3_R_2
39.5.1.5.53 I2S_CUV_L_R
39.5.1.6 CEC
39.5.1.6.1 CEC_TX_STATUS_0
39.5.1.6.2 CEC_TX_STATUS_1
39.5.1.6.3 CEC_RX_STATUS_0
39.5.1.6.4 CEC_RX_STATUS_1
39.5.1.6.5 CEC_INTR_MASK
39.5.1.6.6 CEC_INTR_CLEAR
39.5.1.6.7 CEC_LOGIC_ADDR
39.5.1.6.8 CEC_DIVISOR_0
39.5.1.6.9 CEC_DIVISOR_1
39.5.1.6.10 CEC_DIVISOR_2
39.5.1.6.11 CEC_DIVISOR_3
39.5.1.6.12 CEC_TX_CTRL
39.5.1.6.13 CEC_TX_BYTE_NUM
39.5.1.6.14 CEC_TX_STATUS_2
39.5.1.6.15 CEC_TX_STATUS_3
39.5.1.6.16 CEC_TX_BUFFER_x
39.5.1.6.17 CEC_RX_CTRL
39.5.1.6.18 CEC_RX_STATUS_2
39.5.1.6.19 CEC_RX_STATUS_3
39.5.1.6.20 CEC_RX_BUFFER_x
39.5.1.6.21 CEC_FILTER_CTRL
39.5.1.6.22 CEC_FILTER_TH
39.6 HDMI PHY
39.6.1 PHY Configuration Change through APB
39.6.2 PHY Ready Sequence
39.6.3 HDMI PHY Configuration
39.6.4 Register Description
39.6.4.1 Register Map Summary
39.6.4.1.1 PHY
39.6.4.1.1.1 HDMIPHY 4H Register
39.6.4.1.1.2 HDMIPHY 24H Register
39.6.4.1.1.3 HDMIPHY 3CH Register
39.6.4.1.1.4 HDMIPHY 40H Register
39.6.4.1.1.5 HDMIPHY 5CH Register
39.6.4.1.1.6 HDMIPHY 74H Register
39.6.4.1.1.7 HDMIPHY 78H Register
39.6.4.1.1.8 HDMIPHY 7CH Register
39.6.4.1.1.9 HDMI Application Sequences
39.6.4.1.2 DisplayTop
39.6.4.1.2.1 HDMI_MUXCTRL
39.6.4.1.2.2 HDMI_SYNCCTRL0
39.6.4.1.2.3 HDMI_SYNCCTRL1
39.6.4.1.2.4 HDMI_SYNCCTRL2
39.6.4.1.2.5 HDMI_SYNCCTRL3
39.6.4.1.2.6 HDMI Converter FIELD Control0
39.6.4.1.2.7 HDMI Converter FIELD control1
40 MIPI
40.1 Overview
40.2 Features
40.2.1 DSI Master Features (DSIM)
40.2.2 CSI Slave Features (CSIS)
40.3 D-PHY Features
40.4 Block Diagram for DSIM
40.4.1 Internal Primary FIFOs
40.4.2 Packet Header Arbitration
40.4.3 RxFIFO Structure
40.5 Interfaces and Protocol
40.5.1 Display Controller Interface
40.5.2 RGB Interface
40.5.3 HSA Mode
40.5.4 HSE Mode
40.5.5 Transfer General Data in Video Mode
40.5.6 MIPI DSIM Converts RGB Interface to Video Mode
40.6 Configuration
40.7 PLL
40.8 Buffer
40.9 DSIM
40.9.1 Register Description
40.9.1.1 Register Map Summary
40.9.1.1.1 DSIM_STATUS
40.9.1.1.2 DSIM_SWRST
40.9.1.1.3 DSIM_CLKCTRL
40.9.1.1.4 DSIM_TIMEOUT
40.9.1.1.5 DSIM_CONFIG
40.9.1.1.6 DSIM_ESCMODE
40.9.1.1.7 DSIM_MDRESOL
40.9.1.1.8 DSIM_MVPORCH
40.9.1.1.9 DSIM_MHPORCH
40.9.1.1.10 DSIM_MSYNC
40.9.1.1.11 DSIM_SDRESOL
40.9.1.1.12 DSIM_INTSRC
40.9.1.1.13 DSIM_INTMSK
40.9.1.1.14 DSIM_PKTHDR
40.9.1.1.15 DSIM_PAYLOAD
40.9.1.1.16 DSIM_RXFIFO
40.9.1.1.17 DSIM_FIFOTHLD
40.9.1.1.18 DSIM_FIFOCTRL
40.9.1.1.19 DSIM_MEMACCHR
40.9.1.1.20 DSIM_PLLCTRL
40.9.1.1.21 DSIM_PLLCTRL1
40.9.1.1.22 DSIM_PLLCTRL2
40.9.1.1.23 DSIM_PLLTMR
40.9.1.1.24 DSIM_PHYCTRL
40.9.1.1.25 DSIM_PHYCTRL1
40.9.1.1.26 DSIM_PHYTIMING
40.9.1.1.27 DSIM_PHYTIMING1
40.9.1.1.28 DSIM_PHYTIMING2
40.9.1.1.29 DSIM_VERSION
40.9.1.1.30 DSIM_S3D_CTL
40.9.1.1.31 DSIM_P3D_CTL
40.9.1.1.32 DSIM_MIC_CTL
40.9.1.1.33 DSIM_P3D_ON_MIC_OFF_HORIZONTAL
40.9.1.1.34 DSIM_P3D_OFF_MIC_ON_HORIZONTAL
40.9.1.1.35 DSIM_P3D_ON_MIC_ON_HORIZONTAL
40.9.1.1.36 DSIM_P3D_ON_MIC_OFF_HFP
40.9.1.1.37 DSIM_P3D_OFF_MIC_ON_HFP
40.9.1.1.38 DSIM_P3D_ON_MIC_ON_HFP
40.10 CSIS
40.10.1 Interfaces and Protocol
40.10.1.1 D-PHY layer FSM
40.10.1.2 PPI Interface Timing & Protocol
40.10.1.2.1 High Speed Data Transfer
40.10.1.2.2 Ultra-Low Power Mode
40.10.1.2.3 ISP (CAM I/F) Interface
40.10.1.3 Description of Output Protocol
40.10.2 Configuration
40.10.2.1 Image Resolution
40.10.2.2 Image Data Format
40.10.3 Interrupt
40.10.4 Clock Specification
40.10.5 Register Description
40.10.5.1 Register Map Summary
40.10.5.1.1 CSIS_CTRL
40.10.5.1.2 CSIS_DPHYCTRL
40.10.5.1.3 CSIS_CONFIG_CH0
40.10.5.1.4 CSIS_DPHYSTS
40.10.5.1.5 CSIS_INTMSK
40.10.5.1.6 CSIS_INTSRC
40.10.5.1.7 CSIS_CTRL2
40.10.5.1.8 CSIS_VERSION
40.10.5.1.9 B_DPHYCTRL
40.10.5.1.10 S_DPHYCTRL
40.10.5.1.11 CSIS_RESOL_CH0
40.10.5.1.12 SDW_CONFIG_CH0
40.10.5.1.13 SDW_RESOL_CH0
40.10.5.1.14 Non-Image Data Register
40.11 D-PHY
40.11.1 Architecture
40.11.1.1 PLL and Clock Lane Connection
40.11.1.2 Data Lane Connection
40.11.1.3 IP Structure
40.11.1.4 Power Consumption
40.11.1.5 Signals
40.11.1.6 Package and Board Connection Guideline
40.11.1.7 Core Interface Timing Diagram
40.11.1.8 Data Lane: HS-TX and HS-RX Function
40.11.1.9 Clock Lane: ULPS Function
40.11.1.10 Data Lane: ULPS Function
40.11.1.11 Data Lane: LP-TX and LP-RX Function
40.11.1.12 Data Lane: Remote Trigger Reset
40.11.1.13 Data Lane: Turn Around
40.11.1.14 Initialization Sequence
41 Video Input Processor (VIP)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 VIP Interconnection
41.4.1 Block Diagram
41.4.2 Clock Generation
41.4.3 Sync Generation
41.4.3.1 ITU-R BT.601 8-bit
41.4.3.2 ITU-R BT.656
41.4.3.3 ITU BT.656-like support
41.4.4 External Data Valid and Field
41.4.4.1 External Data Valid
41.4.4.2 External Field
41.4.5 Data Order
41.4.6 Status
41.4.6.1 Horizontal & Vertical Counter
41.4.6.2 Current HSYNC & VSYNC Status
41.4.6.3 Current Field Status
41.4.7 FIFO Controls
41.4.8 Recommend Setting for Video Input Port
41.5 Clipper & Decimator
41.5.1 Clipping & Scale-down
41.5.2 Output Data Format
41.5.2.1 Separated YUV format
41.5.3 Interlace Scan Mode
41.5.4 Pixels Alignment
41.6 Interrupt Generation
41.7 Register Description
41.7.1 Register Map Summary
41.7.1.1 VIP_CONFIG
41.7.1.2 VIP_INTCTRL
41.7.1.3 VIP_SYNCCTRL
41.7.1.4 VIP_SYNCMON
41.7.1.5 VIP_VBEGIN
41.7.1.6 VIP_VEND
41.7.1.7 VIP_HBEGIN
41.7.1.8 VIP_HEND
41.7.1.9 VIP_FIFOCTRL
41.7.1.10 VIP_HCOUNT
41.7.1.11 VIP_VCOUNT
41.7.1.12 VIP_EXTCLKINV
41.7.1.13 VIP_CDENB
41.7.1.14 VIP_ODINT
41.7.1.15 VIP_IMGWIDTH
41.7.1.16 VIP_IMGHEIGHT
41.7.1.17 CLIP_LEFT
41.7.1.18 CLIP_RIGHT
41.7.1.19 CLIP_TOP
41.7.1.20 CLIP_BOTTOM
41.7.1.21 DECI_TARGETW
41.7.1.22 DECI_TARGETH
41.7.1.23 DECI_DELTAW
41.7.1.24 DECI_DELTAH
41.7.1.25 DECI_CLEARW
41.7.1.26 DECI_CLEARH
41.7.1.27 DECI_FORMAT
41.7.1.28 DECI_LUADDR
41.7.1.29 DECI_LUSTRIDE
41.7.1.30 DECI_CRADDR
41.7.1.31 DECI_CRSTRIDE
41.7.1.32 DECI_CBADDR
41.7.1.33 DECI_CBSTRIDE
41.7.1.34 CLIP_FORMAT
41.7.1.35 CLIP_LUADDR
41.7.1.36 CLIP_LUSTRIDE
41.7.1.37 CLIP_CRADDR
41.7.1.38 CLIP_CRSTRIDE
41.7.1.39 CLIP_CBADDR
41.7.1.40 CLIP_CBSTRIDE
41.7.1.41 VIP_SCANMODE
41.7.1.42 VIP_PORT_SELECTOR
42 Multi-Format Video Codec
42.1 Overview
42.2 Functional Description
42.2.1 List of Video CODECs
42.2.2 Supported Video Encoding Tools
42.2.2.1 H.264/AVC BP/CBP Encoder
42.2.2.2 MPEG4-SP Encoder
42.2.2.3 H.263 P0/P3 (Interactive and Streaming Wireless Profile) Encoder
42.2.3 Supported Video Decoding Tools
42.2.3.1 H.264/AVC Decoder
42.2.3.2 VC-1/WMV-9 Decoder
42.2.3.3 MPEG-4 Decoder
42.2.3.4 Sorenson Spark Decoder
42.2.3.5 H.263 V2 (Interactive and Streaming Wireless Profile, Profile 3) Decoder
42.2.3.6 MPEG-1/MPEG-2
42.2.3.7 AVS Decoder
42.2.3.8 Real Video 10 Decoder
42.2.3.9 VP8 Decoder
42.2.3.10 Theora Decoder
42.2.4 Supported JPEG Tools
42.2.4.1 MJPEG Baseline Process Encoder and Decoder
42.2.5 Non-codec related features
42.2.5.1 Value Added Features
42.2.5.2 Programmability
42.2.5.3 Optimal External Memory Accesses
43 3D Graphic Engine
43.1 Overview
43.2 Features
43.2.1 Pixel Processor Features
43.2.2 Geometry Processor Features
43.2.3 Level 2 Cache Controller Features
43.2.4 MMU
43.2.5 PMU
43.3 Operation
43.3.1 Clock
43.3.2 Reset
43.3.3 Interrupt
44 Crypto Engine
44.1 Overview
44.2 Features
44.3 Block Diagram
44.4 Functional Description
44.4.1 Polling Mode
44.4.2 Mode
44.5 Register Description
44.5.1 Register Map Summary
44.5.1.1 CRT_CTRL0
44.5.1.2 AES_CTRL0
44.5.1.3 AES_iv0
44.5.1.4 AES_iv1
44.5.1.5 AES_iv2
44.5.1.6 AES_iv3
44.5.1.7 AES_key0
44.5.1.8 AES_key1
44.5.1.9 AES_key2
44.5.1.10 AES_key3
44.5.1.11 AES_key4
44.5.1.12 AES_key5
44.5.1.13 AES_key6
44.5.1.14 AES_key7
44.5.1.15 AES_TEXTIN0
44.5.1.16 AES_TEXTIN1
44.5.1.17 AES_TEXTIN2
44.5.1.18 AES_TEXTIN3
44.5.1.19 AES_TEXTOUT0
44.5.1.20 AES_TEXTOUT1
44.5.1.21 AES_TEXTOUT2
44.5.1.22 AES_TEXTOUT3
44.5.1.23 DES_CTRL0
44.5.1.24 DES_iv0
44.5.1.25 DES_iv1
44.5.1.26 DES_KEY0_0
44.5.1.27 DES_KEY0_1
44.5.1.28 DES_KEY1_0
44.5.1.29 DES_KEY1_1
44.5.1.30 DES_KEY2_0
44.5.1.31 DES_KEY2_1
44.5.1.32 DES_TEXTIN0
44.5.1.33 DES_TEXTIN1
44.5.1.34 DES_TEXTOUT0
44.5.1.35 DES_TEXTOUT1
44.5.1.36 BDMAR
44.5.1.37 BDMAW
44.5.1.38 HDMAR
44.5.1.39 HASH_CTRL0
44.5.1.40 HASH_iv0
44.5.1.41 HASH_iv1
44.5.1.42 HASH_iv2
44.5.1.43 HASH_iv3
44.5.1.44 HASH_iv4
44.5.1.45 HASH_TEXTOUT0
44.5.1.46 HASH_TEXTOUT1
44.5.1.47 HASH_TEXTOUT2
44.5.1.48 HASH_TEXTOUT3
44.5.1.49 HASH_TEXTOUT4
44.5.1.50 HASH_TEXTIN
44.5.1.51 HASH_MSG_SIZE
44.5.1.52 HASH_MSG_SIZE
45 Secure JTAG
45.1 Overview
45.2 Features
45.3 Block Diagram
45.4 Secure JTAG User Configure
46 Temperature Monitor Unit (TMU)
46.1 Overview
46.2 Temperature Sensing Auto Mode with External Clocks
46.3 Temperature Code Table
46.4 I/O Description
46.5 Programming Guide
46.5.1 Software Sequence
46.5.2 Interrupt Service Routine
46.5.3 Tracing Past Temperature
46.6 Register Description
46.6.1 Register Map Summary
46.6.1.1 TRIMINFO
46.6.1.2 TMU_CONTROL
46.6.1.3 TMU_CONTROL1
46.6.1.4 TMU_STATUS
46.6.1.5 SAMPLING_INTERVAL
46.6.1.6 COUNTER_VALUE0
46.6.1.7 COUNTER_VALUE1
46.6.1.8 CURRENT_TEMP0
46.6.1.9 CURRENT_TEMP1
46.6.1.10 THRESHOLD_TEMP_RISE
46.6.1.11 THRESHOLD_TEMP_FALL
46.6.1.12 P0_PAST_TEMP3_0
46.6.1.13 P0_PAST_TEMP7_4
46.6.1.14 P0_PAST_TEMP11_8
46.6.1.15 P0_PAST_TEMP15_12
46.6.1.16 P0_INTEN
46.6.1.17 P0_INTSTAT
46.6.1.18 P0_INTCLEAR
46.6.1.19 EMUL_CON
47 Electrical Characteristics
47.1 Absolute Maximum Ratings
47.2 Recommended Operating Conditions
47.3 D.C. Electrical Characteristics
S5P6818
Application Processor
Revision 0.00
February 2015
User's Manual
2015 Samsung Electronics Co., Ltd. All rights reserved.
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Samsung Confidential
Important Notice
Samsung Electronics Co. Ltd. ("Samsung") reserves the
right to make changes to the information in this publication
at any time without prior notice. All information provided is
for
reference purpose only. Samsung assumes no
responsibility for possible errors or omissions, or for any
consequences resulting from the use of the information
contained herein.
This publication on its own does not convey any license,
either express or implied, relating to any Samsung and/or
third-party products, under the intellectual property rights of
Samsung and/or any third parties.
Samsung makes no warranty, representation, or guarantee
regarding the suitability of its products for any particular
purpose, nor does Samsung assume any liability arising out
of the application or use of any product or circuit and
specifically disclaims any and all liability, including without
limitation any consequential or incidental damages.
Customers are responsible for their own products and
applications. "Typical" parameters can and do vary in
different applications. All operating parameters, including
"Typicals" must be validated for each customer application
by the customer's technical experts.
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claims, costs, damages, expenses, and reasonable attorney
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WARNING No part of this publication may be reproduced,
stored in a retrieval system, or transmitted in any form or by
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警 告 本文件仅向经韩国三星电子株式会社授权的人员提供，
其内容含有商业秘密保护相关法规规定并受其保护的三星电
子株式会社商业秘密，任何直接或间接非法向第三人披露、
传播、复制或允许第三人使用该文件全部或部分内容的行为
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法行为一经发现，三星电子株式会社有权根据相关法规对其
采取法律措施，包括但不限于提出损害赔偿请求。
Copyright 2015 Samsung Electronics Co., Ltd.
Samsung Electronics Co., Lt.
1-1, Samsungjeonja-ro, Hwaseong-si,
Gyeonggi-do, Korea 445-330
Contact Us: mobilesol.cs@samsung.com
Home Page: http://www.samsungsemi.com
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Trademarks
All brand names, trademarks and registered trademarks belong to their respective owners.
Exynos, Exynos 5410, FlexOneNAND, and OneNAND are trademarks of Samsung Electronics.
ARM, Jazelle, TrustZone, and Thumb are registered trademarks of ARM Limited. Cortex, ETM, ETB,
Coresight, ISA, and Neon are trademarks of ARM Limited.
Java is a trademark of Sun Microsystems, Inc.
SD is a registered trademark of Toshiba Corporation.
MMC and eMMC are trademarks of MultiMediaCard Association.
JTAG is a registered trademark of JTAG Technologies, Inc.
Synopsys is a registered trademark of Synopsys, Inc.
I2S is a trademark of Phillips Electronics.
I2C is a trademark of Phillips Semiconductor Corp.
MIPI and Slimbus are registered trademarks of the Mobile Industry Processor Interface (MIPI) Alliance.
All other trademarks used in this publication are the property of their respective owners.
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Chip Handling Guide
Precaution against Electrostatic Discharge
When using semiconductor devices, ensure that the environment is protected against static electricity:
1. Wear antistatic clothes and use earth band.
2. All objects that are in direct contact with devices must be made up of materials that do not produce static
electricity.
3. Ensure that the equipment and work table are earthed.
4. Use ionizer to remove electron charge.
Contamination
Do not use semiconductor products in an environment exposed to dust or dirt adhesion.
Temperature/Humidity
Semiconductor devices are sensitive to:
Environment
Temperature
Humidity
High temperature or humidity deteriorates the characteristics of semiconductor devices. Therefore, do not store or
use semiconductor devices in such conditions.
Mechanical Shock
Do not to apply excessive mechanical shock or force on semiconductor devices.
Chemical
Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that
deteriorate the characteristics of the devices.
Light Protection
In non- Epoxy Molding Compound (EMC) package, do not expose semiconductor IC to bright light. Exposure to
bright light causes malfunctioning of the devices. However, a few special products that utilize light or with security
functions are exempted from this guide.
Radioactive, Cosmic and X-ray
Radioactive substances, cosmic ray, or X-ray may influence semiconductor devices. These substances or rays
may cause a soft error during a device operation. Therefore, ensure to shield the semiconductor devices under
environment that may be exposed to radioactive substances, cosmic ray, or X-ray.
EMS (Electromagnetic Susceptibility)
Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the
operation under insufficient PCB circuit design for Electromagnetic Susceptibility (EMS).
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Revision History
Revision No.
Date
Description
0.00
Feb. 6, 2015
First draft
Author(s)
Chongkun Lee
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Table of Contents
1 PRODUCT OVERVIEW ................................................................................. 1-1
1.1 Introduction .............................................................................................................................................. 1-1
1.2 Features ................................................................................................................................................... 1-2
1.3 Block Diagram .......................................................................................................................................... 1-3
1.4 Brief Functional Specification ................................................................................................................... 1-4
1.4.1 CPU .................................................................................................................................................. 1-4
1.4.2 Clock & Power Management ............................................................................................................ 1-4
1.4.3 DMA .................................................................................................................................................. 1-4
1.4.4 Interrupt Controller ............................................................................................................................ 1-4
1.4.5 Timer & Watchdog Timer .................................................................................................................. 1-5
1.4.6 RTC .................................................................................................................................................. 1-5
1.4.7 Memory Controller ............................................................................................................................ 1-5
1.4.8 GPIO Controller ................................................................................................................................ 1-5
1.4.9 Ethernet MAC Controller .................................................................................................................. 1-6
1.4.10 SD/MMC Controller......................................................................................................................... 1-7
1.4.11 PPM ................................................................................................................................................ 1-7
1.4.12 PWM ............................................................................................................................................... 1-7
1.4.13 ADC ................................................................................................................................................ 1-8
1.4.14 DAC ................................................................................................................................................ 1-8
1.4.15 I2C .................................................................................................................................................. 1-8
1.4.16 SPI/SSP .......................................................................................................................................... 1-9
1.4.17 MPEG-TS ....................................................................................................................................... 1-9
1.4.18 UART& ISO7816 Sim Card Interface ............................................................................................. 1-9
1.4.19 USB .............................................................................................................................................. 1-10
1.4.20 I2S ................................................................................................................................................ 1-11
1.4.21 AC97 ............................................................................................................................................. 1-11
1.4.22 SPDIF Tx, Rx ................................................................................................................................ 1-11
1.4.23 PDM .............................................................................................................................................. 1-12
1.4.24 Display Controller ......................................................................................................................... 1-12
1.4.25 Video Post Processor ................................................................................................................... 1-13
1.4.26 Video Input Processor .................................................................................................................. 1-14
1.4.27 Multi Format MPEG codec ........................................................................................................... 1-14
1.4.28 3D Graphic Controller ................................................................................................................... 1-15
1.4.29 Security IP .................................................................................................................................... 1-16
1.4.30 Unique Chip ID ............................................................................................................................. 1-16
1.4.31 Operating Conditions .................................................................................................................... 1-17
1.4.32 Package ........................................................................................................................................ 1-17
2 MECHANICAL DIMENSION & IO FUNCTION DESCRIPTION ..................... 2-1
2.1 Mechanical Dimension ............................................................................................................................. 2-1
2.2 FCBGA Ball Map ...................................................................................................................................... 2-3
2.3 I/O Function Description .......................................................................................................................... 2-8
2.3.1 Ball List Table ................................................................................................................................... 2-8
2.4 Ball List Table: sorted by Function ......................................................................................................... 2-25
2.4.1 MCU-A ............................................................................................................................................ 2-25
2.4.2 MCU-S ............................................................................................................................................ 2-28
2.4.3 Digital RGB ..................................................................................................................................... 2-30
2.4.4 HDMI ............................................................................................................................................... 2-31
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2.4.5 LVDS .............................................................................................................................................. 2-31
2.4.6 MIPI DSI ......................................................................................................................................... 2-32
2.4.7 MIPI CSI ......................................................................................................................................... 2-32
2.4.8 VIP .................................................................................................................................................. 2-33
2.4.9 Ethernet MAC ................................................................................................................................. 2-34
2.4.10 MPEG-TS Interface ...................................................................................................................... 2-35
2.4.11 UART_ISO7816 ............................................................................................................................ 2-36
2.4.12 I2C ................................................................................................................................................ 2-36
2.4.13 SPI/SSP ........................................................................................................................................ 2-37
2.4.14 PWM ............................................................................................................................................. 2-37
2.4.15 PPM .............................................................................................................................................. 2-37
2.4.16 PDM .............................................................................................................................................. 2-38
2.4.17 SPDIF ........................................................................................................................................... 2-38
2.4.18 SD/MMC ....................................................................................................................................... 2-38
2.4.19 USB 2.0Host ................................................................................................................................. 2-39
2.4.20 USB 2.0 HSIC HOST .................................................................................................................... 2-39
2.4.21 USB 2.0 OTG ................................................................................................................................ 2-40
2.4.22 I2S & AC97 ................................................................................................................................... 2-40
2.4.23 ADC .............................................................................................................................................. 2-41
2.4.24 ALIVE GPIO .................................................................................................................................. 2-41
2.4.25 JTAG ............................................................................................................................................. 2-41
2.4.26 Crystal PLL & RTC ....................................................................................................................... 2-42
2.4.27 Miscellaneous ............................................................................................................................... 2-42
2.4.28 Not Connect (NC) ......................................................................................................................... 2-42
2.4.29 Video DAC .................................................................................................................................... 2-42
2.4.30 TMU (Temperature Monitor Unit) ................................................................................................. 2-43
2.4.31 Power: VDD .................................................................................................................................. 2-43
2.4.32 Power: GND .................................................................................................................................. 2-44
3 SYSTEM BOOT ............................................................................................. 3-1
3.1 Overview .................................................................................................................................................. 3-1
3.2 Functional Description ............................................................................................................................. 3-2
3.2.1 System Configuration ....................................................................................................................... 3-2
3.3 External Static Memory Boot ................................................................................................................... 3-5
3.3.1 External Static Memory Boot Features ............................................................................................. 3-5
3.3.2 External Static Memory Boot System Configuration ........................................................................ 3-5
3.3.3 External Static Memory Boot Operation ........................................................................................... 3-5
3.4 Internal ROM Boot ................................................................................................................................... 3-6
3.4.1 Features ............................................................................................................................................ 3-6
3.4.2 System Configuration for the Internal ROM Booting ........................................................................ 3-6
3.4.3 SPI Boot ............................................................................................................................................ 3-7
3.4.4 UART Boot ........................................................................................................................................ 3-8
3.4.5 USB Boot .......................................................................................................................................... 3-9
3.4.6 SDHC Boot ..................................................................................................................................... 3-12
3.4.7 SDFS Boot ...................................................................................................................................... 3-13
3.4.8 NANDBOOT with Error Correction ................................................................................................. 3-14
3.4.9 Additional Information ..................................................................................................................... 3-17
4 SYSTEM CONTROL ...................................................................................... 4-1
4.1 Overview .................................................................................................................................................. 4-1
4.2 Features ................................................................................................................................................... 4-1
4.3 Block Diagram .......................................................................................................................................... 4-2
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4.4 Clock Manager Functional Description .................................................................................................... 4-3
4.4.1 PLL (Phase Locked Loop) ................................................................................................................ 4-3
4.4.2 Change PLL Value.......................................................................................................................... 4-10
4.4.3 Clock Generator .............................................................................................................................. 4-10
4.5 Power Manager ...................................................................................................................................... 4-15
4.5.1 Power Manager Overview .............................................................................................................. 4-15
4.5.2 Power Down Mode Operation ........................................................................................................ 4-16
4.6 Reset Generation ................................................................................................................................... 4-20
4.6.1 Power On Reset Sequence ............................................................................................................ 4-20
4.6.2 Sleep Mode Wakeup Sequence ..................................................................................................... 4-22
4.6.3 Power off sequence ........................................................................................................................ 4-23
4.6.4 Software Reset and GPIO Reset .................................................................................................... 4-24
4.6.5 Watchdog Reset ............................................................................................................................. 4-24
4.6.6 nPORST, Software Reset, Watchdog Reset and GPIO Reset ...................................................... 4-24
4.7 Tie Off .................................................................................................................................................... 4-25
4.8 AXI BUS ................................................................................................................................................. 4-25
4.8.1 Programmable Quality of Service (ProgQoS) ................................................................................ 4-25
4.8.2 Arbitration Scheme ......................................................................................................................... 4-27
4.9 Register Description ............................................................................................................................... 4-29
4.9.1 Register Map Summary .................................................................................................................. 4-29
4.9.2 Tieoff ............................................................................................................................................... 4-66
4.9.3 AXI BUS ........................................................................................................................................ 4-178
4.9.4 IP Reset ........................................................................................................................................ 4-182
5 CLOCK GENERATOR ................................................................................... 5-1
5.1 IP Clock Generator Overview .................................................................................................................. 5-1
5.2 Clock Generator Level 0 .......................................................................................................................... 5-2
5.2.1 Block Diagram .................................................................................................................................. 5-2
5.2.2 Register Description ......................................................................................................................... 5-3
5.3 Clock Generator Level 1 .......................................................................................................................... 5-7
5.3.1 Block Diagram .................................................................................................................................. 5-7
5.3.2 Register Description ......................................................................................................................... 5-8
5.4 Clock Generator Level 2 ........................................................................................................................ 5-18
5.4.1 Block Diagram ................................................................................................................................ 5-19
5.4.2 Register Description ....................................................................................................................... 5-20
6 BUS ............................................................................................................... 6-1
6.1 Overview .................................................................................................................................................. 6-1
6.2 Features ................................................................................................................................................... 6-1
6.3 Description ............................................................................................................................................... 6-2
6.3.1 AXI BUS Description......................................................................................................................... 6-2
6.3.2 Programmable Quality of Service (ProgQoS) .................................................................................. 6-2
6.4 Register Description ................................................................................................................................. 6-3
6.4.1 Register Map Summary .................................................................................................................... 6-3
7 TRUSTZONE PROTECTION CONTROLLER (TZPC) ................................... 7-1
7.1 Overview .................................................................................................................................................. 7-1
7.2 Features ................................................................................................................................................... 7-1
7.3 TZPC Configuration ................................................................................................................................. 7-2
7.3.1 TZPC0 .............................................................................................................................................. 7-2
7.3.2 TZPC1 .............................................................................................................................................. 7-3
7.3.3 TZPC2 .............................................................................................................................................. 7-4
nexell / ys.kim at 2015.02.12SAMSUNG Confidential
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