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K3RG2G20CM-MGCJ__366F_15x15x0.7_(LPD4 32Gb_3732Mbps).pdf

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    Mobile DRAM Stack Specification
    1.0 COMPARISION BETWEEN LPDDR3 AND LPDDR4
    2.0 KEY FEATURES
    3.0 ORDERING INFORMATION
    4.0 ADDRESS CONFIGURATION
    5.0 PACKAGE DIMENSION & PIN DESCRIPTION
    5.1 LPDDR4 SDRAM Package Dimension
    5.2 LPDDR4 SDRAM PACKAGE BALLOUT
    5.3 PAD DEFINITION AND DESCRIPTION
    5.4 FUNCTIONAL BLOCK DIAGRAM
    6.0 IDD SPECIFICATION
    6.1 IDD Spec Table
    CH.A+B 8Gb+8Gb LPDDR4 SDRAM
    1.0 FUNCTIONAL BLOCK DIAGRAM
    2.0 LPDDR4 PAD DEFINITION AND DESCRIPTION
    3.0 FUNCTIONAL DESCRIPTION
    3.1 LPDDR4 SDRAM ADDRESSING
    3.2 Simplified LPDDR4 State Diagram
    Figure 1. LPDDR4: Simplified Bus Interface State Diagram-1
    Figure 2. LPDDR4: Simplified Bus Interface State Diagram -2
    3.3 Mode Register Definition
    3.3.1 Mode Register Assignment and Definition in LPDDR4 SDRAM
    4.0 TRUTH TABLES
    4.1 CKE Truth Tables
    4.2 State Truth Table
    5.0 ABSOLUTE MAXIMUM RATINGS
    6.0 AC & DC OPERATING CONDITIONS
    6.1 Recommended DC Operating Conditions
    6.2 Input Leakage Current
    6.3 Input/Output Leakage Current
    6.4 Operating Temperature Range
    7.0 AC AND DC INPUT MEASUREMENT LEVELS
    7.1 1.1V High speed LVCMOS (HS_LLVCMOS)
    7.1.1 Standard specifications
    7.1.2 DC electrical characteristics
    Figure 3. LPDDR4 Input AC timing definition for CKE
    Figure 4. LPDDR4 Input AC timing definition for Reset_n and ODT_CA
    7.1.3 AC Over/Undershoot
    Figure 5. Overshoot and Undershoot Definition for Address and Control Pins
    7.2 Differential Input Voltage
    7.2.1 Differential Input Voltage for CK
    Figure 6. CK Differential Input Voltage
    7.2.2 Differential Input Voltage for DQS
    Figure 7. DQS Differential Input Voltage
    7.3 Differential Input Cross Point Voltage
    Figure 8. DQS input Crosspoint (Vix) voltage
    Figure 9. CK input Crosspoint voltage (Vix)
    7.4 Single Ended Output Slew Rate
    Figure 10. Single Ended Output Slew Rate Definition
    7.5 Differential Output Slew Rate
    Figure 11. Differential Output Slew Rate Definition
    7.6 Overshoot and Undershoot for LVSTL
    Figure 12. Overshoot and Undershoot Definition
    8.0 OUTPUT BUFFER CHARACTERISTICS
    8.1 LPDDR4 Driver Output Timing Reference Load
    Figure 13. Driver Output Reference Load for Timing and Slew Rate
    8.2 LVSTL (Low Voltage Swing Terminated Logic) IO System
    Figure 14. LVSTL I/O Cell
    Figure 15. pull-down calibration
    Figure 16. pull-up calibration
    9.0 INPUT/OUTPUT CAPACITANCE
    10.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS
    10.1 IDD Measurement Conditions
    11.0 AC AND DC OUTPUT MEASUREMENT LEVELS
    11.1 Single Ended AC and DC Output Levels
    11.2 Pull-down and Pull-up Driver Characteristics and Calibration
    12.0 ELECTRICAL CHARACTERISTICS AND AC TIMING
    12.1 Clock Specification
    12.1.1 Definition for tCK(avg) and nCK
    12.1.2 Definition for tCK(abs)
    12.1.3 Definition for tCH(avg) and tCL(avg)
    12.1.4 Definition for tCH(abs) and tCL(abs)
    12.1.5 Definition for tJIT(per)
    12.1.6 Definition for tJIT(cc)
    12.1.7 Definition for tERR(nper)
    12.1.8 Definition for duty cycle jitter tJIT(duty)
    12.1.9 Definition for tCK(abs), tCH(abs) and tCL(abs)
    12.2 Period Clock Jitter
    12.2.1 Clock period jitter effects on core timing parameters
    12.2.2 Clock jitter effects on Command/Address timing parameters
    12.2.3 Clock jitter effects on Read timing parameters
    12.2.4 Clock jitter effects on Write timing parameters
    12.3 LPDDR4 Refresh Requirements by Device Density
    12.4 AC Timing
    Figure 17. tCMDCKE Timing
    12.5 CA Rx Voltage and Timing
    Figure 18. CA Receiver (Rx) mask
    Figure 19. Across pin VREF CA voltage variation
    Figure 20. CA Timings at the DRAM pins
    Figure 21. CA TcIPW and SRIN_cIVW definition (for each input pulse)
    Figure 22. CA VIHL_AC definition (for each input pulse)
    12.6 DRAM Data Timing
    Figure 23. Read data timing definitions tQH and tDQSQ across on DQ signals per DQS group
    Figure 24. Read data timing tQW valid window defined per DQ signal
    12.7 DQ Rx Voltage And Timing
    Figure 25. DQ Receiver(Rx) mask
    Figure 26. Across pin VREFDQ voltage variation
    Figure 27. DQ to DQS tDQS2DQ & tDQDQ Timings at the DRAM pins referenced from the internal latch
    Figure 28. DQ TdIPW and SRIN_dIVW definition (for each input pulse)
    Figure 29. DQ VIHL_AC definition (for each input pulse)
    CH.C+D 8Gb+8Gb LPDDR4 SDRAM
    1.0 FUNCTIONAL BLOCK DIAGRAM
    2.0 LPDDR4 PAD DEFINITION AND DESCRIPTION
    3.0 FUNCTIONAL DESCRIPTION
    3.1 LPDDR4 SDRAM ADDRESSING
    3.2 Simplified LPDDR4 State Diagram
    Figure 1. LPDDR4: Simplified Bus Interface State Diagram-1
    Figure 2. LPDDR4: Simplified Bus Interface State Diagram -2
    3.3 Mode Register Definition
    3.3.1 Mode Register Assignment and Definition in LPDDR4 SDRAM
    4.0 TRUTH TABLES
    4.1 CKE Truth Tables
    4.2 State Truth Table
    5.0 ABSOLUTE MAXIMUM RATINGS
    6.0 AC & DC OPERATING CONDITIONS
    6.1 Recommended DC Operating Conditions
    6.2 Input Leakage Current
    6.3 Input/Output Leakage Current
    6.4 Operating Temperature Range
    7.0 AC AND DC INPUT MEASUREMENT LEVELS
    7.1 1.1V High speed LVCMOS (HS_LLVCMOS)
    7.1.1 Standard specifications
    7.1.2 DC electrical characteristics
    Figure 3. LPDDR4 Input AC timing definition for CKE
    Figure 4. LPDDR4 Input AC timing definition for Reset_n and ODT_CA
    7.1.3 AC Over/Undershoot
    Figure 5. Overshoot and Undershoot Definition for Address and Control Pins
    7.2 Differential Input Voltage
    7.2.1 Differential Input Voltage for CK
    Figure 6. CK Differential Input Voltage
    7.2.2 Differential Input Voltage for DQS
    Figure 7. DQS Differential Input Voltage
    7.3 Differential Input Cross Point Voltage
    Figure 8. DQS input Crosspoint (Vix) voltage
    Figure 9. CK input Crosspoint voltage (Vix)
    7.4 Single Ended Output Slew Rate
    Figure 10. Single Ended Output Slew Rate Definition
    7.5 Differential Output Slew Rate
    Figure 11. Differential Output Slew Rate Definition
    7.6 Overshoot and Undershoot for LVSTL
    Figure 12. Overshoot and Undershoot Definition
    8.0 OUTPUT BUFFER CHARACTERISTICS
    8.1 LPDDR4 Driver Output Timing Reference Load
    Figure 13. Driver Output Reference Load for Timing and Slew Rate
    8.2 LVSTL (Low Voltage Swing Terminated Logic) IO System
    Figure 14. LVSTL I/O Cell
    Figure 15. pull-down calibration
    Figure 16. pull-up calibration
    9.0 INPUT/OUTPUT CAPACITANCE
    10.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS
    10.1 IDD Measurement Conditions
    11.0 AC AND DC OUTPUT MEASUREMENT LEVELS
    11.1 Single Ended AC and DC Output Levels
    11.2 Pull-down and Pull-up Driver Characteristics and Calibration
    12.0 ELECTRICAL CHARACTERISTICS AND AC TIMING
    12.1 Clock Specification
    12.1.1 Definition for tCK(avg) and nCK
    12.1.2 Definition for tCK(abs)
    12.1.3 Definition for tCH(avg) and tCL(avg)
    12.1.4 Definition for tCH(abs) and tCL(abs)
    12.1.5 Definition for tJIT(per)
    12.1.6 Definition for tJIT(cc)
    12.1.7 Definition for tERR(nper)
    12.1.8 Definition for duty cycle jitter tJIT(duty)
    12.1.9 Definition for tCK(abs), tCH(abs) and tCL(abs)
    12.2 Period Clock Jitter
    12.2.1 Clock period jitter effects on core timing parameters
    12.2.2 Clock jitter effects on Command/Address timing parameters
    12.2.3 Clock jitter effects on Read timing parameters
    12.2.4 Clock jitter effects on Write timing parameters
    12.3 LPDDR4 Refresh Requirements by Device Density
    12.4 AC Timing
    Figure 17. tCMDCKE Timing
    12.5 CA Rx Voltage and Timing
    Figure 18. CA Receiver (Rx) mask
    Figure 19. Across pin VREF CA voltage variation
    Figure 20. CA Timings at the DRAM pins
    Figure 21. CA TcIPW and SRIN_cIVW definition (for each input pulse)
    Figure 22. CA VIHL_AC definition (for each input pulse)
    12.6 DRAM Data Timing
    Figure 23. Read data timing definitions tQH and tDQSQ across on DQ signals per DQS group
    Figure 24. Read data timing tQW valid window defined per DQ signal
    12.7 DQ Rx Voltage And Timing
    Figure 25. DQ Receiver(Rx) mask
    Figure 26. Across pin VREFDQ voltage variation
    Figure 27. DQ to DQS tDQS2DQ & tDQDQ Timings at the DRAM pins referenced from the internal latch
    Figure 28. DQ TdIPW and SRIN_dIVW definition (for each input pulse)
    Figure 29. DQ VIHL_AC definition (for each input pulse)
    Rev. 1.0, Mar. 2016 K3RG2G20CM Mobile DRAM Stack Specification 366FBGA, 15x15 16Gb DDP (32Mb x32DQ x8banks x2channels) + 16Gb DDP (32Mb x32DQ x8banks x2channels) THIS IS THE TARGET DATASHEET FOR LPDDR4AND CONTENTS CAN BE CHANGED. This document and all information provided herein (collectively, "Information") is provided on an "AS-IS" basis and remains the sole and exclusive property of Samsung Electronics. You must keep all Information in strict confidence and trust, and must not, directly or indi- rectly, in any way, disclose, make accessible, post on the internet, reveal, report, publish, disseminate or transfer any Information to any third party. You must not reproduce or copy Information, without first obtaining express written permission from Samsung Electronics. You must not use, or allow use of, any Information in any manner whatsoever, except to internally evaluate the Information. You must restrict access to Information to those of your employees who have a bonafide need-to-know for such purpose and are bound by obli- gations at least as restrictive as this clause. In order to receive Information, you must agree to the foregoing and to indemnify Samsung for any failure to strictly comply therewith. If you do not agree, please do not accept any receipt of Information. datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2016 Samsung Electronics Co., Ltd. All rights reserved. - 1 - gary.pang@avp-electronics.comSAMSUNG
    datasheet Rev. 1.0 LPDDR4 SDRAM Draft Date Remark 10th Dec, 2015 30th Mar, 2016 Target Final Editor J.Y.Bae J.Y.Bae K3RG2G20CM-MGCJ Revision History Revision No. 0.0 1.0 History - First version for target specification. - Final datasheet. - Correct typo. - Add functional block diagram per channel. - Add note for functional block diagram. - Update Mode Register Definition. 1. Add PPR in MR0 OP[5]. 2. Update MR1 OP[1:0] notes. 3. Change MR7 revision ID : 0001 0000B -> 0001 0001B. 4. Add MR30 and MR39 for testing. - Add Non-Target ODT in MR11 and Command truth table. - Update Command truth table. - Change tDQS2DQ Max value : 650 -> 700 [ps]. - Add tCCDMW parameter. - Update IDD spec values. - Add definition for tCH(abs) and tCL(abs). - Update definition for tJIT(cc). - 2 - gary.pang@avp-electronics.comSAMSUNG
    K3RG2G20CM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM Table Of Contents Mobile DRAM Stack Specification 1.0 COMPARISION BETWEEN LPDDR3 AND LPDDR4 ....................................................................................................................... 6 2.0 KEY FEATURES ............................................................................................................................................................................... 8 3.0 ORDERING INFORMATION ............................................................................................................................................................. 9 4.0 ADDRESS CONFIGURATION .......................................................................................................................................................... 9 5.0 PACKAGE DIMENSION & PIN DESCRIPTION................................................................................................................................ 10 5.1 LPDDR4 SDRAM Package Dimension...........................................................................................................................................10 5.2 LPDDR4 SDRAM PACKAGE BALLOUT........................................................................................................................................11 5.3 PAD DEFINITION AND DESCRIPTION.........................................................................................................................................12 5.4 FUNCTIONAL BLOCK DIAGRAM..................................................................................................................................................13 6.0 IDD SPECIFICATION........................................................................................................................................................................ 14 6.1 IDD Spec Table ..............................................................................................................................................................................17 3.3.1 Mode Register Assignment and Definition in LPDDR4 CH.A+B 8Gb+8Gb LPDDR4 SDRAM 1.0 FUNCTIONAL BLOCK DIAGRAM..................................................................................................................................................... 20 2.0 LPDDR4 PAD DEFINITION AND DESCRIPTION ............................................................................................................................ 21 3.0 FUNCTIONAL DESCRIPTION .......................................................................................................................................................... 22 3.1 LPDDR4 SDRAM ADDRESSING...................................................................................................................................................22 3.2 Simplified LPDDR4 State Diagram .................................................................................................................................................23 3.3 Mode Register Definition ...............................................................................................................................................................25 SDRAM.............................................................................................25 4.0 TRUTH TABLES................................................................................................................................................................................ 43 4.1 CKE Truth Tables ...........................................................................................................................................................................45 4.2 State Truth Table ............................................................................................................................................................................46 5.0 ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................... 48 6.0 AC & DC OPERATING CONDITIONS .............................................................................................................................................. 49 6.1 Recommended DC Operating Conditions ......................................................................................................................................49 6.2 Input Leakage Current ....................................................................................................................................................................49 6.3 Input/Output Leakage Current ........................................................................................................................................................49 6.4 Operating Temperature Range.......................................................................................................................................................49 7.0 AC AND DC INPUT MEASUREMENT LEVELS ............................................................................................................................... 50 7.1 1.1V High speed LVCMOS (HS_LLVCMOS) .................................................................................................................................50 7.1.1 Standard specifications............................................................................................................................................................50 7.1.2 DC electrical characteristics.....................................................................................................................................................50 7.1.2.1 LPDDR4 Input Level for CKE............................................................................................................................................50 7.1.2.2 LPDDR4 Input Level for Reset_n and ODT_CA ...............................................................................................................50 7.1.3 AC Over/Undershoot................................................................................................................................................................51 7.1.3.1 Class-1 LPDDR4 AC Over/Undershoot ............................................................................................................................51 7.2 Differential Input Voltage ................................................................................................................................................................52 7.2.1 Differential Input Voltage for CK ..............................................................................................................................................52 7.2.2 Differential Input Voltage for DQS............................................................................................................................................53 7.3 Differential Input Cross Point Voltage.............................................................................................................................................54 7.4 Single Ended Output Slew Rate .....................................................................................................................................................55 7.5 Differential Output Slew Rate .........................................................................................................................................................56 7.6 Overshoot and Undershoot for LVSTL ...........................................................................................................................................57 8.0 OUTPUT BUFFER CHARACTERISTICS ......................................................................................................................................... 58 8.1 LPDDR4 Driver Output Timing Reference Load.............................................................................................................................58 8.2 LVSTL (Low Voltage Swing Terminated Logic) IO System ............................................................................................................58 9.0 INPUT/OUTPUT CAPACITANCE ..................................................................................................................................................... 60 10.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS.................................................................................................. 61 10.1 IDD Measurement Conditions.......................................................................................................................................................61 11.0 AC AND DC OUTPUT MEASUREMENT LEVELS ......................................................................................................................... 67 11.1 Single Ended AC and DC Output Levels ......................................................................................................................................67 11.2 Pull-down and Pull-up Driver Characteristics and Calibration ......................................................................................................68 12.0 ELECTRICAL CHARACTERISTICS AND AC TIMING ................................................................................................................... 69 12.1 Clock Specification .......................................................................................................................................................................69 12.1.1 Definition for tCK(avg) and nCK.............................................................................................................................................69 12.1.2 Definition for tCK(abs)............................................................................................................................................................69 12.1.3 Definition for tCH(avg) and tCL(avg)......................................................................................................................................69 12.1.4 Definition for tJIT(per) ............................................................................................................................................................69 12.1.5 Definition for tJIT(cc)..............................................................................................................................................................70 12.1.6 Definition for tERR(nper)........................................................................................................................................................70 - 3 - gary.pang@avp-electronics.comSAMSUNG
    K3RG2G20CM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 12.1.7 Definition for duty cycle jitter tJIT(duty)..................................................................................................................................70 12.1.8 Definition for tCK(abs), tCH(abs) and tCL(abs) .....................................................................................................................70 12.2 Period Clock Jitter.........................................................................................................................................................................71 12.2.1 Clock period jitter effects on core timing parameters.............................................................................................................71 12.2.1.1 Cycle time de-rating for core timing parameters ............................................................................................................71 12.2.1.2 Clock Cycle de-rating for core timing parameters ..........................................................................................................71 12.2.2 Clock jitter effects on Command/Address timing parameters ................................................................................................71 12.2.3 Clock jitter effects on Read timing parameters ......................................................................................................................72 12.2.3.1 tRPRE ............................................................................................................................................................................72 12.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) .......................................................................................................72 12.2.3.3 tQSH, tQSL ....................................................................................................................................................................72 12.2.3.4 tRPST.............................................................................................................................................................................72 12.2.4 Clock jitter effects on Write timing parameters ......................................................................................................................72 12.2.4.1 tDS, tDH.........................................................................................................................................................................72 12.2.4.2 tDSS, tDSH ....................................................................................................................................................................72 12.2.4.3 tDQSS............................................................................................................................................................................73 12.3 LPDDR4 Refresh Requirements by Device Density.....................................................................................................................73 12.4 AC Timing .....................................................................................................................................................................................74 12.5 CA Rx Voltage and Timing ...........................................................................................................................................................79 12.6 DRAM Data Timing.......................................................................................................................................................................82 12.7 DQ Rx Voltage And Timing...........................................................................................................................................................85 3.3.1 Mode Register Assignment and Definition in LPDDR4 CH.C+D 8Gb+8Gb LPDDR4 SDRAM 1.0 FUNCTIONAL BLOCK DIAGRAM..................................................................................................................................................... 90 2.0 LPDDR4 PAD DEFINITION AND DESCRIPTION ............................................................................................................................ 91 3.0 FUNCTIONAL DESCRIPTION .......................................................................................................................................................... 92 3.1 LPDDR4 SDRAM ADDRESSING...................................................................................................................................................92 3.2 Simplified LPDDR4 State Diagram .................................................................................................................................................93 3.3 Mode Register Definition ...............................................................................................................................................................95 SDRAM.............................................................................................95 4.0 TRUTH TABLES................................................................................................................................................................................ 113 4.1 CKE Truth Tables ...........................................................................................................................................................................115 4.2 State Truth Table ............................................................................................................................................................................116 5.0 ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................... 118 6.0 AC & DC OPERATING CONDITIONS .............................................................................................................................................. 119 6.1 Recommended DC Operating Conditions ......................................................................................................................................119 6.2 Input Leakage Current ....................................................................................................................................................................119 6.3 Input/Output Leakage Current ........................................................................................................................................................119 6.4 Operating Temperature Range.......................................................................................................................................................119 7.0 AC AND DC INPUT MEASUREMENT LEVELS ............................................................................................................................... 120 7.1 1.1V High speed LVCMOS (HS_LLVCMOS) .................................................................................................................................120 7.1.1 Standard specifications............................................................................................................................................................120 7.1.2 DC electrical characteristics.....................................................................................................................................................120 7.1.2.1 LPDDR4 Input Level for CKE............................................................................................................................................120 7.1.2.2 LPDDR4 Input Level for Reset_n and ODT_CA ...............................................................................................................120 7.1.3 AC Over/Undershoot................................................................................................................................................................121 7.1.3.1 Class-1 LPDDR4 AC Over/Undershoot ............................................................................................................................121 7.2 Differential Input Voltage ................................................................................................................................................................122 7.2.1 Differential Input Voltage for CK ..............................................................................................................................................122 7.2.2 Differential Input Voltage for DQS............................................................................................................................................123 7.3 Differential Input Cross Point Voltage.............................................................................................................................................124 7.4 Single Ended Output Slew Rate .....................................................................................................................................................125 7.5 Differential Output Slew Rate .........................................................................................................................................................126 7.6 Overshoot and Undershoot for LVSTL ...........................................................................................................................................127 8.0 OUTPUT BUFFER CHARACTERISTICS ......................................................................................................................................... 128 8.1 LPDDR4 Driver Output Timing Reference Load.............................................................................................................................128 8.2 LVSTL (Low Voltage Swing Terminated Logic) IO System ............................................................................................................128 9.0 INPUT/OUTPUT CAPACITANCE ..................................................................................................................................................... 130 10.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS.................................................................................................. 131 10.1 IDD Measurement Conditions.......................................................................................................................................................131 11.0 AC AND DC OUTPUT MEASUREMENT LEVELS ......................................................................................................................... 137 11.1 Single Ended AC and DC Output Levels ......................................................................................................................................137 11.2 Pull-down and Pull-up Driver Characteristics and Calibration ......................................................................................................138 12.0 ELECTRICAL CHARACTERISTICS AND AC TIMING ................................................................................................................... 139 12.1 Clock Specification .......................................................................................................................................................................139 12.1.1 Definition for tCK(avg) and nCK.............................................................................................................................................139 - 4 - gary.pang@avp-electronics.comSAMSUNG
    K3RG2G20CM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 12.1.2 Definition for tCK(abs)............................................................................................................................................................139 12.1.3 Definition for tCH(avg) and tCL(avg)......................................................................................................................................139 12.1.4 Definition for tJIT(per) ............................................................................................................................................................139 12.1.5 Definition for tJIT(cc)..............................................................................................................................................................140 12.1.6 Definition for tERR(nper)........................................................................................................................................................140 12.1.7 Definition for duty cycle jitter tJIT(duty)..................................................................................................................................140 12.1.8 Definition for tCK(abs), tCH(abs) and tCL(abs) .....................................................................................................................140 12.2 Period Clock Jitter.........................................................................................................................................................................141 12.2.1 Clock period jitter effects on core timing parameters.............................................................................................................141 12.2.1.1 Cycle time de-rating for core timing parameters ............................................................................................................141 12.2.1.2 Clock Cycle de-rating for core timing parameters ..........................................................................................................141 12.2.2 Clock jitter effects on Command/Address timing parameters ................................................................................................141 12.2.3 Clock jitter effects on Read timing parameters ......................................................................................................................142 12.2.3.1 tRPRE ............................................................................................................................................................................142 12.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) .......................................................................................................142 12.2.3.3 tQSH, tQSL ....................................................................................................................................................................142 12.2.3.4 tRPST.............................................................................................................................................................................142 12.2.4 Clock jitter effects on Write timing parameters ......................................................................................................................142 12.2.4.1 tDS, tDH.........................................................................................................................................................................142 12.2.4.2 tDSS, tDSH ....................................................................................................................................................................142 12.2.4.3 tDQSS............................................................................................................................................................................143 12.3 LPDDR4 Refresh Requirements by Device Density.....................................................................................................................143 12.4 AC Timing .....................................................................................................................................................................................144 12.5 CA Rx Voltage and Timing ...........................................................................................................................................................149 12.6 DRAM Data Timing.......................................................................................................................................................................152 12.7 DQ Rx Voltage And Timing...........................................................................................................................................................155 - 5 - gary.pang@avp-electronics.comSAMSUNG
    K3RG2G20CM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 1.0 COMPARISION BETWEEN LPDDR3 AND LPDDR4 Items CLK scheme Data scheme DQS scheme ADD / CMD scheme State Diagram Command Truth Table Data mask Truth Table I/O Interface Burst Length Burst Type No Wrap # of Bank per channel Organization per channel Data Mask Refresh mode Masked Write DBI Row Column Bank Refresh Requirements Speed bin [Mbps] Read/Write latency Core Parameters IO Parameters CA / CS / Setup / Hold / Deratin Data Setup / Hold / Deratin PASR TCSR Deep Power Down Configurable D/S ZQ Calibration DQ Calibration CA Calibration Write Leveling VDD1 [V] VDD2 [V] VDDQ [V] VDDCA [V] Feature Addressing AC Parameter Special Function Power Supply IDD Specification Parameters and Test Conditions Temperature IDD Measurement Conditions IDD Specification General [’C] - 6 - LPDDR3 Differential (CLK/CLKB) DDR Single-ended, Bi-Directional Differential (DQS/DQSB), Bi-Directional DDR Refer to the Datasheet No support BST As is HSUL_12 8 Sequential No support 8 x16/x32 LPDDR4 SDR Refer to the Datasheet Refer to the Datasheet LVSTL_11 16, 32(OTF) x16 Support (Write) Auto / Self Refresh N/A N/A Support (Masked Write) Support Support Refer to the Datasheet (CA0 ~ CA9 1clock DDR based) Refer to the datasheet (4Gb per channel) (CA0 ~ CA5 4clock SDR based) 1600/1866 3200/3733 Refer to the Datasheet Refer to the datasheet Support Support No Support Support Support Support1) Support Support 1.70 ~ 1.95 1.14 ~ 1.30 1.14 ~ 1.30 1.14 ~ 1.30 As is As is -25 ~ 85 N/A Refer to the datasheet 1.06 ~ 1.17 1.06 ~ 1.17 N/A BL16 based Refer to the datasheet gary.pang@avp-electronics.comSAMSUNG
    K3RG2G20CM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM LPDDR3 As is As is N/A N/A As is As is LPDDR4 Support Support Refer to the Datasheet Refer to the Datasheet -0.4 ~ 2.3 -0.4 ~ 1.6 -0.4 ~ 1.6 -0.4 ~ 1.6 -0.4 ~ 1.6 -55 ~ 125 As is AC : VREF ± 0.150V / ± 0.135V DC : VREF ± 0.10V/0.10V (1600/1866) (1600/1866) -0.4 ~ 2.1 -0.4 ~ 1.5 -0.4 ~ 1.5 N/A -0.4 ~ 1.5 -2 ~ 2 VREF(CA), Internal VREF AC : 0.75×VDD2 @ Min VDD2+0.2 @ Max DC : 0.65×VDD2 @ Min VDD2+0.2 @ Max VREF(DQ), Internal VREF Pull-down Pull-up Characteristics Items w/ ZQ Calibration w/o ZQ Calibration w/ VOH Calibration w/o VOH Calibration Temperature and Voltage Sensitivity Input/Output Capacitance1) Absolute maximum DC ratings RZQI-V Curve VDD1 [V] VDD2 [V] VDDQ [V] VDDCA [V] VIN/VOUT [V] Tstg [’C] Input leakage [uA] CA and CS pins AC/DC Logic Input Lev- els for Single-ended Sig- nals CKE pin 0.65×VDDCA ~ 0.35×VDDCA DQ pins AC : VREF ± 0.15V/0.135V DC : VREF ± 0.10V/0.10V (1600/1866) (1600/1866) VREF_CA/DQ tolerance 0.49×VDDQ ~ 0.51×VDDQ Internal VREF Input/Output Operating con- dition AC/DC Logic Input Lev- els for Differential Differential Input Cross Point Voltage Slew Rate definitions for Differential AC/DC Output levels for Differential Single ended output Slew Differential Output Slew Overshoot / Undershoot VIHdiff/VILdiff (AC/DC) tDVAC VSEH/VSEL(AC) VIXCA/VIXDQ VILdiff /VIHdiff (Max/Min) VOHdiff / VOLdiff (AC) IOZ MMPUPD VOH/VOL(AC/DC) SRQse VOHdiff/VOLdiff(AC) SRQdiff Maximum Amplitude Maximum Area NOTE: 1) The parameter applies to both die and package. Driver Output Timing As is As is As is As is As is As is As is As is As is As is As is As is VDD/VSS : 0.1[V-ns] HSUL_12 TBD TBD TBD TBD TBD -5 ~ 5 TBD TBD 3.5 ~ 9.0 TBD 7.0 ~ 18.0 LVSTL_11 - 7 - gary.pang@avp-electronics.comSAMSUNG
    K3RG2G20CM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM LPDDR4 SDRAM SPECIFICATION Channel A+B : 16Gb DDP (32Mx32DQx8banks x2channels) LPDDR4 SDRAM / Channel C+D : 16Gb DDP (32Mx32DQx8banks x2channels) LPDDR4 SDRAM 366FBGA_15x15 2.0 KEY FEATURES • Double-data rate architecture; two data transfers per clock cycle • Bidirectional data strobes (DQS_t, DQS_c), These are transmitted/received with data to be used in capturing data at the receiver • Differential clock inputs (CK_t and CK_c) • Differential data strobes (DQS_t and DQS_c) • Commands & addresses entered positive CK edges; data and data mask referenced to both edges of DQS • 2channel composition per die • 8 internal banks for each channel • DMI Pin : DBI (Data Bus Inversion) when normal write and read operation, Data mask (DM) for masked write when DBI off - Counting # of DQ’s 1 for masked write when DBI on • Burst Length: 16, 32 (OTF) • Burst Type: Sequential • Read & Write latency : Refer to Table 47 LPDDR4 AC Timing Table • Auto Precharge option for each burst access • Configurable Drive Strength • Refresh and Self Refresh Modes • Partial Array Self Refresh and Temperature Compensated Self Refresh • Write Leveling • CA Calibration • Internal VREF and VREF training • FIFO based write/read training • MPC (Multi Purpose Command) • LVSTL (Low Voltage Swing Terminated Logic) IO • VDD1/VDD2/VDDQ : 1.8V/1.1V/1.1V • VSSQ Termination • No DLL : CK to DQS is not synchronized • Edge aligned data output, write training for data input center align • Refresh rate : 3.9us • Operating Temperature : -25 ~ 85C - 8 - gary.pang@avp-electronics.comSAMSUNG
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