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VCS USER GUIDE.pdf

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    VCS Document Navigator
    Contents
    Getting Started
    Simulator Support with Technologies
    Setting Up the Simulator
    Verifying Your System Configuration
    Obtaining a License
    Setting Up Your Environment
    Setting Up Your C Compiler
    Creating a synopsys_sim.setup File
    The Concept of a Library In VCS MX
    Library Name Mapping
    Including Other Setup Files
    Using SYNOPSYS_SIM_SETUP Environment Variable
    Displaying Setup Information
    Displaying Design Information Analyzed Into a Library
    Using the Simulator
    Basic Usage Model
    Default Time Unit and Time Precision
    Searching Identifiers in the Design Using UNIX Commands
    Examples
    VCS MX Flow
    Three-step Flow
    Analysis
    Using vhdlan
    Commonly Used Analysis Options
    Using vlogan
    Commonly Used Analysis Options
    Analyzing the Design to Different Libraries
    Elaboration
    Using vcs
    Commonly Used Options
    Simulation
    Interactive Mode
    Batch Mode
    Commonly Used Runtime Options
    Two-step Flow
    Compilation
    Using vcs
    Commonly Used Options
    Simulation
    Interactive Mode
    Batch Mode
    Commonly Used Runtime Options
    Elaborating the Design
    Compiling or Elaborating the Design in Debug Mode
    Compiling or Elaborating the Design in Optimized Mode
    Dynamic Loading of DPI Libraries at Runtime
    The Use Model
    Dynamic Loading of PLI Libraries at Runtime
    Key Elaboration Features
    Initializing Verilog Memories and Registers
    Use Model
    Initializing Verilog Variables, Memories, and MDAs in Parts of the Design
    Example
    Changing or Adding Initialized Parts of the Design at Runtime
    Dumping Initialized Values in a File
    Restricting +vcs+initreg Initialization to Either Registers or Memories
    Overriding Generics and Parameters
    Usage Model
    Checking for X and Z Values In Conditional Expressions
    Enabling the Checking
    Filtering Out False Negatives
    Cross Module References (XMRs)
    hdl_xmr Procedure and $hdl_xmr System Task
    Data Types Supported
    VHDL Referencing Verilog using hdl_xmr procedure
    Verilog Referencing VHDL objects using $hdl_xmr
    Usage Model
    $hdl_xmr Support for VHDL Variables
    Use Model
    Datatype Support and Usage Examples
    VCS MX V2K Configurations and Libmaps
    Library Mapping Files
    Resolving ‘include Compiler Directives
    Configurations
    Configuration Syntax
    Use Model
    Example
    Supported Features
    Limitations of Configurations
    Using the -liblist Option
    Design Cells and Library Cells
    Library Search Order Rules
    Library Search Order Rules for MX Designs
    Library Search Order Rules for Verilog or SystemVerilog Designs
    Example Testcase Files
    Usage Examples for Library Search Order Rules for Verilog or SystemVerilog Designs
    Usage Examples for RULE1
    Usage Examples for RULE2
    Usage Examples for RULE3
    Usage Examples for RULE7
    Usage Examples for RULE8
    Usage Examples for Library Search Order Rules for Verilog or SystemVerilog Designs Without Configuration File
    Lint Warning Message for Missing ‘endcelldefine
    Error/Warning/Lint Message Control
    Controlling Error/Warning/Lint Messages Using Compile-Time Options
    Controlling Error Messages
    Upgrading Lint and Warning Messages to Error Messages
    Controlling Warning Messages
    Upgrading Lint Messages to Warning Messages
    Controlling Lint Messages
    Suppressing Lint, Warning, and Error Messages
    Error Conditions and Messages That Cannot Be Disabled
    Using Message Control Options Together
    Message Control Examples
    Controlling Error/Warning/Lint Messages Using a Configuration File
    Controlling Lint Messages
    Controlling Warning Messages
    Controlling Error Messages
    Upgrading Lint and Warning Messages to Error Messages
    Downgrading Error Messages to Warning Messages
    Suppressing All Types of Messages
    Enabling and Disabling by Source File
    Enabling and Disabling by Module Definition
    Enabling and Disabling by Subhierarchy
    Extracting the Files Used in Elaboration
    XML File Format
    Example
    Limitations
    Simulating the Design
    Using DVE
    Using UCLI
    ucli2Proc Command
    Options for Debugging Using DVE and UCLI
    Reporting Forces/Injections in a Simulation
    Use Model
    Reporting Force/Deposit/Release Information
    Handling Forces on Bit/Part Select and MDA Word
    Handling Forces on Concatenated Codes
    Output Format
    Header Section
    Event List Section
    Usage Example
    Limitations
    Key Runtime Features
    Overriding Generics at Runtime
    Usage Model
    Example
    Passing Values from the Runtime Command Line
    VCS MX Supports simv -f
    Limitations
    Specifying a Long Time Before Stopping The Simulation
    The Unified Simulation Profiler
    The Use Model
    Omitting Profiling at Runtime
    Omitting the -simprofile Runtime Option
    Omitting Profile Report Writing after Runtime
    Specifying a Directory for the Profile Database
    Post Simulation Profile Information
    Specifying the Name of the Profile Report
    Running the profrpt Profile Report Generator
    Specifying Views
    The Snapshot Mechanism
    Specifying Timeline Reports
    Recording and Viewing Memory Stack Traces
    Reporting PLI, DPI, and DirectC Function Call Information
    Compiling and Running the Profiler Example
    Profiling Time Used by Various Parts of the Design
    Profiling Memory Used by Various Parts of the Design
    The Output Directories and Files
    The Enhanced Accumulative Views
    The Comparative View
    The Caller-Callee Views
    HTML Profiler Reports
    Hypertext Links to the Source Files
    Single Text Format Report
    Stack Trace Report Example
    SystemC Views
    Constraint Profiling Integrated in the Unified Profiler
    Changes to the Use Model for Constraint Profiling
    The Time Constraint Solver View
    The Memory Constraint Solver View
    Performance/Memory Profiling for Coverage Covergroups
    Use Model
    Example
    HTML Profiler Reports
    Default Summary View
    Time/Memory Summary View
    Time/Memory Module View
    Time/Memory Construct View
    Time/Memory Covergroup View
    Limitations
    Diagnostics
    Using Diagnostics
    Using –diag Option
    Syntax
    Using Smartlog
    Compile-time Diagnostics
    Libconfig Diagnostics
    Example
    Timescale Diagnostics
    Example
    Example 1: Module has `timescale
    Example 2: Passing -timescale from vcs command-line
    Runtime Diagnostics
    Diagnostics for VPI/VHPI PLI Applications
    Keeping the UCLI/DVE Prompt Active After a Runtime Error
    UCLI Use Model
    Automating User Actions on Failure
    DVE Use Model
    UCLI Usage Example
    Limitations
    Diagnosing Quickthread Issues in SystemC
    Quickthread Overruns Its Allocated Stack
    Limitations
    Simulation Runs Out of Memory Due to Quickthread Stacks
    Reducing or Turning Off Redzones
    Post-processing Diagnostics
    Using the vpdutil Utility to Generate Statistics
    The vpdutil Utility Syntax
    Options
    Options for VPD File Information
    Options for Design Information
    Options for Value Change Information
    VCS Multicore Technology Application Level Parallelism
    Enabling Multicore Technology Application Level Parallelism
    Multicore SAIF File Dumping
    Limitations
    VPD, VCD, and EVCD Utilities
    Advantages of VPD
    Dumping a VPD File
    Using System Tasks
    Enable and Disable Dumping
    Override the VPD Filename
    Dump Multi-dimensional Arrays and Memories
    Syntax for Specifying MDAs
    Examples
    Using $vcdplusmemorydump
    Capture Delta Cycle Information
    Dumping an EVCD File
    Limitations
    Post-processing Utilities
    The vcdiff Utility
    The vcdiff Utility Syntax
    The vcdiff Utility Output Example
    The vcat Utility
    The vcat Utility Syntax
    Generating Source Files From VCD Files
    Writing the Configuration File
    The vcsplit Utility
    The vcsplit Utility Syntax
    The vcd2vpd Utility
    Options for specifying EVCD options
    The vpd2vcd Utility
    The Command File Syntax
    Limitations
    The vpdmerge Utility
    Restrictions
    Limitations
    Value Conflicts
    The vpdutil Utility
    Performance Tuning
    Compile-time Performance
    Incremental Compilation
    Compile Once and Run Many Times
    Parallel Compilation
    Runtime Performance
    Using Radiant Technology
    Compiling With Radiant Technology
    Applying Radiant Technology to Parts of the Design
    The Configuration File Syntax
    Configuration File Statement Examples
    Known Limitations
    Potential Differences in Coverage Metrics
    Compilation Performance With Radiant Technology
    Improving Performance When Using PLIs
    Usage Model
    Impact on Performance
    Obtaining VCS Consumption of CPU Resources
    Use Model
    Compile time
    Simulation Time
    Using X-Propagation
    Introduction to X-Propagation
    Guidelines for Running X-Propagation Simulations
    Using the X-Propagation Simulator
    Specifying X-propagation Merge Mode
    Compile Time Diagnostic Report
    Querying X-Propagation at Run Time
    X-Propagation Instrumentation Report
    Enabling Automatic Flip-Flop Recognition
    X-Propagation Configuration File
    X-Propagation Configuration File Syntax
    X-Propagation Instrumentation Definition
    X-Propagation Merge Mode Specification
    Xprop Instrumentation Control
    Process Based X-Propagation Exclusion
    Bounds Checking
    Changing $uniq_prior_checkoff/on Usage Model
    Time Zero Initialization
    Handling Non-pure Functions Due to Static Lifetime
    X-Propagation Code Examples
    If Statement
    Case Statement
    Edge Sensitive Expression
    Latch
    Limitations
    Gate-level Simulation
    SDF Annotation
    Using Unified SDF Feature
    Using $sdf_annotate System Task
    Using -xlrm Option for SDF Retain, Gate Pulse Propagation, and Gate Pulse Detection Warning
    Using Optimistic Mode in SDF
    Using Gate Pulse Propagation
    Generating Warnings During Gate Pulses
    Precompiling an SDF File
    Creating the Precompiled Version of the SDF file
    Precompiling SDF alone Without Compiling Design Files
    Writing Precompiled SDF to a Different Directory
    SDF Configuration File
    Delay Objects and Constructs
    SDF Configuration File Commands
    approx_command
    mtm_command
    scale_command
    SDF Example with Configuration File
    Delays and Timing
    Transport and Inertial Delays
    The Inertial Delay Implementation
    Enabling Transport Delays
    Pulse Control
    Pulse Control with Transport Delays
    Pulse Control with Inertial Delays
    Specifying Pulse on Event or Detect Behavior
    Specifying the Delay Mode
    Using the Configuration File to Disable Timing
    Using the timopt Timing Optimizer
    Editing the timopt.cfg File
    Editing Potential Sequential Device Entries
    Editing Clock Signal Entries
    Using Scan Simulation Optimizer
    ScanOpt Config File Format
    ScanOpt Assumptions
    Combinational Path Delays
    Length of Test Cycles
    Negative Timing Checks
    The Need for Negative Value Timing Checks
    The $setuphold Timing Check Extended Syntax
    Negative Timing Checks for Asynchronous Controls
    The $recrem Timing Check Syntax
    Enabling Negative Timing Checks
    Other Timing Checks Using the Delayed Signals
    Checking Conditions
    Toggling the Notifier Register
    SDF Back-annotation to Negative Timing Checks
    How VCS MX Calculates Delays
    Using VITAL Models and Netlists
    Validating and Optimizing a VITAL Model
    Validating the Model for VITAL Conformance
    Verifying the Model for Functionality
    Optimizing the Model for Performance and Capacity
    Re-Verifying the Model for Functionality
    Understanding Error and Warning Messages
    Distributing a VITAL Model
    Simulating a VITAL Netlist
    Applying Stimulus
    Overriding Generic Parameter Values
    Understanding VCS MX Error Messages
    System Errors
    Model and Netlist Errors
    Viewing VITAL Subprograms
    Timing Back-annotation
    VCS MX Naming Styles
    Negative Constraints Calculation (NCC)
    Simulating in Functional Mode
    Understanding VITAL Timing Delays and Error Messages
    Negative Constraint Calculation (NCC)
    Conformance Checks
    Type Checks
    Syntactic and Semantic Checks
    Error Messages
    Coverage
    Code Coverage
    Functional Coverage
    Options For Coverage Metrics
    Using SystemVerilog
    Usage Model
    Using UVM With VCS
    Update on UVM-1.0
    Update on UVM-EA
    Natively Compiling and Elaborating UVM-1.0
    Natively Compiling and Elaborating UVM-1.1d
    Compiling the External UVM Library
    Using the -ntb_opts uvm Option
    Specifying External uvm_dpi.cc Source
    Explicitly Specifying UVM Files and Arguments
    Accessing HDL Registers Through UVM Backdoor
    Generating UVM Register Abstraction Layer Code
    Recording UVM Transactions
    Debugging UVM Testbench Designs Using DVE
    Recording UVM Phases
    UVM Template Generator (uvmgen)
    Using Mixed VMM/UVM Libraries
    Migrating from OVM to UVM
    Where to Find UVM Examples
    Where to Find UVM Documentation
    UVM-1.1d Documentation
    UVM-1.0 Documentation
    UVM-VMM Interop Documentation
    Using VMM with VCS
    Using OVM with VCS
    Native Compilation and Elaboration of OVM 2.1.2
    Compiling the External OVM Library
    Using the -ntb_opts ovm Option
    Explicitly Specifying OVM Files and Arguments
    Recording OVM Transactions
    Debugging SystemVerilog Designs
    Functional Coverage
    Newly implemented SystemVerilog Constructs
    Modport Expressions in an Interface
    Limitations
    Interface Classes
    Difference Between Extends and Implements
    Cast and Interface Class
    Name Conflicts and Resolution
    Name Conflicts During Implementation
    Name Conflicts During Inheritance
    Interface Class and Randomization
    Package Exports
    Severity System Tasks as Procedural Statements
    Width Casting Using Parameters
    Recently Implemented SystemVerilog Constructs
    The std::randomize() Function
    Syntax
    Description
    Example
    SystemVerilog Bounded Queues
    wait() Statement with a Static Class Member Variable
    Parameters and Localparams in Classes
    SystemVerilog Math Functions
    Streaming Operators
    Packing (Used on RHS)
    Primitive Operation
    Streaming Concatenation
    Unpacking (Used on LHS)
    Primitive operation
    Streaming Concatenation
    Packing and Unpacking
    Propagation and force Statement
    Error Conditions
    Structures with Streaming Operators
    Constant Functions in Generate Blocks
    Support for Aggregate Methods in Constraints Using the “with” Construct
    Debugging During Initialization SystemVerilog Static Functions and Tasks in Module Definitions
    Example
    Explicit External Constraint Blocks
    Using an Empty Constraint Block
    The Explicit Form in Previous Releases
    Generate Constructs in Program Blocks
    Error Condition for Using a Genvar Outside of its Generate Block
    Randomizing Unpacked Structs
    Using the Scope Randomize Method std::randomize()
    Using the Class Randomize Method randomize()
    Disabling and Re-enabling Randomization
    Using In-line Random Variable Control
    Limitation
    Making wait fork Statements Compliant with the SV LRM
    Making disable fork Statements Compliant with the SV LRM
    Extensions to SystemVerilog
    Unique/Priority Case/IF Final Semantic Enhancements
    Using Unique/Priority Case/If with Always Block or Continuous Assign
    Using Unique/Priority Inside a Function
    System Tasks to Control Warning Messages
    Single-Sized Packed Dimension Extension
    Covariant Virtual Function Return Types
    Self Instance of a Virtual Interface
    UVM Example
    Error Condition for Using a Genvar Outside of its Generate Block
    Using a Package in a SystemVerilog Module, Program, and Interface Header
    Using OpenVera Native Testbench
    Usage Model
    Example
    Usage Model
    Importing VHDL Procedures
    Exporting OpenVera Tasks
    Using Template Generator
    Example
    Design Description
    Generating the Testbench Template, the Interface, and the Top- level Verilog Module from the Design
    Testbench Development and Description
    Interface Description
    Interface for SRAM, sram.if.vrh
    Top-level Verilog Module Description
    Compiling Testbench With the Design And Running
    Key Features
    Multiple Program Support
    Configuration File Model
    Configuration File
    Usage Model for Multiple Programs
    NTB Options and the Configuration File
    Class Dependency Source File Reordering
    Circular Dependencies
    Dependency-based Ordering in Encrypted Files
    Using Encrypted Files
    Functional Coverage
    Using Reference Verification Methodology
    Limitations
    Aspect Oriented Extensions
    Aspect-Oriented Extensions in SV
    Processing of AOE as a Precompilation Expansion
    Weaving advice into the target method
    Pre-compilation Expansion details
    Precedence
    Adding of Introductions
    Weaving of advices
    Symbol Resolution Details:
    Examples:
    hide_list details
    Examples
    Using Constraints
    Inconsistent Constraints
    Constraint Debug
    Partition
    Randomize Serial Number
    Solver Trace
    Constraint Profiler
    Test Case Extraction
    Using multiple +ntb_solver_debug arguments
    Summary for +ntb_solver_debug
    +ntb_solver_debug=serial
    +ntb_solver_debug=trace
    +ntb_solver_debug=profile
    +ntb_solver_debug=extract
    Constraint Debug Using DVE
    Constraint Guard Error Suppression
    Error Message Suppression Limitations
    Flattening Nested Guard Expressions
    Pushing Guard Expressions into Foreach Loops
    Array and XMR Support in std::randomize()
    Error Conditions
    XMR Support in Constraints
    XMR Function Calls in Constraints
    State Variable Index in Constraints
    Runtime Check for State Versus Random Variables
    Array Index
    Using DPI Function Calls in Constraints
    Invoking Non-pure DPI Functions from Constraints
    Using Foreach Loops Over Packed Dimensions in Constraints
    Memories with Packed Dimensions
    Single Packed Dimension
    Multiple Packed Dimensions
    MDAs with Packed Dimensions
    Single Packed Dimension
    Multiple Packed Dimensions
    Just Packed Dimensions
    The foreach Iterative Constraint for Packed Arrays
    Randomized Objects in a Structure
    Support for Typecast in Constraints
    Syntax
    Description
    Examples
    Strings in Constraints
    SystemVerilog LRM P1800-2012 Update
    Using Soft Constraints in SystemVerilog
    Using Soft Constraints
    Soft Constraint Prioritization
    Within a Single Class
    Soft Constraints Defined in Classes Instantiated as rand Members in Another Class
    Soft Constraints Inheritance Between Classes
    Soft Constraints in AOP Extensions to a Class
    Soft Constraints in View Constraints Blocks
    Discarding Lower-Priority Soft Constraints
    Unique Constraints
    Extensions for SystemVerilog Coverage
    Support for Reference Arguments in get_coverage()
    get_inst_coverage() method
    get_coverage() method
    Functional Coverage Methodology Using the SystemVerilog C/C++ Interface
    SystemVerilog Functional Coverage Flow
    Covergroup Definition
    SystemVerilog (Covergroup for C/C++): covg.sv
    C Testbench: test.c
    Approach #1: Passing Arguments by Reference
    Approach #2: Passing Arguments by Value
    Compile Flow
    Runtime
    C/C++ Functional Coverage API Specification
    Parameters
    Description
    Parameters
    Description
    Parameters
    Description
    OpenVera-SystemVerilog Testbench Interoperability
    Scope of Interoperability
    Importing OpenVera types into SystemVerilog
    Data Type Mapping
    Mailboxes and Semaphores
    Events
    Strings
    Enumerated Types
    Integers and Bit-Vectors
    Arrays
    Structs and Unions
    Connecting to the Design
    Mapping Modports to Virtual Ports
    Virtual Modports
    Importing Clocking Block Members into a Modport
    Semantic Issues with Samples, Drives, and Expects
    Notes to Remember
    Blocking Functions in OpenVera
    Constraints and Randomization
    Functional Coverage
    Usage Model
    Limitations
    Using SystemVerilog Assertions
    Using SVAs in the HDL Design
    Using Standard Checker Library
    Instantiating SVA Checkers in Verilog
    Instantiating SVA Checkers in VHDL
    Inlining SVAs in the Verilog Design
    Usage Model
    Inlining SVA in the VHDL design
    Usage Model
    Controlling SystemVerilog Assertions
    Elaboration and Runtime Options
    Concatenating Assertion Options
    Assertion Monitoring System Tasks
    Using Assertion Categories
    Using System Tasks
    Using Assertion System Tasks
    Using Attributes
    Stopping and Restarting Assertions By Category
    Starting and Stopping Assertions Using Assertion System Tasks
    Viewing Results
    Using a Report File
    Enhanced Reporting for SystemVerilog Assertions in Functions
    Introduction
    Usage Model
    Name Conflict Resolution
    Checker and Generate Blocks
    Controlling Assertion Failure Messages
    Introduction
    Options for Controlling Default Assertion Failure Messages
    Options to Control Termination of Simulation
    Option to Enable Compilation of OVA Case Pragmas
    Reporting Values of Variables in the Assertion Failure Messages
    Limitations
    Using SystemVerilog Constructs Inside vunits
    Limitations
    List of supported IEEE Std. 1800-2009 Compliant SVA Features
    Enabling IEEE Std. 1800-2009 Compliant Features
    Limitations
    SystemVerilog Assertions Limitations
    Debug Support for New Constructs
    Note on Cross Features
    Using Property Specification Language
    Including PSL in the Design
    Examples
    Usage Model
    Examples
    PSL Assertions Inside VHDL Block Statements in Vunit
    Introduction
    Example
    Use Model
    Limitations
    PSL Macro Support in VHDL
    Using the %for Construct
    Using the %if Construct
    Using Expressions with %if and %for Constructs
    PSL Macro Support Limitations
    Using SVA Options, SVA System Tasks, and OV Classes
    Limitations
    Using SystemC
    Overview
    The syscan Utility
    VCSSYSTEMC Macro for Compiling VCS-Specific Code
    Verilog Design Containing Verilog/VHDL Modules and SystemC Leaf Modules
    Usage Model
    Input Files Required
    Generating Verilog/VHDL Wrappers for SystemC Modules
    Creating Verilog/VHDL Wrapper from a SystemC Header File
    Supported Port Data Types
    Example
    Compiling Interface Models with acc_user.h and vhpi_user.h
    Controlling Time Scale and Resolution in a SystemC
    Automatic Adjustment of the Time Resolution
    Limitations
    Setting Time Scale/Resolution of Verilog or VHDL Kernel
    Setting Time Scale/Resolution of SystemC Kernel
    Adding a Main Routine for Verilog-On-Top Designs
    SNPS_REGISTER_SC_MAIN
    SystemC Designs Containing Verilog and VHDL Modules
    Usage Model
    Input Files Required
    Generating a SystemC Wrapper for Verilog Modules
    Generating A SystemC Wrapper for VHDL Design
    Example
    Elaboration Scheme
    SNPS_REGISTER_SC_MODULE
    VHDL Design Containing Verilog/VHDL Modules and SystemC Leaf Modules
    Usage Model
    Input Files Required
    Generating a Verilog/VHDL Wrapper for SystemC Modules
    Example
    Use Model
    SystemC Only Designs
    Usage Model
    Restrictions
    Supported and Unsupported UCLI/DVE and CBug Features
    Controlling TimeScale Resolution
    Setting Timescale of SystemC Kernel
    Automatic Adjustment of Time Resolution
    Considerations for Export DPI Tasks
    Use syscan -export_DPI [function-name]
    Use syscan -export_DPI [Verilog-file]
    Use a Stubs File
    Using options -Mlib and -Mdir
    Specifying Runtime Options to the SystemC Simulation
    Using a Port Mapping File
    Automatic Creation of Portmap File
    Using a Data Type Mapping File
    Combining SystemC with Verilog Configurations
    Verilog-on-Top, SystemC and/or VHDL Down
    Compiling a Verilog/SystemC Design
    Compiling a Verilog/SystemC+VHDL Design
    SystemC-on-Top, Verilog and/or VHDL Down
    Compiling a SystemC/Verilog Design
    Compiling a SystemC/Verilog+VHDL Design
    Limitations
    Parameters
    Parameters in Verilog
    Parameters in VHDL
    Parameters in SystemC
    Verilog-on-Top, SystemC-Down
    VHDL-on-Top, SystemC-down
    SystemC-on-Top, Verilog or VHDL down
    Namespace
    Parameter Specification as VCS Elaboration Arguments
    Debug
    Limitations
    Debugging Mixed Simulations Using DVE or UCLI
    Transaction Level Interface
    Interface Definition File
    Generation of the TLI Adapters
    Transaction Debug Output
    Instantiation and Binding
    Supported Data Types of Formal Arguments
    Miscellaneous
    Delta-Cycles
    Using a Customized SystemC Installation
    Compatibility with OSCI SystemC
    Compiling Source Files
    Limitations
    Using Posix Threads or Quickthreads
    VCS Extensions to SystemC Library
    Installing VG GNU Package
    Support for SystemC 2.3
    Static and Dynamic Linking
    Static Linking in VCS MX
    Dynamic Linking in VCS MX (For C/C++ Files)
    Dynamic Linking in VCS MX (For SystemC Files)
    LD_LIBRARY_PATH Environment Variable
    Limitations
    Verilog wrapper needed for pure VHDL-top-SystemC down
    Incremental Compile of SystemC Source Files
    Full Build from Scratch
    Full Incremental Build
    Partial Build with Object Files
    Partial Build with Shared Libraries
    Updating the Shared Library
    Using Different Libraries
    Partial Build Invoked with VCS
    Partial Build if Just One Shared Library is Updated
    Adding or Deleting SC Source Files in Shared Library
    Changing From a Shared Library Back to Object Files
    Dependency Checking of SystemC Source Files
    Default Setting
    Example
    VCS Command
    Check Dependency at Elaboration
    Check Dependency at Incremental Compile (vcs –sysc=incr)
    Option –sysc=dep Applies to all libs
    Selecting Specific libs
    Example
    VCS Command
    Check Dependency at Elaboration
    Check Dependency at Incremental Compile (vcs –sysc=incr)
    Option –sysc=nodep Applies to all libs, Except csrc
    Example
    VCS Command
    Check Dependency at Elaboration
    Check Dependency at Incremental Compile (vcs –sysc=incr)
    TLI Direct Access
    Accessing SystemC Members from SystemVerilog
    TLI Adaptor
    Instantiating the TLI adaptor in SV
    Direct Variable Access
    Calling SystemC Member Function
    Example
    Arguments of Type char* Used in Blocking Member Functions
    Example
    Supported Data Types
    Basic Types
    SystemC char* Type
    Example
    SystemC Channel Types
    Example
    Arrays
    Example
    SC_FIFO
    Example
    Non-SystemC Classes
    Sub-classes
    Example
    Example
    Name Clashes
    var Name Clashes
    var Name Clashes with Method Names
    Error Handling
    Locating SystemC Instance
    Out-of-array Accesses
    Compile Flow
    Syntax of TLI File
    Rules for TLI File/Syntax
    Example
    Debug Flow
    Accessing Struct or Class Members of a SystemC Module from SystemVerilog
    Enhancements to TLI for Providing Access to SystemC/ C++ Class Members from SystemVerilog
    Accessing Struct or Class Members of a SystemC Module Object from SystemVerilog
    Example
    Generating Adaptor Code
    Accessing Generic C++ Struct or Class
    C++ Functions TLI_UNREGISTER_ID() and TLI_REGISTER_ID()
    SystemVerilog Function attach_by_id()
    SystemVerilog set or get function
    Example
    Extensions of TLI Input File
    Invoking Pack or Unpack Adaptor Code Generation
    Limitations
    Accessing Verilog Variables from SystemC
    Usage Model
    Access Functions
    Supported Data Types
    Unsupported Data Types
    Usage Example
    Type Conversion Mechanism
    Accessing SystemVerilog Functions and Tasks from SystemC
    Introduction
    Usage Model
    Function Declaration Hierarchy
    Passing Arguments
    Supported Types
    Usage Example
    Compile Flow
    Usage Guidelines
    Limitations
    Accessing SystemC Members from SystemVerilog Using the tli_get_ or tli_set_ Functions
    Using the tli_get_ and tli_set_ Functions
    Prototypes of tli_get_ and tli_set_ Functions
    Supported Data Types
    Sub-Members
    Unsupported Data Types
    Member Variables
    Example
    Type Conversion Mechanism
    Compile Flow
    Using tli_D Option
    Example
    Modifying SystemC Code
    Example
    Modifying SystemVerilog Code
    Example
    TLI Directive (create directaccess)
    Generating C++ Struct Definition from SystemVerilog Class Definition
    Use Model for Generating C++ Struct from SystemVerilog Class
    Data Type Conversion from SystemVerilog to C++
    Example for Generating C++ Struct from SystemVerilog Class
    Limitations
    Supporting Designs with Donut Topologies
    Example
    Exchanging Data Between SystemVerilog and SystemC Using Byte Pack/Unpack
    Use Model
    Supported Data Types
    Unsupported Data Types
    Mapping of SystemC/C++ and SystemVerilog/VMM Data Types
    Usage Examples
    Using the Pack Operator
    Using Unpack Operator
    Using Pack and Unpack Functions
    Using Code Generator
    Naming Convention
    Input Files
    TLI File
    C source file containing the struct or class
    Output Files
    Generated SV class
    Generated C files
    Supported Data types for Automatic Code Generation
    Correcting the Generated Files
    Compile Flow
    Usage Example for Code Generator
    Code Generation
    Manual Modifications
    SystemC Module Using Byte Packing
    Verilog Module Using Byte Packing
    Building Simulation
    Using Direct Program Interface Based Communication
    Example
    Limitations of Using DPI-based Communication Between Verilog and SystemC
    Using OPT Interface-Based Communication
    OPT Interface-Based Communication Limitations
    Improving VCS-SystemC Compilation Speed Using Precompiled C++ Headers
    Introduction to Precompiled Header Files
    Using Precompiled Header Files
    Example to Use the Precompiled Header Files
    Example
    Invoking the Creation of Precompiled Header Files
    Limitations
    Limitations of GNU Precompiled Header Files
    Limitations of syscan -prec
    Limitations of using -prec with path
    Limitations of Sharing Precompiled Header Files
    Increasing Stack and Stack Guard Size
    Increasing the Stack Size
    Example
    Increasing the Stack Guard Size
    Example
    Guidelines to Diagnose Stack Overrun
    Debugging SystemC Runtime Errors
    Debugging SystemC Kernel Errors
    Troubleshooting Your Elaboration Errors
    Example
    Troubleshooting Your Runtime Errors
    Function cbug_stop_here()
    Limitations
    Diagnosing Quickthread Issues
    Using HDL and SystemC Sync Loops
    The Coarse-Grained Sync Loop (blocksync)
    The Fine-Grained Sync Loop (deltasync)
    Run Time
    Alignment of Delta Cycles
    Example Syntax
    Restrictions
    Restrictions That No Longer Apply
    Newsync is Now Default
    Advantages of deltasync Loop
    Simulation Differences Between blocksync and deltasync Loop
    Scenario 1 - Mismatched Time Resolution
    Scenario 2 - Differences During Initialization Phase of the Simulation
    Scenario 3 - Race Conditions Between Delta Cycles and Domains
    Scenario 4 - Differences When the Simulation Ends
    Scenario 5 - Different Execution Order of Concurrent Delta Cycles / NBA Queues
    Controlling Simulation Run From sc_main
    Example
    Effect on end_of_simulation Callbacks
    Enabling E115 Check in VCS Co-Simulation Interface
    UCLI Save Restore Support for SystemC-on-top and Pure-SystemC
    SystemC with UCLI Save and Restore Use Model
    SystemC with UCLI Save and Restore Coding Guidelines
    Saving and Restoring Files During Save and Restore
    Restoring the Saved Files from the Previous Saved Session
    Limitations of UCLI Save Restore Support
    Enabling Unified Hierarchy for VCS and SystemC
    Using Unified Hierarchy Elaboration
    Value Added by Option –sysc=unihier
    Using the –sysc=show_sc_main Switch
    SystemC Unified Hierarchy Flow Limitations
    Aligning VMM and SystemC Messages
    Introduction
    Use Model
    Changing Message Alignment Settings
    Mapping SystemC to VMM Severities
    Filtering Messages
    Limitations
    UVM Message Alignment
    Enabling UVM Message Alignment
    Accessing UVM Report Object of SystemC Instance
    Introducing TLI Adapters
    TLI Adapter Overview
    SystemC Adapters
    Global Package
    Global Package APIs
    User Package
    User Package for VMM Channel Interface
    User Package for VMM TLM Interface
    Use Model
    VMM Channel Interface (vmm_tlm_generic_payload)
    VMM TLM Interface (vmm_tlm_generic_payload)
    VMM Channel/TLM Interface (Other data type)
    SV Interface Other Than vmm_channel/vmm_tlm
    VMM Channel Interface Details
    Bind Function
    Conversion Functions
    Processes
    VMM TLM Interface Details
    Bind Function
    Conversion Functions
    Processes
    Target Class
    Non-Blocking Extended Class
    Examples
    Example-1
    SV Producer Channel Connected to SC OSCI TLM2.0 LT Consumer
    Example-2
    SV Producer Channel Connected to SC OSCI TLM2.0 AT Consumer
    Example-3
    SV Producer VMM_TLM (Blocking Interface) Connected to SC OSCI TLM2.0 LT Consumer
    Example-4
    SV Producer VMM_TLM (Non-Blocking Interface) Connected to SC OSCI TLM2.0 AT Consumer
    Example-5
    SC Producer OSCI TLM2.0 LT Connected to SV Channel Consumer
    Example-6
    SC Producer OSCI TLM2.0 AT Initiator Connected to SV Channel Consumer
    Example-7
    SC Producer OSCI TLM2.0 LT Connected to SV VMM-TLM (Blocking Interface) Consumer
    Example-8
    SC Producer OSCI TLM2.0 AT Initiator Connected to SV VMM- TLM (Non-Blocking Interface) Consumer
    Example-9
    SV Producer VMM-TLM (Analysis Port) Connected to SC OSCI TLM2.0 Subscriber
    Example-10
    SC Producer OSCI TLM2.0 Analysis Parent Connected to SV VMM-TLM Analysis Subscriber
    Using VCS UVM TLI Adapters
    Using the UVM TLI Adapters
    UVM TLM Interface
    UVM Analysis Interface
    Handling Multiple Subscribers
    UVM TLM Communication Examples
    uvm_tlm_blocking Example
    uvm_tlm_nonblocking Example
    uvm_tlm_analysis Example
    Modeling SystemC Designs with SCV
    SCV Library in VCS
    Use Model
    msglog Extensions for Transaction Recording with SCV in VCS
    Use Model
    Viewing SystemC sc_report_handler Messages from Log File
    Generating Profile Reports for SystemC Designs
    Time Profiling
    Enabling Time Profiling at Compile-time
    Using Time Profiling at Runtime
    Memory Profiling
    Enabling Memory Profiling at Compile-time
    Using Memory Profiling at Runtime
    Profiler Example
    Profile Report Limitations
    C Language Interface
    Using PLI
    Writing a PLI Application
    Functions in a PLI Application
    Header Files for PLI Applications
    PLI Table File
    Syntax
    Specifying Access Capabilities for PLI Functions
    Specifying Access Capabilities for VCS MX Debugging Features
    Using the PLI Table File
    Enabling ACC Capabilities
    Globally
    Using the Configuration File
    Selected ACC Capabilities
    Learning What Access Capabilities are Used
    Compiling to Enable Only the Access Capabilities You Need
    Limitations
    PLI Access to Ports of Celldefine and Library Modules
    Example
    Visualization in DVE
    Limitations
    Using VPI Routines
    Support for VPI Callbacks for Reasons cbForce and cbRelease
    Support for the vpi_register_systf Routine
    Integrating a VPI Application With VCS MX
    PLI Table File for VPI Routines
    Virtual Interface Debug Support
    Example
    Limitations
    Unimplemented VPI Routines
    Using VHPI Routines
    Diagnostics for VPI/VHPI PLI Applications
    Using DirectC
    Using Direct C/C++ Function Calls
    How C/C++ Functions Work in a Verilog Environment
    Declaring the C/C++ Function
    Calling the C/C++ Function
    Storing Vector Values in Machine Memory
    Converting Strings
    Avoiding a Naming Problem
    Using Pass by Reference
    Using Direct Access
    Using the vc_hdrs.h File
    Access Routines for Multi-Dimensional Arrays
    UB *vc_arrayElemRef(UB*, U, ...)
    U vc_getSize(UB*,U)
    Using Abstract Access
    Using vc_handle
    Using Access Routines
    int vc_isScalar(vc_handle)
    int vc_isVector(vc_handle)
    int vc_isMemory(vc_handle)
    int vc_is4state(vc_handle)
    int vc_is2state(vc_handle)
    int vc_is4stVector(vc_handle)
    int vc_is2stVector(vc_handle)
    int vc_width(vc_handle)
    int vc_arraySize(vc_handle)
    scalar vc_getScalar(vc_handle)
    void vc_putScalar(vc_handle, scalar)
    char vc_toChar(vc_handle)
    int vc_toInteger(vc_handle)
    char *vc_toString(vc_handle)
    char *vc_toStringF(vc_handle, char)
    void vc_putReal(vc_handle, double)
    double vc_getReal(vc_handle)
    void vc_putValue(vc_handle, char *)
    void vc_putValueF(vc_handle, char *, char )
    void vc_putPointer(vc_handle, void*) void *vc_getPointer(vc_handle)
    void vc_StringToVector(char *, vc_handle)
    void vc_VectorToString(vc_handle, char *)
    int vc_getInteger(vc_handle)
    void vc_putInteger(vc_handle, int)
    vec32 *vc_4stVectorRef(vc_handle)
    U *vc_2stVectorRef(vc_handle)
    void vc_get4stVector(vc_handle, vec32 *) void vc_put4stVector(vc_handle, vec32 *)
    void vc_get2stVector(vc_handle, U *) void vc_put2stVector(vc_handle, U *)
    UB *vc_MemoryRef(vc_handle)
    UB *vc_MemoryElemRef(vc_handle, U indx)
    scalar vc_getMemoryScalar(vc_handle, U indx)
    void vc_putMemoryScalar(vc_handle, U indx, scalar)
    int vc_getMemoryInteger(vc_handle, U indx)
    void vc_putMemoryInteger(vc_handle, U indx, int)
    void vc_get4stMemoryVector(vc_handle, U indx, vec32 *)
    void vc_put4stMemoryVector(vc_handle, U indx, vec32 *)
    void vc_get2stMemoryVector(vc_handle, U indx, U *)
    void vc_put2stMemoryVector(vc_handle, U indx, U *)
    void vc_putMemoryValue(vc_handle, U indx, char *)
    void vc_putMemoryValueF(vc_handle, U indx, char, char *)
    char *vc_MemoryString(vc_handle, U indx)
    char *vc_MemoryStringF(vc_handle, U indx, char)
    void vc_FillWithScalar(vc_handle, scalar)
    char *vc_argInfo(vc_handle)
    int vc_Index(vc_handle, U, ...)
    U vc_mdaSize(vc_handle, U)
    Summary of Access Routines
    Enabling C/C++ Functions
    Mixing Direct And Abstract Access
    Specifying the DirectC.h File
    Extended BNF for External Function Declarations
    VHDL 2002 and 2008 Support
    VHDL 2002 Protected Type
    Use Model
    Limitations of VHDL 2002 Protected Type
    VHDL 2008 Constructs
    New Data Types and Operators
    C-style Comments
    New Use Clause and Aliases
    Standard Environment Package
    External Names Support
    The all Keyword in the Process Sensitivity List
    Use Model for VHDL 2008 Constructs
    SAIF Support
    Using SAIF Files with VCS MX
    SAIF System Tasks for Verilog or Verilog-Top Designs
    The Flows to Generate a Backward SAIF File
    Generating an SDPD Backward SAIF File
    Generating a Non-SPDP Backward SAIF File
    SAIF Calls That Can Be Used on VHDL or VHDL-Top Designs
    SAIF Support for Two-Dimensional Memories in v2k Designs
    UCLI SAIF Dumping
    Criteria for Choosing Signals for SAIF Dumping
    Encrypting Source Files
    IEEE Verilog Standard 1364-2005 Encryption
    The Protection Header File
    Unsupported Protection Pragma Expressions
    Other Options for IEEE Std 1364-2005 Encryption Mode
    How Protection Envelopes Work
    The VCS MX Public Encryption Key
    Creating Interoperable Digital Envelopes Using VCS MX - Example
    Discontinued -ipkey Option
    IEEE VHDL Standard 1076-2008 Encryption
    VHDL 1076-2008 Encryption Use Model
    Encrypting the Entire VHDL Source Files
    Encrypting the Parts of VHDL Source Files
    Using the Protection Header File
    Options for VHDL 1076-2008 Encryption Mode
    Protection Envelopes
    The VCS MX Public Encryption Key
    Usage Example
    Example for Full Encryption
    Perform the following commands:
    Example for Partial Encryption
    Perform the following commands:
    Debug Protection
    Combining Encrypted and Unencrypted Code
    Entirely-Encrypted or Unencrypted Source Files
    Partially-Encrypted Source Files
    Assertion and Report Statements
    Hierarchy Attributes
    Profiling
    VHPI
    VPD / VCD
    Coverage
    Error Messages
    Limitations
    128-bit Advanced Encryption Standard
    Compiler Directives for Source Protection
    Using Compiler Directives or Pragmas
    -protect128
    Example
    -putprotect128
    Automatic Protection Options
    Using Automatic Protection Options
    -autoprotect128
    -auto2protect128
    -auto3protect128
    +protect option
    +putprotect+
    +autoprotect[file_suffix]
    +auto2protect[file_suffix]
    +auto3protect[file_suffix]
    +deleteprotected
    +pli_unprotected
    Debugging Partially Encrypted Source Code
    gen_vcs_ip
    Syntax
    Analysis Options
    Exporting The IP
    Use Model
    IP Vendor
    IP Generation
    IP User
    Licensing
    Integrating VCS MX with Vera
    Setting Up Vera and VCS MX
    Using Vera with VCS MX
    Usage Model
    VCS MX and CustomSim Cosimulation
    Introduction to VCS MX and CustomSim
    Analyzing a Design
    Elaborating a Design
    Running the Simulation
    Setting up the Environment
    Licenses
    Required UNIX Paths and Variable Settings
    Use Model
    Example
    Integrating VCS MX with Specman
    Type Support
    Usage Flow
    Setting Up The Environment
    Specman e code accessing VHDL only
    Specman e Code Accessing Verilog Only
    e code accessing both VHDL and Verilog
    Guidelines for Specifying HDL Path or Tick Access with VCS MX-Specman Interface
    Using specrun and specview
    Adding Specman Objects To DVE
    Version Checker for Specman
    Use Model
    Precedence Order
    Integrating VCS MX with Denali
    Setting Up Denali Environment for VCS MX
    Integrating Denali with VCS MX
    Usage Model
    Usage Model for VHDL Memory Models
    Usage Model for Verilog Memory Models
    Execute Denali Commands at UCLI Prompt
    Integrating VCS MX with Debussy
    Using the Current Version of VCS MX with Novas 2010.07 Version
    Setting Up Debussy
    Usage Model to Dump fsdb File
    Using VHDL Procedures or Verilog System Tasks
    Using UCLI
    Examples
    Integrating VCS with MVSIM Native Mode
    Introduction to MVSIM
    MVSIM Native Mode in VCS
    References
    Migrating to VCS MX
    Step 1: Setting Up The Environment
    Step 2: Analysis
    Step 3: Elaboration
    Step 4: Simulation
    Simulation Executable
    User Interface Commands
    Simulation Results
    Coding Style
    LRM Extensions
    VCS MX Environment Variables
    Setup Variables
    Analysis Setup Variables
    Compilation/Elaboration Setup Variables
    Simulation Setup Variables
    C Compilation and Linking Setup Variables
    New Timescale Implementation
    Understanding `timescale
    Scenario 1:
    Scenario 2:
    Scenario 3:
    Verilog only and Verilog Top Mixed Design
    VHDL only and VHDL Top Mixed Designs
    Setting up Simulator Resolution From Command Line
    Other Useful Timescale Related Switches
    Non compatible switches
    Limitations
    Optional Environment Variables
    Analysis Utilities
    The vhdlan Utility
    Using Smart Order
    Use Model
    Syntax:
    Example:
    Syntax:
    Example:
    Limitations
    The vlogan Utility
    Elaboration Options
    Options for Incremental Compilation
    Options for Help and Documentation
    Option for SystemVerilog
    Options for SystemVerilog Assertions
    Options to Enable Compilation of OVA Case Pragmas
    Options for Native Testbench
    Option for Initializing Memories and Registers with Random Values
    Option for Specifying Initial Values for Parts of the Design or Testbench
    Options for Using Radiant Technology
    Options for Starting Simulation Right After Compilation
    Options for Specifying Delays and SDF Files
    Options for Compiling an SDF File
    Options for Specify Blocks and Timing Checks
    Options for Pulse Filtering
    Options for Negative Timing Checks
    Options for Profiling Your Design
    Option to Specify Elaboration Options in a File
    Limitations of -file option
    Options for Compiling Runtime Options into the Executable
    Options for PLI Applications
    Options to Enable the VCS MX DirectC Interface
    Options for Flushing Certain Output Text File Buffers
    Options for Controlling Messages
    Options for Cell Definition
    Options for Licensing
    Options for Controlling the Linker
    Options for Controlling the C Compiler
    Options for Source Protection
    Options for Mixed Analog/Digital Simulation
    Unified Option to Change Generic and Parameter Values
    Checking for X and Z Values in Conditional Expressions
    Options for Detecting Race Conditions
    Options to Specify the Time Scale
    Options for Overriding Parameters
    Option to Enable Bounds Check in VHDL
    General Options
    Enable the VCS MX/SystemC Cosimulation Interface
    TetraMAX
    Suppressing Port Coersion to inout
    Allow Inout Port Connection Width Mismatches
    Allow Zero or Negative Multiconcat Multiplier
    Specifying a VCD File
    Enabling Dumping
    Enabling Identifier Search
    Memories and Multi-Dimensional Arrays (MDAs)
    Specifying a Log File
    Changing Source File Identifiers to Upper Case
    Specifying the Name of the Executable File
    Returning The Platform Directory Name
    Maximum Donut Layers for a Mixed HDL Design
    Enabling feature beyond VHDL LRM
    Enable Loop Detect
    Changing the Time Slot of Sequential UDP Output Evaluation
    Gate-Level Performance
    Option to Omit Compilation of Code Between Pragmas
    Generating a List of Source Files
    Simulation Options
    Options for Simulating Native Testbenches
    Options for SystemVerilog Assertions
    Options to Control Termination of Simulation
    Options for Enabling and Disabling Specify Blocks
    Options for Specifying When Simulation Stops
    Options for Recording Output
    Options for Controlling Messages
    Options for VPD Files
    Options for VCD Files
    Options for Specifying Delays
    Options for Flushing Certain Output Text File Buffers
    Options for Licensing
    Option to Specify User-Defined Runtime Options in a File
    Option for Initializing Integer Data Type Variables at Runtime
    Option for Changing or Specifying Initial Values for Parts of the Design or Testbench
    General Options
    Viewing the Compile-Time Options
    Recording Where ACC Capabilities are Used
    Suppressing the $stop System Task
    Enabling User-defined Plusarg Options
    Enabling feature beyond VHDL LRM
    Specifying acc_handle_simulated_net PLI Routine
    Loading DPI Libraries Dynamically at Rutime
    Loading PLI Libraries Dynamically at Runtime
    Verilog Compiler Directives and System Tasks
    Compiler Directives
    Compiler Directives for Cell Definition
    Compiler Directives for Setting Defaults
    Compiler Directives for Macros
    Compiler Directives for Delays
    Compiler Directives for Backannotating SDF Delay Values
    Compiler Directives for Source Protection
    General Compiler Directives
    Compiler Directive for Including a Source File
    Compiler Directive for Setting the Time Scale
    Compiler Directive for Specifying a Library
    Compiler Directive for File Names and Line Numbers
    Unimplemented Compiler Directives
    System Tasks and Functions
    System Tasks for SystemVerilog Assertions Severity
    System Tasks for SystemVerilog Assertions Control
    System Tasks for SystemVerilog Assertions
    System Tasks for VCD Files
    System Tasks for LSI Certification VCD and EVCD Files
    System Tasks for VPD Files
    System Tasks for SystemVerilog Assertions
    System Tasks for Executing Operating System Commands
    System Tasks for Log Files
    System Tasks for Data Type Conversions
    System Tasks for Displaying Information
    System Tasks for File I/O
    System Tasks for Loading Memories
    System Tasks for Time Scale
    System Tasks for Simulation Control
    System Tasks for Timing Checks
    Timing Checks for Clock and Control Signals
    System Tasks for PLA Modeling
    System Tasks for Stochastic Analysis
    System Tasks for Simulation Time
    System Tasks for Probabilistic Distribution
    System Tasks for Resetting VCS MX
    General System Tasks and Functions
    Checks for a Plusarg
    SDF Files
    Counting the Drivers on a Net
    Depositing Values
    Fast Processing Stimulus Patterns
    Saving and Restarting The Simulation State
    Checking for X and Z Values in Conditional Expressions
    Calculating Bus Widths
    Displaying the Method Stack
    IEEE Standard System Tasks Not Yet Implemented
    Index
    Symbols
    A
    B
    C
    D
    E
    F
    G
    H
    I
    J
    K
    L
    M
    N
    O
    P
    Q
    R
    S
    T
    U
    V
    W
    X
    Y
    Z
    VCS® MX/VCS MXi™ User Guide I-2014.03 March 2014 Comments? E-mail your comments about this manual to: vcs_support@synopsys.com.
    Copyright Notice and Proprietary Information © 2014 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at http://www.synopsys.com/Company/Pages/Trademarks.aspx. All other product or company names may be trademarks of their respective owners. Third-Party Links Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content. Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 www.synopsys.com ii
    Contents 1. Getting Started Simulator Support with Technologies . . . . . . . . . . . . . . . . . . . . . Setting Up the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying Your System Configuration . . . . . . . . . . . . . . . . . . . Obtaining a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up Your Environment. . . . . . . . . . . . . . . . . . . . . . . . . Setting Up Your C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . Creating a synopsys_sim.setup File . . . . . . . . . . . . . . . . . . . The Concept of a Library In VCS MX. . . . . . . . . . . . . . . . Library Name Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . Including Other Setup Files . . . . . . . . . . . . . . . . . . . . . . . Using SYNOPSYS_SIM_SETUP Environment Variable . Displaying Setup Information. . . . . . . . . . . . . . . . . . . . . . . . . Displaying Design Information Analyzed Into a Library . . . . . Using the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Time Unit and Time Precision . . . . . . . . . . . . . . . . . . . . . 1-2 1-5 1-5 1-6 1-8 1-9 1-9 1-11 1-12 1-13 1-13 1-14 1-15 1-17 1-18 1-19 iii
    Searching Identifiers in the Design Using UNIX Commands . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1-22 2. VCS MX Flow Three-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using vhdlan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using vlogan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Design to Different Libraries . . . . . . . . . . . Elaboration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using vcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interactive Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commonly Used Runtime Options. . . . . . . . . . . . . . . . . . Two-step Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using vcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interactive Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commonly Used Runtime Options. . . . . . . . . . . . . . . . . . 3. Elaborating the Design Compiling or Elaborating the Design in Debug Mode . . . . . . . . . Compiling or Elaborating the Design in Optimized Mode . . . . . . Dynamic Loading of DPI Libraries at Runtime . . . . . . . . . . . . . . 2-2 2-2 2-4 2-7 2-14 2-15 2-16 2-19 2-19 2-20 2-20 2-22 2-22 2-23 2-27 2-28 2-28 2-29 3-1 3-2 3-3 iv
    The Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Loading of PLI Libraries at Runtime . . . . . . . . . . . . . . . Key Elaboration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initializing Verilog Memories and Registers . . . . . . . . . . . . . . Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-5 3-6 3-6 3-8 Initializing Verilog Variables, Memories, and MDAs in Parts of the 3-9 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing or Adding Initialized Parts of the Design at Runtime 3-12 Dumping Initialized Values in a File . . . . . . . . . . . . . . . . . Restricting +vcs+initreg Initialization to Either Registers or Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overriding Generics and Parameters . . . . . . . . . . . . . . . . . . Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking for X and Z Values In Conditional Expressions . . . Enabling the Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . Filtering Out False Negatives. . . . . . . . . . . . . . . . . . . . . . Cross Module References (XMRs) . . . . . . . . . . . . . . . . . . . . hdl_xmr Procedure and $hdl_xmr System Task. . . . . . . . Data Types Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Referencing Verilog using hdl_xmr procedure. . . . Verilog Referencing VHDL objects using $hdl_xmr . . . . . Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $hdl_xmr Support for VHDL Variables . . . . . . . . . . . . . . . Datatype Support and Usage Examples . . . . . . . . . . . . . VCS MX V2K Configurations and Libmaps . . . . . . . . . . . . . . Library Mapping Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-13 3-14 3-15 3-16 3-17 3-18 3-20 3-20 3-21 3-22 3-24 3-25 3-26 3-27 3-31 3-32 3-33 v
    Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the -liblist Option . . . . . . . . . . . . . . . . . . . . . . . . . . Design Cells and Library Cells . . . . . . . . . . . . . . . . . . . . . Library Search Order Rules . . . . . . . . . . . . . . . . . . . . . . . Example Testcase Files . . . . . . . . . . . . . . . . . . . . . . . . . . Usage Examples for Library Search Order Rules for Verilog or 3-37 3-37 3-42 3-45 3-47 3-55 SystemVerilog Designs. . . . . . . . . . . . . . . . . . . . . . . . 3-57 Usage Examples for Library Search Order Rules for Verilog or SystemVerilog Designs Without Configuration File . . Lint Warning Message for Missing ‘endcelldefine . . . . . . . . . Error/Warning/Lint Message Control . . . . . . . . . . . . . . . . . . . 3-74 3-78 3-82 Controlling Error/Warning/Lint Messages Using Compile-Time Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 Controlling Error/Warning/Lint Messages Using a Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extracting the Files Used in Elaboration . . . . . . . . . . . . . . . . XML File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99 3-107 3-108 3-113 4. Simulating the Design Using DVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using UCLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ucli2Proc Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Options for Debugging Using DVE and UCLI . . . . . . . . . . . . . . . Reporting Forces/Injections in a Simulation . . . . . . . . . . . . . . . . Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting Force/Deposit/Release Information. . . . . . . . . . . . 4-2 4-3 4-5 4-6 4-8 4-8 4-10 vi
    Handling Forces on Bit/Part Select and MDA Word. . . . . Handling Forces on Concatenated Codes . . . . . . . . . . . . Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Runtime Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overriding Generics at Runtime. . . . . . . . . . . . . . . . . . . . . . . Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Passing Values from the Runtime Command Line . . . . . . . . VCS MX Supports simv -f . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying a Long Time Before Stopping The Simulation . . . 5. The Unified Simulation Profiler The Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Omitting Profiling at Runtime . . . . . . . . . . . . . . . . . . . . . . . . . Omitting the -simprofile Runtime Option . . . . . . . . . . . . . . . . Omitting Profile Report Writing after Runtime . . . . . . . . . . . . Specifying a Directory for the Profile Database . . . . . . . . . . . Post Simulation Profile Information . . . . . . . . . . . . . . . . . . . . . . . Specifying the Name of the Profile Report. . . . . . . . . . . . . . . Running the profrpt Profile Report Generator . . . . . . . . . . . . . . . Specifying Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Snapshot Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Timeline Reports . . . . . . . . . . . . . . . . . . . . . . . . . Recording and Viewing Memory Stack Traces . . . . . . . . . . . 4-11 4-12 4-12 4-16 4-18 4-20 4-21 4-21 4-25 4-26 4-26 4-27 5-2 5-4 5-5 5-6 5-6 5-7 5-7 5-8 5-10 5-13 5-14 5-15 vii
    Reporting PLI, DPI, and DirectC Function Call Information. . Compiling and Running the Profiler Example. . . . . . . . . . Profiling Time Used by Various Parts of the Design. . . . . Profiling Memory Used by Various Parts of the Design . . The Output Directories and Files . . . . . . . . . . . . . . . . . . . . . . The Enhanced Accumulative Views. . . . . . . . . . . . . . . . . . . . The Comparative View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Caller-Callee Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . HTML Profiler Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hypertext Links to the Source Files . . . . . . . . . . . . . . . . . . . . Single Text Format Report . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Trace Report Example . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constraint Profiling Integrated in the Unified Profiler . . . . . . . . . Changes to the Use Model for Constraint Profiling . . . . . . . . The Time Constraint Solver View. . . . . . . . . . . . . . . . . . . . . . The Memory Constraint Solver View . . . . . . . . . . . . . . . . . . . Performance/Memory Profiling for Coverage Covergroups. . . . . Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HTML Profiler Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Summary View. . . . . . . . . . . . . . . . . . . . . . . . . . . Time/Memory Summary View . . . . . . . . . . . . . . . . . . . . . Time/Memory Module View . . . . . . . . . . . . . . . . . . . . . . . Time/Memory Construct View . . . . . . . . . . . . . . . . . . . . . Time/Memory Covergroup View. . . . . . . . . . . . . . . . . . . . 5-15 5-16 5-18 5-19 5-20 5-21 5-28 5-30 5-36 5-64 5-68 5-68 5-71 5-79 5-79 5-81 5-89 5-93 5-94 5-94 5-95 5-95 5-96 5-96 5-97 5-99 viii
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