logo资料库

MC9S12EXP100.pdf

第1页 / 共1328页
第2页 / 共1328页
第3页 / 共1328页
第4页 / 共1328页
第5页 / 共1328页
第6页 / 共1328页
第7页 / 共1328页
第8页 / 共1328页
资料共1328页,剩余部分请下载后查看
查询"MC9S12XEP100RMV1"供应商 HCS12XMicrocontrollersfreescale.comBecause of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010MC9S12XEP100Reference ManualCoversMC9S12XEFamilyMC9S12XEP100RMV1Rev. 1.2309/2010
查询"MC9S12XEP100RMV1"供应商 To provide the most up-to-date information, the document revision on the World Wide Web is the mostcurrent. A printed copy may be an earlier revision. To verif, refer to: http://freescale.com/ThisdocumentcontainsinformationforthecompleteS12XE-FamilyandthusincludesasetofseparateFTM module sections to cover the whole family. A full list of family members and options is included inthe appendices.Thisdocumentcontainsinformationforallconstituentmodules,withtheexceptionoftheS12XCPU.ForS12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual.BecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010Revision HistoryDateRevisionDescriptionMay,20081.16FigureB-3Θ1 value corrected.Added LVR minimum assert levelEnhanced RESET pin description.IIC register name correctedCorrected D-Flash size reference for XEG128Changed module revision history tables to a unified formatCorrected corrupted formatsJul, 20081.17Added Module Run Idd ValuesAdded 3.3V expansion bus timingCorrected NVM timing parametersChanged IIC SCL Divider noteSep, 20081.18Updated NVM timing parameter section for brownout caseSpecified time delay from RESET to start of CPU code executionAdded NVM patch Part IDsEnhanced ECT GPIO / timer function transitioning descriptionDec, 20081.19Updated 208MAPBGA thermal parametersRevised TIM flag clearing procedureCorrected CRG register addressAdded maskset identifier suffix for ATMC fabFixed typosAug, 20091.20Added 208MAPBGA disclaimerAdded VREAPI to PT5. Added LVR Note to electricals.Updates to TIM/ECT/XGATE/SCI/MSCAN (see embedded rev. history)Apr, 20101.21FTM section (see FTM revision history)PIM section (see PIM revision history)May, 20101.22ECT and TIM sections (see ECT, TIM revision history tables)BDM Alternate clock source defined in device overviewSep, 20101.23Added S12XEG256 option. Updated MSCAN section
查询"MC9S12XEP100RMV1"供应商 MC9S12XE-Family Reference Manual , Rev. 1.23Freescale Semiconductor3BecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010Chapter1Device Overview MC9S12XE-Family. . . . . . . . . . . . . . . . . . . . .27Chapter2Port Integration Module (S12XEP100PIMV1). . . . . . . . . . . . . .89Chapter3Memory Mapping Control (S12XMMCV4). . . . . . . . . . . . . . . .187Chapter4Memory Protection Unit (S12XMPUV1) . . . . . . . . . . . . . . . . .227Chapter5External Bus Interface (S12XEBIV4). . . . . . . . . . . . . . . . . . . .241Chapter6Interrupt (S12XINTV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261Chapter7Background Debug Module (S12XBDMV2). . . . . . . . . . . . . .277Chapter8S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . .303Chapter9Security (S12XE9SECV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . .345Chapter10XGATE (S12XGATEV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351Chapter11S12XE Clocks and Reset Generator (S12XECRGV1). . . . . .467Chapter12Pierce Oscillator (S12XOSCLCPV2). . . . . . . . . . . . . . . . . . . .497Chapter13Analog-to-Digital Converter (ADC12B16CV1) . . . . . . . . . . . .501Chapter14Enhanced Capture Timer (ECT16B8CV3). . . . . . . . . . . . . . . .525Chapter15Inter-Integrated Circuit (IICV3) Block Description. . . . . . . . .577Chapter16Scalable Controller Area Network (S12MSCANV3). . . . . . . .603Chapter17Periodic Interrupt Timer (S12PIT24B8CV2) . . . . . . . . . . . . . .657Chapter18Periodic Interrupt Timer (S12PIT24B4CV2) . . . . . . . . . . . . . .675Chapter19Pulse-Width Modulator (S12PWM8B8CV1). . . . . . . . . . . . . .689Chapter20Serial Communication Interface (S12SCIV5). . . . . . . . . . . . .721Chapter21Serial Peripheral Interface (S12SPIV5). . . . . . . . . . . . . . . . . .759Chapter22Timer Module (TIM16B8CV2) Block Description. . . . . . . . . .785Chapter23Voltage Regulator (S12VREGL3V3V1). . . . . . . . . . . . . . . . . .813Chapter24128 KByte Flash Module (S12XFTM128K2V1) . . . . . . . . . . . .829Chapter25256 KByte Flash Module (S12XFTM256K2V1) . . . . . . . . . . . .889
查询"MC9S12XEP100RMV1"供应商 MC9S12XE-Family Reference Manual , Rev. 1.234Freescale SemiconductorBecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010Chapter26384 KByte Flash Module (S12XFTM384K2V1) . . . . . . . . . . . .951Chapter27512 KByte Flash Module (S12XFTM512K3V1) . . . . . . . . . . .1013Chapter28768 KByte Flash Module (S12XFTM768K4V2) . . . . . . . . . . .1075Chapter291024 KByte Flash Module (S12XFTM1024K5V2) . . . . . . . . .1137AppendixAElectrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .1199AppendixBPackage Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1255AppendixCPCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1260AppendixDDerivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1265AppendixEDetailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . .1268AppendixFOrdering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1319
查询"MC9S12XEP100RMV1"供应商 MC9S12XE-Family Reference Manual Rev. 1.23Freescale Semiconductor5BecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010Blank Page
查询"MC9S12XEP100RMV1"供应商 MC9S12XE-Family Reference Manual , Rev. 1.236Freescale SemiconductorBecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010Blank Page
查询"MC9S12XEP100RMV1"供应商 MC9S12XE-Family Reference Manual , Rev. 1.23Freescale Semiconductor7BecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 2010Chapter1Device Overview MC9S12XE-Family1.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271.1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271.1.2Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311.1.3Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321.1.4Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331.1.5Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341.1.6Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401.1.7Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401.2Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411.2.1Device Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421.2.2Pin Assignment Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .481.2.3Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .621.2.4Power Supply Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .721.3System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .751.4Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .761.4.1Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .761.4.2Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .781.4.3Freeze Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .791.4.4System States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .791.5Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .801.6Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .801.6.1Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .801.6.2Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .801.6.3Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .841.7ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861.7.1External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861.7.2ADC0 Channel[17] Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861.8ADC1 External Trigger Input Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861.9MPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871.10VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871.10.1Temperature Sensor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871.11BDM Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871.12S12XEPIM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .871.13Oscillator Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88Chapter2Port Integration Module (S12XEPIMV1)2.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
查询"MC9S12XEP100RMV1"供应商 MC9S12XE-Family Reference Manual , Rev. 1.238Freescale SemiconductorBecauseofanorderfromtheUnitedStatesInternationalTradeCommission,BGA-packagedproductlinesandpartnumbersindicated here currently are not available from Freescale for import or sale in the United States prior to September 20102.1.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .892.1.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .902.2External Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .902.3Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .982.3.1Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .992.3.2Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1062.3.3Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1082.3.4Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1082.3.5Port A Data Direction Register (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1092.3.6Port B Data Direction Register (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1092.3.7Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1102.3.8Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1112.3.9Port C Data Direction Register (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1112.3.10Port D Data Direction Register (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1122.3.11Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1132.3.12Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1142.3.13S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR). . . . . . . . . . . . . . . . . .1142.3.14S12X_EBI ports Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . .1162.3.15ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1172.3.16PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1182.3.17IRQ Control Register (IRQCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1192.3.18PIM Reserved Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1192.3.19Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1202.3.20Port K Data Direction Register (DDRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1202.3.21Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1212.3.22Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1222.3.23Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1222.3.24Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1232.3.25Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1232.3.26Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1242.3.27PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1242.3.28PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1242.3.29Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1252.3.30Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1262.3.31Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1262.3.32Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1272.3.33Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1282.3.34Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1282.3.35Port S Wired-Or Mode Register (WOMS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1292.3.36PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1292.3.37Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1302.3.38Port M Input Register (PTIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1312.3.39Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1322.3.40Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1342.3.41Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
分享到:
收藏