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EDA for IC Implementation, Circuit Design, and Process Technolog....pdf
Contents
SECTION I: RTL to GDS-II, or Synthesis, Place, and Route
Chapter 1: Design Flows
1.1 Introduction
1.2 Invention
1.3 Implementation
1.4 Integration
1.5 Future Scaling Challenges
1.6 Conclusion
Chapter 2: Logic Synthesis
2.1 Introduction
2.2 Behavioral and Register Transfer-Level Synthesis
2.3 Two-Level Minimization
2.4 Multilevel Logic Minimization
2.5 Enabling Technologies for Logic Synthesis
2.6 Sequential Optimization
2.7 Physical Synthesis
2.8 Multivalued Logic Synthesis
2.9 Summary
Chapter 3: Power Analysis and Optimization from Circuit to Register-Transfer Levels
3.1 Introduction
3.2 Power Analysis
3.3 Circuit-Level Power Optimization
3.4 Logic Synthesis for Low Power
3.5 Conclusion
Chapter 4: Equivalence Checking
4.1 Introduction
4.2 Equivalence Checking Problem
4.3 Boolean Reasoning
4.4 Combinational Equivalence Checking
4.5 Sequential Equivalence Checking
4.6 Summary
Chapter 5: Digital Layout — Placement
5.1 Introduction: Placement Problem and Contexts
5.2 Global Placement
5.3 Detailed Placement and Legalizers
5.4 Placement Trends
5.5 Academic and Industrial Placers
5.6 Conclusions
Chapter 6: Static Timing Analysis
6.1 Introduction
6.2 Representation of Combinational and Sequential Circuits
6.3 Gate Delay Models
6.4 Timing Analysis for Combinational Circuits
6.5 Timing Analysis for Sequential Circuits
6.6 Clocking Disciplines: Edge-Triggered Circuits
6.7 Clocking and Clock-Skew Optimization
6.8 Statistical Static Timing Analysis
6.9 Conclusion
Chapter 7: Structured Digital Design
7.1 Introduction
7.2 Datapaths
7.3 Programmable Logic Arrays
7.4 Memory and Register Files
7.5 Structured Chip Design
7.6 Summary
Chapter 8: Routing
8.1 Introduction
8.2 Types of Routers
8.3 A Brief History of Routing
8.4 Common Routing Algorithms
8.5 Additional Router Considerations
Chapter 9: Exploring Challenges of Libraries for Electronic Design
9.1 Introduction
9.2 What Does It Mean to Design Libraries?
9.3 How Did We Get Here, Anyway?
9.4 Commercial Efforts
9.5 What Makes the Effort Easier?
9.6 The Enemies of Progress
9.7 Environments That Drive Progress
9.8 Libraries and What They Contain
9.9 Summary
Chapter 10: Design Closure
10.1 Introduction
10.2 Current Practice
10.3 The Future of Design Closure
10.4 Conclusion
Chapter 11: Tools for Chip-Package Codesign
11.1 Introduction
11.2 Drivers for Chip-Package Codesign
11.3 Digital System Codesign Issues
11.4 Mixed-Signal Codesign Issues
11.5 I/O Buffer Interface Standard and Other Macromodels
11.6 Conclusions
Chapter 12: Design Databases
12.1 Introduction
12.2 History
12.3 Modern Database Examples
12.4 Fundamental Features
12.5 Advanced Features
12.6 Technology Data
12.7 Library Data and Structures: Design-Data Management
12.8 Interoperability Models
Chapter 13: FPGA Synthesis and Physical Design
13.1 Introduction
13.2 System-Level Tools
13.3 Logic Synthesis
13.4 Physical Design
13.5 Looking Forward
SECTION II: Analog and Mixed-Signal Design
Chapter 14: Simulation of Analog and RF Circuits and Systems
14.1 Introduction
14.2 Differential-Algebraic Equations for Circuits via Modified Nodal Analysis
14.3 Device Models
14.4 Basic Circuit Simulation: DC Analysis
14.5 Steady-State Analysis
14.6 Multitime Analysis
14.7 Noise in RF Design
14.8 Conclusions
Chapter 15: Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits
15.1 Introduction
15.2 Top-Down Mixed-Signal Design Methodology
15.3 Mixed-Signal and Behavioral Simulation
15.4 Analog Behavioral and Power Model Generation Techniques
15.5 Symbolic Analysis of Analog Circuits
15.6 Conclusions
Chapter 16: Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey
16.1 Introduction
16.2 Analog Layout Problems and Approaches
16.3 Analog Cell Layout Strategies
16.4 Mixed-Signal System Layout
16.5 Field-Programmable Analog Arrays
16.6 Conclusions
SECTION III: Physical Verification
Chapter 17: Design Rule Checking
17.1 Introduction
17.2 Geometric Algorithms for Physical Verification
17.3 Hierarchical Data Structures
17.4 Time Complexity of Hierarchical Analysis
17.5 Connectivity Models
17.6 Parallel Computing
17.7 Future Roles for Verification
Chapter 18: Resolution Enhancement Techniques and Mask Data Preparation
18.1 Introduction
18.2 Lithographic Effects
18.3 RET for Smaller k[sub(1)]
18.4 Software Implementations of RET Solutions
18.5 Mask Data Preparation
18.6 Summary
Chapter 19: Design for Manufacturability in the Nanometer Era
19.1 Introduction
19.2 Taxonomy of Yield Loss Mechanisms
19.3 Logic Design for Manufacturing
19.4 Parametric Design for Manufacturing Methodologies
19.5 Design for Manufacturing Integration in the Design Flow: Yield–Aware Physical Synthesis
19.6 Summary
Chapter 20: Design and Analysis of Power Supply Networks
20.1 Introduction
20.2 Voltage-Drop Analysis Modes
20.3 Linear System Solution Techniques
20.4 Models for Power Distribution Networks
20.5 Conclusions
Chapter 21: Noise Considerations in Digital ICs
21.1 Introduction
21.2 Why Has Noise Become a Problem for Digital Chips?
21.3 Noise Effects in Digital Designs
21.4 Static Noise Analysis
21.5 Electrical Analysis
21.6 Fixing Noise Problems
21.7 Summary and Conclusions
Chapter 22: Layout Extraction
22.1 Introduction
22.2 Early History
22.3 Problem Analysis
22.4 System Capabilities
22.5 Converting Drawn Geometries to Actual Geometries
22.6 Designed Device Extraction
22.7 Connectivity Extraction
22.8 Parasitic Resistance Extraction
22.9 Capacitance Extraction Techniques
22.10 Inductance Extraction Techniques
22.11 Network Reduction
22.12 Process Variation
22.13 Conclusions and Future Study
Chapter 23: Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation
23.1 Introduction
23.2 Mechanisms and Effects of Mixed-Signal Noise Coupling
23.3 Modeling of Mixed-Signal Noise Coupling
23.4 Mixed-Signal Noise Measurement and Validation
23.5 Application to Placement and Power Distribution Synthesis
23.6 Summary
SECTION IV: Technology CAD
Chapter 24: Process Simulation
24.1 Introduction
24.2 Process Simulation Methods
24.3 Ion Implantation
24.4 Diffusion
24.5 Oxidation
24.6 Etch and Deposition
24.7 Lithography and Photoresist Modeling
24.8 Silicidation
24.9 Mechanics Modeling
24.10 Putting It All Together
24.11 Conclusions
Chapter 25: Device Modeling — From Physics to Electrical Parameter Extraction
25.1 Introduction
25.2 MOS Technology and Intrinsic Device Modeling
25.3 Parasitic Junction and Inhomogeneous Substrate Effects
25.4 Device Technology Alternatives
25.5 Conclusions
Chapter 26: High-Accuracy Parasitic Extraction
26.1 Introduction
Part I: Extraction via Fast Integral Equation Methods
Part II: Statistical Capacitance Extraction
Index
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
Color Plates
EDA for IC Implementation,
Circuit Design, and
Process Technology
Electronic Design Automation for
Integrated Circuits Handbook
Edited by
Louis Scheffer, Luciano Lavagno,
and Grant Martin
EDA for IC System Design, Verification,
and Testing
EDA for IC Implementation, Circuit Design, and
Process Technology
EDA for IC Implementation,
Circuit Design, and
Process Technology
Edited by
Louis Scheffer
Cadence Design Systems
San Jose, California, U.S.A.
Luciano Lavagno
Cadence Berkeley Laboratories
Berkeley, California, U.S.A.
Grant Martin
Tensilica Inc.
Santa Clara, California, U.S.A.
Published in 2006 by
CRC Press
Taylor & Francis Group
6000 Broken Sound Parkway NW, Suite 300
Boca Raton, FL 33487-2742
© 2006 by Taylor & Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group
No claim to original U.S. Government works
Printed in the United States of America on acid-free paper
10 9 8 7 6 5 4 3 2 1
International Standard Book Number-10: 0-8493-7924-5 (Hardcover)
International Standard Book Number-13: 978-0-8493-7924-6 (Hardcover)
Library of Congress Card Number 2005052941
This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with
permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish
reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials
or for the consequences of their use.
No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or
other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information
storage or retrieval system, without written permission from the publishers.
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Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for
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Library of Congress Cataloging-in-Publication Data
EDA for IC implementation, circuit design, and process technology / editors, Louis Scheffer, Luciano
Lavagno, Grant Martin.
p. cm. -- (Electronic design automation for integrated circuits handbook)
Includes bibliographical references and index.
ISBN 0-8493-7924-5
1. Integrated circuits--Computer-aided design. 2. Integrated circuits--Design and construction. I. Title:
Electronic design automation for integrated circuit implementation, circuit design, and process technology.
II. Scheffer, Louis. III. Lavagno, Luciano, 1959- IV. Martin, Grant (Grant Edmund) V. Series.
TK7874.E257 2005
621.3815--dc22
2005052941
Taylor & Francis Group
is the Academic Division of Informa plc.
Visit the Taylor & Francis Web site at
http://www.taylorandfrancis.com
and the CRC Press Web site at
http://www.crcpress.com
Acknowledgments
and Dedication for the
EDA Handbook
The editors would like to acknowledge the unsung heroes of EDA, those who work to advance the field
in addition to their own personal, corporate, or academic agendas. These men and women serve in a vari-
ety of ways — they run the smaller conferences, they edit technical journals, and they serve on standards
committees, just to name a few. These largely volunteer jobs won’t make anyone rich or famous despite
the time and effort that goes into them, but they do contribute mightily to the remarkable and sustained
advancement of EDA. Our kudos to these folks, who don’t get the credit they deserve.
On a more personal note, Louis Scheffer would like to acknowledge the love, support, encouragement,
and help of his wife Lynde, his daughter Lucynda, and his son Loukos. Without them this project would
not have been possible.
Luciano Lavagno would like to thank his wife Paola and his daughter Alessandra Chiara for making his
life so wonderful.
Grant Martin would like to acknowledge, as always, the love and support of his wife, Margaret Steele,
and his two daughters, Jennifer and Fiona.
Preface
Preface for Volume 2
Electronic Design Automation (EDA) is a spectacular success in the art of engineering. Over the last quar-
ter of a century, improved tools have raised designers’ productivity by a factor of more than a thousand.
Without EDA, Moore’s law would remain a useless curiosity. Not a single billion-transistor chip could be
designed or debugged without these sophisticated tools, so without EDA we would have no laptops, cell
phones, video games, or any of the other electronic devices we take for granted.
But spurred on by the ability to build bigger chips, EDA developers have largely kept pace, and these
enormous chips can still be designed, debugged, and tested,-and in fact, with decreasing time to market.
The story of EDA is much more complex than the progression of integrated circuit (IC) manufactur-
ing, which is based on simple physical scaling of critical dimensions. Instead, EDA evolves by a series of
paradigm shifts. Every chapter in this book, all 49 of them, was just a gleam in some expert’s eye just a
few decades ago. Then it became a research topic, then an academic tool, and then the focus of a startup
or two. Within a few years, it was supported by large commercial EDA vendors, and is now part of the
conventional wisdom. Although users always complain that today’s tools are not quite adequate for
today’s designs, the overall improvements in productivity have been remarkable. After all, in what other
field do people complain of only a 21% compound annual growth in productivity, sustained over three
decades, as did the International Technology Roadmap for Semiconductors in 1999?
And what is the future of EDA tools? As we look at the state of electronics and integrated circuit design
in the 2005–2006 timeframe, we see that we may soon enter a major period of change in the discipline. The
classical scaling approach to integrated circuits, spanning multiple orders of magnitude in the size of devices
over the last 40⫹ years, looks set to last only a few more generations or process nodes (though this has been
argued many times in the past, and has invariably been proved to be too pessimistic a projection).
Conventional transistors and wiring may well be replaced by new nano and biologically-based technologies
that we are currently only beginning to experiment with. This profound change will surely have a consider-
able impact on the tools and methodologies used to design integrated circuits. Should we be spending our
efforts looking at CAD for these future technologies, or continue to improve the tools we currently use?
Upon further consideration, it is clear that the current EDA approaches have a lot of life left in them.
With at least a decade remaining in the evolution of current design approaches, and hundreds of thou-
sands or millions of designs left that must either craft new ICs or use programmable versions of them, it
is far too soon to forget about today’s EDA approaches. And even if the technology changes to radically
new forms and structures, many of today’s EDA concepts will be reused and evolved for design into tech-
nologies well beyond the current scope and thinking.
The field of EDA for ICs has grown well beyond the point where any single individual can master it all,
or even be aware of the progress on all fronts. Therefore, there is a pressing need to create a snapshot of
this extremely broad and diverse subject. Students need a way of learning about the many disciplines and
topics involved in the design tools in widespread use today. As design grows multi-disciplinary, electronics
designers and EDA tool developers need to broaden their scope. The methods used in one subtopic may
well have applicability to new topics as they arise. All of electronics design can utilize a comprehensive
reference work in this field.
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