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RapidIO : the embedded system interconnect.pdf

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    RapidIO® The Embedded System Interconnect
    Contents
    Preface
    1 The Interconnect Problem
    1.1 Processor Performance and Bandwidth Growth
    1.2 Multiprocessing
    1.3 System of Systems
    1.4 Problems with Traditional Buses
    1.4.1 Bus Loading
    1.4.2 Signal Skew
    1.4.3 Expense of Wider Buses
    1.4.4 Problems with PCI
    1.5 The Market Problem
    1.6 RapidIO: A New Approach
    1.6.1 Why RapidIO?
    1.7 Where Will it be Used?
    1.8 An Analogy
    References
    2 RapidIO Technology
    2.1 Philosophy
    2.2 The Specification Hierarchy
    2.3 RapidIO Protocol Overview
    2.3.1 Packets and Control Symbols
    2.4 Packet Format
    2.5 Transaction Formats and Types
    2.6 Message Passing
    2.7 Globally Shared Memory
    2.8 Future Extensions
    2.9 Flow Control
    2.9.1 Link Level Flow Control
    2.9.2 End-to-end Flow Control
    2.10 The Parallel Physical Layer
    2.10.1 Parallel Electrical Interface
    2.11 The Serial Physical Layer
    2.11.1 PCS and PMA Layers
    2.11.2 Electrical Interface
    2.12 Link Protocol
    2.13 Maintenance and Error Management
    2.13.1 Maintenance
    2.13.2 System Discovery
    2.13.3 Error Coverage
    2.13.4 Error Recovery
    2.14 Performance
    2.14.1 Packet Structures
    2.14.2 Source Routing and Concurrency
    2.14.3 Packet Overhead
    2.15 Operation Latency
    References
    3 Devices, Switches, Transactions and Operations
    3.1 Processing Element Models
    3.1.1 Integrated Processor-memory Processing Element Model
    3.1.2 Memory-only Processing Element Model
    3.2 I/O Processing Element
    3.3 Switch Processing Element
    3.4 Operations and Transactions
    3.4.1 Operation Ordering
    3.4.2 Transaction Delivery
    3.4.3 Ordered Delivery System Issues
    3.4.4 Deadlock Considerations
    4 I/O Logical Operations
    4.1 Introduction
    4.2 Request Class Transactions
    4.2.1 Field Definitions for Request Class Transactions
    4.3 Response Class Transactions
    4.3.1 Field Definitions for Response Packet Formats
    4.4 A Sample Read Operation
    4.5 Write Operations
    4.6 Streaming Writes
    4.7 Atomic Operations
    4.8 Maintenance Operations
    4.9 Data Alignment
    5 Messaging Operations
    5.1 Introduction
    5.2 Message Transactions
    5.2.1 Type 10 Packet Format (Doorbell Class)
    5.2.2 Type 11 Packet Format (Message Class)
    5.2.3 Response Transactions
    5.3 Mailbox Structures
    5.3.1 A Simple Inbox
    5.3.2 An Extended Inbox
    5.3.3 Receiving Messages
    5.4 Outbound Mailbox Structures
    5.4.1 A Simple Outbox
    5.4.2 An Extended Outbox
    5.4.3 Transmitting Messages
    6 System Level Addressing in RapidIO Systems
    6.1 System Topology
    6.2 Switch-based Systems
    6.3 System Packet Routing
    6.4 Field Alignment and Definition
    6.5 Routing Maintenance Packets
    7 The Serial Physical Layer
    7.1 Packets
    7.1.1 Packet Format
    7.1.2 Packet Protection
    7.1.2.1 Packet CRC Operation
    7.1.2.2 16-Bit Packet CRC Code
    7.2 Control Symbols
    7.2.1 Stype0 Control Symbol Definitions
    7.2.1.1 Packet-accepted Control Symbol
    7.2.1.2 Packet-retry Control Symbol
    7.2.1.3 Packet-not-accepted Control Symbol
    7.2.1.4 Status Control Symbol
    7.2.1.5 Link-response Control Symbol
    7.2.2 Stype1 Control Symbol Definitions
    7.2.2.1 Start-of-packet Control Symbol
    7.2.2.2 Stomp Control Symbol
    7.2.2.3 End-of-packet Control Symbol
    7.2.2.4 Restart-from-retry Control Symbol
    7.2.2.5 Link-request Control Symbol
    7.2.2.6 Multicast-event Control Symbol
    7.2.3 Control Symbol Protection
    7.2.3.1 CRC-5 Code
    7.3 PCS and PMA Layers
    7.3.1 PCS Layer Functions
    7.3.2 PMA Layer Functions
    7.3.3 Definitions
    7.3.4 The 8B/10B Transmission Code
    7.3.5 Character and Code Group Notation
    7.3.6 Running Disparity
    7.3.6.1 Running Disparity Rules
    7.3.7 8B/10B Encoding
    7.3.8 Transmission Order
    7.3.9 8B/10B Decoding
    7.3.10 Special Code Groups and Characters
    7.3.10.1 Packet Delimiter Control Symbol (/PD/)
    7.3.10.2 Start of Control Symbol (/SC/)
    7.3.10.3 Idle (/I/ )
    7.3.10.4 Sync (/K/)
    7.3.10.5 Skip (/R/)
    7.3.10.6 Align (/A/)
    7.4 Using the Serial Physical Layer
    7.4.1 Port Initialization Process
    7.4.2 Packet Exchange Protocol
    7.4.2.1 Control Symbols
    7.4.2.2 Packets
    7.4.3 Idle Sequence
    7.4.4 Data Flow Across a 1x Serial RapidIO Link
    7.4.5 Data Flow Across a 4x Serial RapidIO Link
    7.4.6 Flow Control
    7.4.6.1 Receiver-controlled Flow Control
    7.4.6.2 Transmitter-controlled Flow Control
    7.4.6.3 Input Retry-stopped Recovery Process
    7.4.6.4 Output Retry-stopped Recovery Process
    7.4.7 Link Maintenance Protocol
    7.4.8 Canceling Packets
    7.5 Transaction and Packet Delivery Ordering Rules
    7.5.1 Deadlock Avoidance
    7.6 Error Detection and Recovery
    7.6.1 Lost Packet Detection
    7.6.2 Link Behavior Under Error
    7.6.3 Effect of Single-bit Code Group Errors
    7.6.4 Recoverable Errors
    7.6.4.1 Input Error-stopped Recovery Process
    7.6.4.2 Output Error-stopped Recovery Process
    7.6.4.3 Idle Sequence Errors
    7.6.4.4 Control Symbol Errors
    7.6.4.5 Reserved stype and cmd Field Encodings
    7.6.4.6 Link Protocol Violations
    7.6.4.7 Corrupted Control Symbols
    7.6.4.8 Packet Errors
    7.6.4.9 Link Time-out
    7.7 Retimers and Repeaters
    7.8 The Electrical Interface
    8 Parallel Physical Layer Protocol
    8.1 Packet Formats
    8.2 Control Symbol Formats
    8.2.1 Acknowledgment Control Symbol Formats
    8.2.1.1 Packet-accepted Control Symbol
    8.2.1.2 Packet-retry Control Symbol
    8.2.1.3 Packet-not-accepted Control Symbol
    8.2.2 Packet Control Symbols
    8.2.3 Link Maintenance Control Symbol Formats
    8.2.3.1 Link Request Control Symbol
    8.2.3.2 Link Response Control Symbol
    8.3 Control Symbol Transmission Alignment
    8.4 Packet Start and Control Symbol Delineation
    8.5 Packet Exchange Protocol
    8.5.1 Packet and Control Alignment
    8.5.2 Acknowledge Identification
    8.6 Field Placement and Definition
    8.6.1 Flow Control Fields Format
    8.6.2 Packet Priority and Transaction Request Flows
    8.6.3 Transaction and Packet Delivery
    8.6.4 Control Symbol Protection
    8.6.5 Packet Protection
    8.6.6 Transactional Boundaries
    8.7 Link Maintenance Protocol
    8.7.1 Command Descriptions
    8.7.1.1 Reset and Safety Lockouts
    8.7.1.2 Input-status
    8.7.1.3 Send-training
    8.7.2 Status Descriptions
    8.8 Packet Termination
    8.9 Packet Pacing
    8.10 Embedded Control Symbols
    8.11 Packet Alignment
    8.12 System Maintenance
    8.12.1 Port Initialization
    8.12.1.1 Port Width Mode Selection
    8.12.1.2 Ports Not Requiring Port Initialization
    8.12.1.3 Ports Requiring Port Initialization
    8.12.1.4 Port Initialization Process
    8.12.2 Link Initialization
    8.12.3 Training
    8.12.3.1 Training Pattern
    8.12.3.2 Training Pattern Transmission
    8.12.3.3 Maintenance Training
    8.12.3.4 Unexpected Training Pattern Reception
    8.13 System Clocking Considerations
    8.13.1 Example Clock Distribution
    8.13.2 Elasticity Mechanism
    8.14 Board Routing Guidelines
    8.14.1 Impedance
    8.14.2 Skew
    8.14.3 PCB Stackup
    8.14.4 Termination
    8.14.5 Additional Considerations
    8.14.5.1 Single Board Environments
    8.14.5.2 Single Connector Environments
    8.14.5.3 Backplane Environments
    9 Interoperating with PCI Technologies
    9.1 Address Map Considerations
    9.2 Transaction Flow
    9.2.1 PCI 2.2 to RapidIO Transaction Flow
    9.2.1.1 Posted PCI to RapidIO Transaction
    9.2.1.2 Non-posted PCI to RapidIO Transaction
    9.2.1.3 RapidIO to PCI Transaction
    9.3 PCI-X to RapidIO Transaction Flow
    9.4 RapidIO to PCI Transaction Mapping
    9.5 Operation Ordering and Transaction Delivery
    9.5.1 Operation Ordering
    9.5.2 Transaction Delivery Ordering
    9.5.3 PCI-X Relaxed Ordering Considerations
    9.6 Interactions with Globally Shared Memory
    9.7 Byte Lane and Byte Enable Usage
    9.8 Error Management
    10 RapidIO Bringup and Initialization Programming
    10.1 Overview of the System Bringup Process
    10.1.1 Boot Requirements
    10.1.2 Enumeration
    10.1.3 Address Space Mapping
    10.2 System Application Programming Interfaces
    10.2.1 Basic Hardware Abstraction Layer (HAL) Functions
    10.2.2 RapidIO Bringup HAL Functions
    10.2.3 Routing-table Manipulation HAL Functions
    10.2.4 Device Access Routine (DAR) Functions
    10.3 System Bringup Example
    11 Advanced Features
    11.1 System-level Flow Control
    11.1.1 Interconnect Fabric Congestion Example
    11.1.2 System-level Flow Control Operations
    11.1.3 End Point Flow Control Rules
    11.1.4 Switch Flow Control Rules
    11.2 Error Management Extensions
    11.2.1 Hot-insertion/extraction
    11.2.2 The Port-write Transaction
    11.2.3 Persistence of Error Management Registers
    11.2.4 Error Management Extensions
    11.3 Memory Coherency Support
    11.3.1 Features of the Globally Shared Memory (GSM) Specification
    11.4 Multicasting Transactions in RapidIO
    11.4.1 RapidIO Multicast Support
    11.4.2 Multicast Ordering Requirements
    11.4.3 Multicast Programming Model
    11.4.4 Other Multicast Characteristics
    11.5 Multicasting Symbols
    11.5.1 Example of Use of Multicast-event Control Symbol
    12 Data Streaming Logical Layer
    12.1 Introduction
    12.2 Type 9 Packet Format (Data Streaming Class)
    12.3 Virtual Streams
    12.3.1 Class of Service, Virtual Queues
    12.3.2 RapidIO Flows
    12.3.3 Segmentation and Reassembly
    12.3.4 Segmentation Contexts
    12.3.5 Reassembly
    12.4 Configuring Data Streaming Systems
    12.5 Advanced Traffic Management
    12.6 Using Data Streaming
    12.6.1 CSIX to RapidIO Data Streaming Interface
    12.6.1.1 Introduction to CSIX Packet Formats
    12.6.1.2 Adapting CSIX to RapidIO Data Streaming Format
    12.6.1.3 Flow Control
    12.6.2 Ethernet and IP Applications
    12.6.3 Ethernet Switching
    12.6.4 IP Switching
    12.6.5 TCP Offload
    12.6.6 RapidIO to ATM
    Reference
    13 Applications of the RapidIO Interconnect Technology
    13.1 RapidIO in Storage Systems
    13.1.1 Features of Storage
    13.1.2 Capacity
    13.1.3 Availability
    13.1.4 Density
    13.1.5 Manageability
    13.1.6 Storage System Applications of RapidIO
    13.1.6.1 Storage Requirements
    13.1.7 Conclusion
    13.2 RapidIO in Cellular Wireless Infrastructure
    13.2.1 Introduction to Wireless Infrastructure
    13.2.2 Mobile Switching Center/GPRS Support Node
    13.2.3 Core Network Interface
    13.2.4 Transcoding and Transrating
    13.2.5 Radio Network Control
    13.2.6 Basestation
    13.2.7 RapidIO For Wireless Infrastructure
    13.2.7.1 Simplification with RapidIO
    13.2.7.2 Architectural Possibilities with RapidIO
    13.2.8 Conclusions
    13.3 Fault-tolerant Systems and RapidIO
    13.3.1 Key Elements of Fault Tolerance
    13.3.1.1 No Single Point of Failure
    13.3.1.2 No Single Point of Repair
    13.3.1.3 Fault Recovery Support
    13.3.1.4 100% Fault Detection
    13.3.1.5 100% Fault Isolation
    13.3.1.6 Fault Containment
    13.3.2 Live Lock and Head of Queue Blocking
    13.3.3 A System Example
    13.3.4 Summary
    References
    14 Developing RapidIO Hardware
    14.1Introduction
    14.1.1 Implementation Performance–Cost Analysis
    14.1.2 Logical Layer Transaction Considerations
    14.1.3 RapidIO Transport Layer Considerations
    14.1.4 RapidIO Physical Layer Considerations
    14.1.5 Protocol Bridging Considerations
    14.1.6 Transaction Buffering Considerations
    14.1.7 Clocking Considerations
    14.1.8 Packet Data Alignment Considerations
    14.1.9 Data Recovery Considerations
    14.2 Implementing a RapidIO End Point
    14.2.1 End Point Overview
    14.2.2 Implementing RapidIO in an End Point
    14.2.3 Transaction Routing: Terminating End Point
    14.2.4 Implementing Logical and Transport Layer Functions
    14.2.5 Implementing Serial Physical Layer Functions
    14.2.6 Implementing Parallel Physical Layer Functions
    14.2.7 Outbound Transaction Flow
    14.2.8 Sample Outbound Module
    14.2.8.1 Re-transmit Queue
    14.2.8.2 Packet Generator
    14.2.8.3 Control Symbol Generator
    14.2.8.4 Logical Outbound Module
    14.2.9 Inbound Transaction Flow
    14.2.10 Sample Inbound Module
    14.2.10.1 Destination IDs
    14.2.10.2 End Point Inbound Module
    14.2.10.3 Transport Layer
    14.2.10.4 Inbound Buffers
    14.2.10.5 Response, Port-write Out and Debug Packet Assembler
    14.2.10.6 Elastic Rx/Tx FIFO and Lane Alignment
    14.2.11 Acknowledgment Symbol History Queue
    14.3 Supporting Functions
    14.3.1 RapidIO Controller Configuration
    14.3.2 Link Training
    14.3.3 Device Maintenance
    14.3.4 Performance Monitoring
    14.3.4.1 Traffic Efficiency
    14.3.4.2 Bit Error Rate
    14.3.4.3 Throughput
    14.3.4.4 Bottleneck Detection
    14.3.4.5 Congestion Detection
    14.3.5 Error Handling
    14.3.5.1 Recoverable Errors
    14.3.5.2 Inbound and Outbound Packet Errors
    14.3.5.3 Control Symbol Errors
    14.3.5.4 Non-recoverable Errors
    14.3.5.5 Outbound Port-write
    14.3.5.6 Inbound Port-write
    14.3.6 Interrupts
    14.3.6.1 Sample Controller Interrupts
    14.3.6.2 Switching Fabric Interrupts
    14.3.6.3 Terminating End Point
    14.3.6.4 Bridging Device Interrupts
    14.3.6.5 Mapping to Interrupt Output Pins
    14.3.7 Reset
    14.3.8 Clocking
    14.3.8.1 Parallel Switch Clocking
    14.3.8.2 End Point Clocking
    14.3.8.3 RapidIO Interface PLL Configuration
    14.3.8.4 Sample PLL Bypass
    14.3.8.5 Serial Switch Clocking
    14.4 Implementing a RapidIO Switch
    14.4.1 Switch Features
    14.4.2 Switch Performance and Cost Implications
    14.4.3 Implementing RapidIO in a Switch
    14.4.3.1 Inbound and Outbound Modules
    14.4.3.2 Sample Inbound Module
    14.4.3.3 Destination IDs
    14.4.3.4 Switch Packet Priority
    14.4.4 Port Mirroring Capability
    14.4.5 Sample Outbound Module
    14.4.6 Internal Switching Fabric
    14.4.7 Packet Routing: Routing Tables
    14.5 Summary
    15 Implementation Benefits of the RapidIO Interconnect Technology in FPGAs
    15.1 Building the Ecosystem
    15.2 Advances in FPGA Technology
    15.2.1 I/O Connectivity Options
    15.2.2 Rich Logic Fabrics
    15.2.3 The IP Portfolio
    15.3 Multiprotocol Support for the Embedded Environment
    15.4 Simple Handshake
    15.5 Low Buffering Overhead
    15.6 Efficient Error Coverage
    15.7 Conclusion
    16 Application of RapidIO to Mechanical Environments
    16.1 Helpful Features for Mechanical Environments
    16.2 Channel Characteristics
    16.3 Industry Standard Mechanical Platforms Supporting RapidIO
    16.3.1 RapidIO Hardware Interoperability Platform (HIP)
    16.3.2 CompactPCI Serial RapidIO (PICMG 2.18)
    16.3.3 AdvancedTCA Serial RapidIO (PICMG 3.5)
    16.3.4 Switched Mezzanine Card XMC (VITA 42)
    16.3.5 Advanced Mezzanine Card Serial RapidIO (PICMG AMC)
    16.3.6 VME Switched Serial VXS for RapidIO (VITA 41.2)
    16.3.7 Advanced Module Format (VITA 46)
    16.4 Summary
    Appendix A RapidIO Logical and Transport Layer Registers
    A.1 Reserved Register and Bit Behavior
    A.2 Capability Registers (CARs)
    A.2.1 Device Identity CAR (Offset 0x0 Word 0)
    A.2.2 Device Information CAR (Offset 0x0 Word 1)
    A.2.3 Assembly Identity CAR (Offset 0x8 Word 0)
    A.2.4 Assembly Information CAR (Offset 0x8 Word 1)
    A.2.5 Processing Element Features CAR (Offset 0x10 Word 0)
    A.2.6 Switch Port Information CAR (Offset 0x10 Word 1)
    A.2.7 Source Operations CAR (Offset 0x18 Word 0)
    A.2.8 Destination Operations CAR (Offset 0x18 Word 1)
    A.2.9 Data Streaming Information CAR (Configuration Space Offset 0x3C)
    A.3 Command and Status Registers (CSRs)
    A.3.1 Mailbox CSR (Offset 0x40 Word 0)
    A.3.2 Write-port or Doorbell CSR (Offset 0x40 Word 1)
    A.3.3 Data Streaming Logical Layer Control CSR (Offset 0x48 Word 0)
    A.3.4 Processing Element Logical Layer Control CSR (Offset 0x48 Word 1)
    A.3.5 Local Configuration Space Base Address 0 CSR (Offset 0x58 Word 0)
    A.3.6 Local Configuration Space Base Address 1 CSR (Offset 0x58 Word 1)
    A.3.7 Base Device ID CSR (Offset 0x60 Word 0)
    A.3.8 Host Base Device ID Lock CSR (Offset 0x68 Word 0)
    A.3.9 Component Tag CSR (Offset 0x68 Word 1)
    A.4 Extended Features Data Structure
    Appendix B Serial Physical Layer Registers
    B.1 Generic End Point Devices
    B.1.1 Register Maps
    B.1.2 Command and Status Registers (CSRs)
    B.1.2.1 Port Maintenance Block Header 0 (Block Offset 0x0 Word 0)
    B.1.2.2 Port Maintenance Block Header 1 (Block Offset 0x0 Word 1)
    B.1.2.3 Port Link Time-out Control CSR (Block Offset 0x20 Word 0)
    B.1.2.4 Port Response Time-out Control CSR (Block Offset 0x20 Word 1)
    B.1.2.5 Port General Control CSR (Block Offset 0x38 Word 1)
    B.1.2.6 Port n Error and Status CSRs (Offsets 0x58, 78, . . . , 238 Word 0)
    B.1.2.7 Port n Control CSR (Block Offsets 0x58, 78, . . . , 238 Word 1)
    B.2 Generic End Point Devices: Software-assisted Error Recovery Option
    B.2.1 Register Map
    B.2.2 Command and Status Registers (CSRs)
    B.2.2.1 Port Maintenance Block Header 0 (Block Offset 0x0 Word 0)
    B.2.2.2 Port Maintenance Block Header 1 (Block Offset 0x0 Word 1)
    B.2.2.3 Port Link Time-out Control CSR (Block Offset 0x20 Word 0)
    B.2.2.4 Port Response Time-out Control CSR (Block Offset 0x20 Word 1)
    B.2.2.5 Port General Control CSR (Block Offset 0x38 Word 1)
    B.2.2.6 Port n Link Maintenance Request CSRs (Offsets 0x40, 60, . . . , 220 Word 0)
    B.2.2.7 Port n Link Maintenance Response CSRs (0x40, 60, . . . , 220 Word 1)
    B.2.2.8 Port n Local ackID CSRs (Block Offsets 0x48, 68, . . . , 228 Word 0)
    B.2.2.9 Port n Error and Status CSRs (Block Offset 0x58, 78, . . . , 238 Word 0)
    B.2.2.10 Port n Control CSR (Block Offsets 0x58, 78, . . . , 238 Word 1)
    B.2.3 Generic Switch Devices
    B.2.4 Command and Status Registers (CSRs)
    B.2.4.1 Port Maintenance Block Header 0 (Block Offset 0x0 Word 0)
    B.2.4.2 Port Maintenance Block Header 1 (Block Offset 0x0 Word 1)
    B.2.4.3 Port Link Time-out Control CSR (Block Offset 0x20 Word 0)
    B.2.4.4 Port General Control CSR (Block Offset 0x38 Word 1)
    B.2.4.5 Port n Error and Status CSRs (Block Offsets 0x58, 78, . . . , 238 Word 0)
    B.2.4.6 Port n Control CSR (Block Offsets 0x58, 78, . . . , 238 Word 1)
    Appendix C Parallel Physical Layer Registers
    C.1 Generic End Point Devices
    C.1.1 Register Map
    C.1.2 Command and Status Registers (CSRs)
    C.1.2.1 Port Maintenance Block Header 0 (Block Offset 0x0 Word 0)
    C.1.2.2 Port Maintenance Block Header 1 (Block Offset 0x0 Word 1)
    C.1.2.3 Port Link Time-out Control CSR (Block Offset 0x20 Word 0)
    C.1.2.4 Port Response Time-out Control CSR (Block Offset 0x20 Word 1)
    C.1.2.5 Port General Control CSR (Block Offset 0x38 Word 1)
    C.1.2.6 Port n Error and Status CSRs (Block Offsets 0x58, 78, . . . , 238 Word 0)
    C.1.2.7 Port n Control CSR (Block Offsets 0x58, 78, . . . , 238 Word 1)
    C.2 Generic End Point Devices: Software-assisted Error Recovery Option
    C.2.1 Register Map
    C.2.2 Command and Status Registers (CSRs)
    C.2.2.1 Port Maintenance Block Header 0 (Block Offset 0x0 Word 0)
    C.2.2.2 Port Maintenance Block Header 1 (Block Offset 0x0 Word 1)
    C.2.2.3 Port Link Time-out Control CSR (Block Offset 0x20 Word 0)
    C.2.2.4 Port Response Time-out Control CSR (Block Offset 0x20 Word 1)
    C.2.2.5 Port General Control CSR (Block Offset 0x38 Word 1)
    C.2.2.6 Port n Link Maintenance Request CSRs (Block Offsets 0x40, 60, . . . , 220 Word 0)
    C.2.2.7 Port n Link Maintenance Response CSRs (Block Offsets 0x40, 60, . . . , 220 Word 1)
    C.2.2.8 Port n Local ackID Status CSRs (Block Offsets 0x48, 68, . . . , 228 Word 0)
    C.2.2.9 Port n Error and Status CSRs (Block Offsets 0x58, 78, . . . , 238 Word 0)
    C.2.2.10 Port n Control CSR (Block Offsets 0x58, 78, . . . , 238 Word 1)
    C.3 Switch Devices
    C.3.1 Register Map
    C.3.2 Command and Status Registers (CSRs)
    C.3.2.1 Port Maintenance Block Header 0 (Block Offset 0x0 Word 0)
    C.3.2.2 Port Maintenance Block Header 1 (Block Offset 0x0 Word 1)
    C.3.2.3 Port Link Time-out Control CSR (Block Offset 0x20 Word 0)
    C.3.2.4 Port General Control CSR (Block Offset 0x38 Word 1)
    C.3.2.5 Port n Error and Status CSRs (Block Offsets 0x58, 78, . . . , 238 Word 0)
    C.3.2.6 Port n Control CSR (Block Offsets 0x58, 78, . . . , 238 Word 1)
    Appendix D Error Management Extensions Registers
    D.1 Additions to Existing Registers
    D.2 New Error Management Register
    D.2.1 Register Map
    D.2.2 Command and Status Registers (CSRs)
    D.2.2.1 Error Reporting Block Header (Block Offset 0x0 Word 0)
    D.2.2.2 Logical/Transport Layer Error Detect CSR (Block Offset 0x08 Word 0)
    D.2.2.3 Logical/Transport Layer Error Enable CSR (Block Offset 0x08 Word 1)
    D.2.2.4 Logical/Transport Layer High Address Capture CSR (Block Offset 0x10 Word 0)
    D.2.2.5 Logical/Transport Layer Address Capture CSR (Block Offset 0x10 Word 1)
    D.2.2.6 Logical/Transport Layer Device ID Capture CSR (Block Offset 0x18 Word 0)
    D.2.2.7 Logical/Transport Layer Control Capture CSR (Block Offset 0x18 Word 1)
    D.2.2.8 Port-write Target deviceID CSR (Block Offset 0x28 Word 0)
    D.2.2.9 Packet Time-to-live CSR (Block Offset 0x28 Word 1)
    D.2.2.10 Port n Error Detect CSR (Block Offset 0x40, 80, . . . , 400, Word 0)
    D.2.2.11 Port n Error Rate Enable CSR (Block Offset 0x40, 80, . . . , 400, Word 1)
    D.2.2.12 Port n Error Capture Attributes CSR (Block Offset 0x48, 88, . . . , 408, Word 0)
    D.2.2.13 Port n Packet/Control Symbol Error Capture CSR 0 (Block Offset 0x48, 88, . . . , 408, Word 1)
    D.2.2.14 Port n Packet Error Capture CSR 1 (Block Offset 0x50, 90, . . . , 410, Word 0)
    D.2.2.15 Port n Packet Error Capture CSR 2 (Block Offset 0x50, 90, . . . , 410, Word 1)
    D.2.2.16 Port n Packet Error Capture CSR 3 (Block Offset 0x58, 98, . . . , 418, Word 0)
    D.2.2.17 Port n Error Rate CSR (Block Offset 0x68, A8, . . . , 428, Word 0)
    D.2.2.18 Port n Error Rate Threshold CSR (Block Offset 0x68, A8, . . . , 428, Word 1)
    Index
    RapidIO® The Embedded System Interconnect Sam Fuller RapidIO Trade Association, USA with contributions from Alan Gatherer CTO, Wireless Infrastructure, Texas, USA Charles Hill Motorola, Inc., Arizona, USA Victor Menasce Applied Micro Circuits Corporation, Ontario, Canada Brett Niver EMC Corporation, Hopkinton, USA Richard O’Connor Tundra Semiconductor Corporation, Ontario, Canada Peter Olanders Ericsson AB, Stockholm, Sweden Nupur Shah Xilinx Inc., California, USA David Wickliff Lucent Technologies, Illinois, USA
    RapidIO® The Embedded System Interconnect
    RapidIO® The Embedded System Interconnect Sam Fuller RapidIO Trade Association, USA with contributions from Alan Gatherer CTO, Wireless Infrastructure, Texas, USA Charles Hill Motorola, Inc., Arizona, USA Victor Menasce Applied Micro Circuits Corporation, Ontario, Canada Brett Niver EMC Corporation, Hopkinton, USA Richard O’Connor Tundra Semiconductor Corporation, Ontario, Canada Peter Olanders Ericsson AB, Stockholm, Sweden Nupur Shah Xilinx Inc., California, USA David Wickliff Lucent Technologies, Illinois, USA
    Copyright © 2005 John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (+44) 1243 779777 Email (for orders and customer service enquiries): cs-books@wiley.co.uk Visit our Home Page on www.wileyeurope.com or www.wiley.com All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or emailed to permreq@wiley.co.uk, or faxed to (+44) 1243 770620. Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The Publisher is not associated with any product or vendor mentioned in this book. This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the Publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Other Wiley Editorial Offices John Wiley & Sons Inc., 111 River Street, Hoboken, NJ 07030, USA Jossey-Bass, 989 Market Street, San Francisco, CA 94103-1741, USA Wiley-VCH Verlag GmbH, Boschstr. 12, D-69469 Weinheim, Germany John Wiley & Sons Australia Ltd, 33 Park Road, Milton, Queensland 4064, Australia John Wiley & Sons (Asia) Pte Ltd, 2 Clementi Loop #02-01, Jin Xing Distripark, Singapore 129809 John Wiley & Sons Canada Ltd, 22 Worcester Road, Etobicoke, Ontario, Canada M9W 1L1 Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic books. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN 0-470-09291-2 Typeset in 10/12pt Times by Graphicraft Limited, Hong Kong Printed and bound in Great Britain by TJ International, Padstow, Cornwall This book is printed on acid-free paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production.
    Contents Preface 1 The Interconnect Problem 1.1 Processor Performance and Bandwidth Growth 1.2 Multiprocessing 1.3 System of Systems 1.4 Problems with Traditional Buses 1.4.1 Bus Loading 1.4.2 Signal Skew 1.4.3 Expense of Wider Buses 1.4.4 Problems with PCI 1.5 The Market Problem 1.6 RapidIO: A New Approach 1.6.1 Why RapidIO? 1.7 Where Will it be Used? 1.8 An Analogy References 2 RapidIO Technology 2.1 Philosophy 2.2 The Specification Hierarchy 2.3 RapidIO Protocol Overview 2.3.1 Packets and Control Symbols 2.4 Packet Format 2.5 Transaction Formats and Types 2.6 Message Passing 2.7 Globally Shared Memory 2.8 Future Extensions 2.9 Flow Control 2.9.1 Link Level Flow Control 2.9.2 End-to-end Flow Control xix 1 1 2 3 4 6 6 6 7 7 8 8 9 11 12 13 13 14 15 15 16 17 17 18 18 18 18 19
    vi CONTENTS 2.10 The Parallel Physical Layer 2.10.1 Parallel Electrical Interface 2.11 The Serial Physical Layer 2.11.1 PCS and PMA Layers 2.11.2 Electrical Interface 2.12 Link Protocol 2.13 Maintenance and Error Management 2.13.1 Maintenance 2.13.2 System Discovery 2.13.3 Error Coverage 2.13.4 Error Recovery 2.14 Performance 2.14.1 Packet Structures 2.14.2 Source Routing and Concurrency 2.14.3 Packet Overhead 2.15 Operation Latency References 3 Devices, Switches, Transactions and Operations 3.1 Processing Element Models 3.1.1 Integrated Processor-memory Processing Element Model 3.1.2 Memory-only Processing Element Model 3.2 I/O Processing Element 3.3 Switch Processing Element 3.4 Operations and Transactions 3.4.1 Operation Ordering 3.4.2 Transaction Delivery 3.4.3 Ordered Delivery System Issues 3.4.4 Deadlock Considerations 4 I/O Logical Operations 4.1 Introduction 4.2 Request Class Transactions 4.2.1 Field Definitions for Request Class Transactions 4.3 Response Class Transactions 4.3.1 Field Definitions for Response Packet Formats 4.4 A Sample Read Operation 4.5 Write Operations 4.6 Streaming Writes 4.7 Atomic Operations 4.8 Maintenance Operations 4.9 Data Alignment 5 Messaging Operations 5.1 Introduction 5.2 Message Transactions 20 21 21 21 22 22 23 23 23 23 24 24 24 25 25 25 26 27 27 28 29 29 30 30 30 33 33 33 35 35 35 36 37 37 39 42 44 45 45 47 49 49 50
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