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Network Processors Architecture Programming and Implementation.pdf

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    Cover Page
    Network Processors
    Copyright Page
    Table of Contents
    Preface
    Chapter 1. Introduction and Motivation
    1.1 Network Processors Ecosystem
    1.2 Communication Systems and Applications
    1.3 Network Elements
    1.4 Network Processors
    1.5 Structure of This Book
    1.6 Summary
    Part 1. Networks
    Chapter 2. Networking Fundamentals
    2.1 Introduction
    2.2 Networks Primer
    2.3 Data Networking Models
    2.4 Basic Network Technologies
    2.5 Telecom Networks
    2.6 Data Networks
    2.7 Summary
    Appendix A: Registration Protocols
    Appendix B: Spanning Tree Protocols
    Chapter 3. Converged Networks
    3.1 Introduction
    3.2 From Telecom Networks to Data Networks
    3.3 From Datacom to Telecom
    3.4 Summary
    Appendix A: Routing Information Distribution Protocols
    Chapter 4. Access and Home Networks
    4.1 Access Networks
    4.2 Home and Building Networks
    4.3 Summary
    Part 2. Processing
    Chapter 5. Packet Processing
    5.1 Introduction and Definitions
    5.2 Ingress and Egress
    5.3 Framing
    5.4 Parsing and Classification
    5.5 Search, Lookup, and Forwarding
    5.6 Modification
    5.7 Compression and Encryption
    5.8 Queueing and Traffic Management
    5.9 Summary
    Chapter 6. Packet Flow Handling
    6.1 Definitions
    6.2 Quality of Service
    6.3 Class of Service
    6.4 QoS Mechanisms
    6.5 Summary
    Chapter 7. Architecture
    7.1 Introduction
    7.2 Background and Definitions
    7.3 Equipment Design Alternatives: ASICS Versus NP
    7.4 Network Processors Basic Architectures
    7.5 Instruction Set (Scalability; Processing Speed)
    7.6 NP Components
    7.7 Summary
    Chapter 8. Software
    8.1 Introduction
    8.2 Conventional Systems
    8.3 Programming Models Classification
    8.4 Parallel Programming
    8.5 Pipelining
    8.6 Network Processor Programming
    8.7 Summary
    Appendix A: Parsing and Classification Languages
    Appendix B: Click and NP-Click Language and Programming Model
    Appendix C: PPL Language and Programming Model
    Chapter 9. NP Peripherals
    9.1 Switch Fabrics
    9.2 Coprocessors
    9.3 Summary
    Part 3. A Network Processor: EZchip
    Chapter 10. EZchip Architecture, Capabilities, and Applications
    10.1 General Description
    10.2 System Architecture
    10.3 Lookup Structures
    10.4 Counters, Statistics and Rate Control
    10.5 Traffic Management
    10.6 Stateful Classification
    10.7 Multicast Frames
    10.8 Data Flow
    10.9 Summary
    Chapter 11. EZchip Programming
    11.1 Instruction Pipeline
    11.2 Writing NP Microcode
    11.3 Preprocessor Overview
    11.4 Developing and Running NP Applications
    11.5 Top Common Commands
    11.6 Summary
    Appendix A: Preprocessor Commands
    Chapter 12. Parsing
    12.1 Internal Engine Diagram
    12.2 Topparse Registers
    12.3 Topparse Structures
    12.4 Topparse Instruction Set
    12.5 Example
    12.6 Summary
    Appendix A: Detailed Register Description
    Appendix B: Topparse Addressing Modes
    Appendix C: Topparse Detailed Instruction Set
    Chapter 13. Searching
    13.1 Introduction
    13.2 Internal Engine Diagram
    13.3 Topsearch I Structures
    13.4 Interface to Topparse (Input to Topsearch)
    13.5 Interface to Topresolve (Output of Topsearch)
    13.6 Hash Table Learning
    13.7 Example
    13.8 Summary
    Chapter 14. Resolving
    14.1 Internal Engine Diagram
    14.2 Topresolve Registers
    14.3 Topresolve Structures
    14.4 Topresolve Instruction Set
    14.5 Example
    14.6 Summary
    Appendix A: Detailed Register Description
    Appendix B: Topresolve Addressing Modes
    Appendix C: Topresolve Detailed Instruction Set
    Chapter 15. Modifying
    15.1 Introduction
    15.2 Internal Engine Diagram
    15.3 Topmodify Registers
    15.4 Topmodify Structures
    15.5 Topmodify Instruction Set
    15.6 Example
    15.7 Summary
    Appendix A: Detailed Register Description
    Appendix B: Topmodify Addressing Modes
    Appendix C: Topmodify Detailed Instruction Set
    Chapter 16. Running the Virtual Local Area Network Example
    16.1 Installation
    16.2 Getting Started
    16.3 Microcode Development Workflow
    16.4 Summary
    Chapter 17. Writing Your First High-Speed Network Application
    17.1 Introduction
    17.2 Data Flow and Top Microcode
    17.3 Data Structures
    17.4 Summary
    List of Acronyms
    References
    Index
    Network Processors
    The Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology The Designer’s Guide to VHDL, Second Edition Peter J. Ashenden The System Designer’s Guide to VHDL-AMS Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden Modeling Embedded Systems and SoCs Axel Jantsch ASIC and FPGA Verification: A Guide to Component Modeling Richard Munden Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne Wolf Functional Verification Bruce Wile, John Goss, and Wolfgang Roesner Customizable and Configurable Embedded Processors Edited by Paolo Ienne and Rainer Leupers Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Configured Processors Steve Leibson ESL Design and Verification Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon System-on-Chip Test Architectures Edited by Laung-Terng Wang, Charles Stroud, and Nur Touba Verification Techniques for System-Level Design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad VHDL-2008: Just the New Stuff Peter J. Ashenden and Jim Lewis On-Chip Communication Architectures: System on Chip Interconnect Sudeep Pasricha and Nikil Dutt Embedded DSP Processor Design: Application Specific Instruction Set Processors Dake Liu Processor Description Languages: Applications and Methodologies Edited by Prabhat Mishra and Nikil Dutt
    Network Processors Architecture, Programming, and Implementation Ran Giladi Ben-Gurion University of the Negev and EZchip Technologies Ltd. AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Morgan Kaufmann is an imprint of Elsevier
    Morgan Kaufmann Publishers is an imprint of Elsevier. 30 Corporate Drive, Suite 400, Burlington, MA 01803 This book is printed on acid-free paper. ⬁ Copyright © 2008 by Elsevier Inc. All rights reserved. Designations used by companies to distinguish their products are often claimed as trademarks or registered trademarks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, scanning, or otherwise, without prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (+44) 1865 843830, fax: (+44) 1865 853333, e-mail: permissions@elsevier.com. You may also complete your request on-line via the Elsevier homepage (http://elsevier.com), by selecting “Support & Contact” then “Copyright and Permission” and then “Obtaining Permissions.” Library of Congress Cataloging-in-Publication Data Giladi, Ran. Network processors: architecture, programming, and implementation/Ran Giladi. p. cm.—(The Morgan Kaufmann systems on silicon series) Includes bibliographical references and index. ISBN 978-0-12-370891-5 (alk. paper) 1. Network processors. 2. Routing (Computer network management)—Equipment and supplies. 3. Packet switching (Data transmission)—Equipment and supplies. I. Title. TK5105.543.G55 2008 621.382’1–dc22 2008024883 For information on all Morgan Kaufmann publications, visit our Website at www.mkp.com or www.books.elsevier.com Printed in the United States 08 09 10 11 12 10 9 8 7 6 5 4 3 2 1 Working together to grow libraries in developing countries www.elsevier.com | www.bookaid.org | www.sabre.org
    In memory of my father Benjamin (Sontag) Z”L To my mother Rita (Aaron) To my beloved wife Kora To Ornit, Niv, and Itamar, our wonderful children, and to my dear brother Eival
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    Contents Preface ............................................................................................ xi Introduction and Motivation ........................................... 1.1 Network Processors Ecosystem ............................................ 1.2 Communication Systems and Applications ........................... 1.3 Network Elements ................................................................ 1.4 Network Processors .............................................................. 1.5 1.6 1 1 2 6 8 Structure of This Book .......................................................... 10 Summary ............................................................................... 12 CHAPTER 1 PART 1 Networks CHAPTER 2 Networking Fundamentals .............................................. 15 2.1 Introduction .......................................................................... 16 2.2 Networks Primer ................................................................... 17 2.3 Data Networking Models ...................................................... 21 2.4 Basic Network Technologies ................................................. 25 2.5 Telecom Networks ................................................................ 26 2.6 Data Networks ...................................................................... 38 2.7 Summary ............................................................................... 69 Appendix A ............................................................................ 70 Appendix B ........................................................................... 72 Converged Networks ........................................................ 77 CHAPTER 3 3.1 Introduction .......................................................................... 77 3.2 From Telecom Networks to Data Networks .......................... 78 3.3 From Datacom to Telecom .................................................... 87 3.4 Summary ............................................................................... 134 Appendix A ............................................................................ 135 CHAPTER 4 Access and Home Networks ........................................... 149 4.1 Access Networks ................................................................... 149 4.2 Home and Building Networks ............................................... 178 4.3 Summary ............................................................................... 180 PART 2 Processing Packet Processing ............................................................ 183 CHAPTER 5 5.1 Introduction and Defi nitions ................................................ 183 5.2 Ingress and Egress ................................................................. 186 5.3 Framing ................................................................................. 188
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