logo资料库

Diamond_Reveal_031910工具使用.ppt

发布时间：2022-06-14 发布人：admin 分类：说明书 资料大小：1.30M 资料格式：ppt 举报 版权申诉
第1页 / 共27页
第2页 / 共27页
第3页 / 共27页
第4页 / 共27页
第5页 / 共27页
第6页 / 共27页
第7页 / 共27页
第8页 / 共27页
资料共27页，剩余部分请下载后查看
    REVEAL INTRODUCTION FPGA ON-CHIP DEBUG Lattice Confidential
    Reveal Training Agenda • Highlights • User Tool Flow • Key Concepts • Tool Details • Summary • JTAG Builder Flow Lattice Diamond Reveal Page: 2 © 2010 Lattice Semiconductor Corporation
    Reveal Most Important to Remember! • Reveal Users Guide on-line help and website – PDF (176 pages) available in – Complete information about all Reveal features • Reveal Troubleshooting Guide – PDF (9 pages) available in on- line help and website – Complete information about all Reveal features • Look There First! – Rare problem not covered in these documents Lattice Diamond Reveal Page: 3 © 2010 Lattice Semiconductor Corporation
    Reveal Introduction • Hardware Debugging Tool – Embedded Logic Analyzer for debugging internal signals – Supports MachXO, EC/ECP, XP, ECP2/M, XP2, SC/M, ECP3 devices – Many advanced features compared to ispTRACY Lattice Diamond Reveal Page: 4 © 2010 Lattice Semiconductor Corporation
    Reveal Highlights • Project Navigator Integration – Reveal “rvl” file indicates presence of debug – Original design can be updated and debug automatically – Debug can be removed by deleting “rvl” file from Project reapplied Navigator • Uses Signal-Centric Method – Eliminates user need to “design” and connect debug cores – Significantly improved ease of use • Advanced Triggering Capabilities – Trigger Units (TU) for dynamic signal comparisons – Trigger Expressions (TE) for dynamic combinations and sequences of trigger units – Most advanced triggering capabilities of any on-chip debug tool Lattice Diamond Reveal Page: 5 © 2010 Lattice Semiconductor Corporation
    User Tool Flow • User Flow – Project Navigator – Reveal Inserter – ispVM – Reveal Analyzer • Simpler User Flow than Competitors Project Navigator Reveal Inserter Build Database MAP PAR Generate Bitfile Debug IP Cores Modified Design Synthesis .lpf file .rvl file .rvs file .rva file • Reveal Inserter and Analyzer Share Debug Data ispVM Lattice FPGA Reveal Analyzer Software Tools Background Tasks Lattice Diamond Reveal Page: 6 © 2010 Lattice Semiconductor Corporation
    Datasets • FPGA Being Debugged Contains – User Design – Debug Logic • Dataset is a Container for Debug Information for a Design – Debug logic can have multiple cores – Each core has unique sample clock – Each core has trigger logic & storage buffer – Each core has unique settings • Multiple Reveal Project Files can be Saved Lattice Diamond Reveal Page: 7 © 2010 Lattice Semiconductor Corporation
    Trigger Units & Trigger Expressions • Trigger Units Compare Signals Against Operators And Values – Operators for ==, !=, >, >=, <, =<, rising-edge, falling-edge, serial compare • Trigger Expressions Combine Trigger Units Into Flexible Equations – &, |, ^, !, THEN, NEXT operators – Multiple expressions can be combined – Expressions can be dynamically changed when debugging Trigger Units Trigger Expressions Lattice Diamond Reveal Page: 8 © 2010 Lattice Semiconductor Corporation
    分享到：
    赞 收藏

    相关推荐

    资料库

    开发技术

    共收录19306份资料，累计14个分类，关注成员有19位，主要包括：Actionscript,Javascript,PHP,VB,Perl,Delphi,Python,C#,C,Java,C++,Web开发,硬件开发,其它

    热门标签

    Actionscript Javascript PHP VB Perl Delphi Python C# C Java C++ Web开发 硬件开发 其它

    最新资料