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PCI Express® Base Specification Revision 2.0.pdf
Objective of the Specification
Document Organization
Documentation Conventions
Terms and Acronyms
Reference Documents
1. Introduction
1.1. A Third Generation I/O Interconnect
1.2. PCI Express Link
1.3. PCI Express Fabric Topology
1.3.1. Root Complex
1.3.2. Endpoints
1.3.2.1. Legacy Endpoint Rules
1.3.2.2. PCI Express Endpoint Rules
1.3.2.3. Root Complex Integrated Endpoint Rules
1.3.3. Switch
1.3.4. Root Complex Event Collector
1.3.5. PCI Express to PCI/PCI-X Bridge
1.4. PCI Express Fabric Topology Configuration
1.5. PCI Express Layering Overview
1.5.1. Transaction Layer
1.5.2. Data Link Layer
1.5.3. Physical Layer
1.5.4. Layer Functions and Services
1.5.4.1. Transaction Layer Services
1.5.4.2. Data Link Layer Services
1.5.4.3. Physical Layer Services
1.5.4.4. Inter-Layer Interfaces
1.5.4.4.1. Transaction/Data Link Interface
1.5.4.4.2. Data Link/Physical Interface
2. Transaction Layer Specification
2.1. Transaction Layer Overview
2.1.1. Address Spaces, Transaction Types, and Usage
2.1.1.1. Memory Transactions
2.1.1.2. I/O Transactions
2.1.1.3. Configuration Transactions
2.1.1.4. Message Transactions
2.1.2. Packet Format Overview
2.2. Transaction Layer Protocol - Packet Definition
2.2.1. Common Packet Header Fields
2.2.2. TLPs with Data Payloads - Rules
2.2.3. TLP Digest Rules
2.2.4. Routing and Addressing Rules
2.2.4.1. Address Based Routing Rules
2.2.4.2. ID Based Routing Rules
2.2.5. First/Last DW Byte Enables Rules
2.2.6. Transaction Descriptor
2.2.6.1. Overview
2.2.6.2. Transaction Descriptor – Transaction ID Field
2.2.6.3. Transaction Descriptor – Attributes Field
2.2.6.4. Relaxed Ordering Attribute
2.2.6.5. No Snoop Attribute
2.2.6.6. Transaction Descriptor – Traffic Class Field
2.2.7. Memory, I/O, and Configuration Request Rules
2.2.8. Message Request Rules
2.2.8.1. INTx Interrupt Signaling - Rules
2.2.8.2. Power Management Messages
2.2.8.3. Error Signaling Messages
2.2.8.4. Locked Transactions Support
2.2.8.5. Slot Power Limit Support
2.2.8.6. Vendor_Defined Messages
2.2.8.7. Ignored Messages
2.2.9. Completion Rules
2.3. Handling of Received TLPs
2.3.1. Request Handling Rules
2.3.1.1. Data Return for Read Requests
2.3.2. Completion Handling Rules
2.4. Transaction Ordering
2.4.1. Transaction Ordering Rules
2.4.2. Update Ordering and Granularity Observed by a Read Transaction
2.4.3. Update Ordering and Granularity Provided by a Write Transaction
2.5. Virtual Channel (VC) Mechanism
2.5.1. Virtual Channel Identification (VC ID)
2.5.2. TC to VC Mapping
2.5.3. VC and TC Rules
2.6. Ordering and Receive Buffer Flow Control
2.6.1. Flow Control Rules
2.6.1.1. FC Information Tracked by Transmitter
2.6.1.2. FC Information Tracked by Receiver
2.7. Data Integrity
2.7.1. ECRC Rules
2.7.2. Error Forwarding
2.7.2.1. Error Forwarding Usage Model
2.7.2.2. Rules For Use of Data Poisoning
未标题
2.8. Completion Timeout Mechanism
2.9. Link Status Dependencies
2.9.1. Transaction Layer Behavior in DL_Down Status
2.9.2. Transaction Layer Behavior in DL_Up Status
3. Data Link Layer Specification
3.1. Data Link Layer Overview
3.2. Data Link Control and Management State Machine
3.2.1. Data Link Control and Management State Machine Rules
3.3. Flow Control Initialization Protocol
3.3.1. Flow Control Initialization State Machine Rules
3.4. Data Link Layer Packets (DLLPs)
3.4.1. Data Link Layer Packet Rules
3.5. Data Integrity
3.5.1. Introduction
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter)
3.5.2.1. LCRC and Sequence Number Rules (TLP Transmitter)
3.5.2.2. Handling of Received DLLPs
3.5.3. LCRC and Sequence Number (TLP Receiver)
3.5.3.1. LCRC and Sequence Number Rules (TLP Receiver)
4. Physical Layer Specification
4.1. Introduction
4.2. Logical Sub-block
4.2.1. Symbol Encoding
4.2.1.1. Serialization and De-serialization of Data
4.2.1.2. Special Symbols for Framing and Link Management (K Codes)
4.2.1.3. 8b/10b Decode Rules
4.2.2. Framing and Application of Symbols to Lanes
4.2.3. Data Scrambling
4.2.4. Link Initialization and Training
4.2.4.1. Training Sequences
4.2.4.2. Electrical Idle Sequences
4.2.4.3. Inferring Electrical Idle
4.2.4.4. Lane Polarity Inversion
4.2.4.5. Fast Training Sequence (FTS)
4.2.4.6. Link Error Recovery
4.2.4.7. Reset
4.2.4.7.1. Fundamental Reset
4.2.4.7.2. Hot Reset
4.2.4.8. Link Data Rate Negotiation
4.2.4.9. Link Width and Lane Sequence Negotiation
4.2.4.9.1. Required and Optional Port Behavior
4.2.4.10. Lane-to-Lane De-skew
4.2.4.11. Lane vs. Link Training
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions
4.2.5.1. Detect
4.2.5.2. Polling
4.2.5.3. Configuration
4.2.5.4. Recovery
4.2.5.5. L0
4.2.5.6. L0s
4.2.5.7. L1
4.2.5.8. L2
4.2.5.9. Disabled
4.2.5.10. Loopback
4.2.5.11. Hot Reset
4.2.6. Link Training and Status State Rules
4.2.6.1. Detect
4.2.6.1.1. Detect.Quiet
4.2.6.1.2. Detect.Active
4.2.6.2. Polling
4.2.6.2.1. Polling.Active
4.2.6.2.2. Polling.Compliance
4.2.6.2.3. Polling.Configuration
4.2.6.2.4. Polling.Speed
4.2.6.3. Configuration
4.2.6.3.1. Configuration.Linkwidth.Start
4.2.6.3.1.1. Downstream Lanes
4.2.6.3.1.2. Upstream Lanes
4.2.6.3.2. Configuration.Linkwidth.Accept
4.2.6.3.2.1. Downstream Lanes
4.2.6.3.2.2. Upstream Lanes
4.2.6.3.3. Configuration.Lanenum.Accept
4.2.6.3.3.1. Downstream Lanes
4.2.6.3.3.2. Upstream Lanes
4.2.6.3.4. Configuration.Lanenum.Wait
4.2.6.3.4.1. Downstream Lanes
4.2.6.3.4.2. Upstream Lanes
4.2.6.3.5. Configuration.Complete
4.2.6.3.5.1. Downstream Lanes
4.2.6.3.5.2. Upstream Lanes
4.2.6.3.6. Configuration.Idle
4.2.6.4. Recovery
4.2.6.4.1. Recovery.RcvrLock
4.2.6.4.2. Recovery.Speed
4.2.6.4.3. Recovery.RcvrCfg
4.2.6.4.4. Recovery.Idle
4.2.6.5. L0
4.2.6.6. L0s
4.2.6.6.1. Receiver L0s
4.2.6.6.1.1. Rx_L0s.Entry
4.2.6.6.1.2. Rx_L0s.Idle
4.2.6.6.1.3. Rx_L0s.FTS
4.2.6.6.2. Transmitter L0s
4.2.6.6.2.1. Tx_L0s.Entry
4.2.6.6.2.2. Tx_L0s.Idle
4.2.6.6.2.3. Tx_L0s.FTS
4.2.6.7. L1
4.2.6.7.1. L1.Entry
4.2.6.7.2. L1.Idle
4.2.6.8. L2
4.2.6.8.1. L2.Idle
4.2.6.8.2. L2.TransmitWake
4.2.6.9. Disabled
4.2.6.10. Loopback
4.2.6.10.1. Loopback.Entry
4.2.6.10.2. Loopback.Active
4.2.6.10.3. Loopback.Exit
4.2.6.11. Hot Reset
4.2.7. Clock Tolerance Compensation
4.2.7.1. Rules for Transmitters
4.2.7.2. Rules for Receivers
4.2.8. Compliance Pattern
4.2.9. Modified Compliance Pattern
4.3. Electrical Sub-block
4.3.1. Maintaining Backwards Compatibility
4.3.1.1. 2.5 GT/s is Not a Subset of 5.0 GT/s
4.3.1.2. Component Interfaces
4.3.2. Jitter Budgeting and Measurement
4.3.3. Transmitter Specification
4.3.3.1. Transmitter Phase Jitter Filtering
4.3.3.2. Low and Full Swing Transmitter Output Levels
4.3.3.3. Transmitter Margining
4.3.3.4. Transmitter Pin to Pad Correlation
4.3.3.5. Transmitter Specification
4.3.3.6. Measurement Setup For Characterizing Transmitter
4.3.3.7. Voltage Level Definitions
4.3.3.8. Transmitter Parameters Details
4.3.3.9. Transmitter De-emphasis
4.3.3.9.1. Measuring Tx Eye Width in the Presence of De-Emphasis
4.3.3.10. Transmitter PLL Bandwidth and Peaking
4.3.3.11. Transmitter Return Loss
4.3.4. Receiver Specification
4.3.4.1. Receiver Pin to Pad Correlation
4.3.4.2. Receiver Tolerancing at 5.0 GT/s
4.3.4.3. Calibration Channel Characteristics
4.3.4.4. Receiver Specifications
4.3.4.5. Receiver Return Loss
4.3.4.6. Receiver Compliance Eye Diagram
4.3.4.7. Receiver Dynamic Voltage Range
4.3.4.8. Exit From Idle Detect (EFI)
4.3.4.9. Receiver Loopback
4.3.5. Transmitter and Receiver DC Specifications
4.3.5.1. Channel AC Coupling Capacitors
4.3.5.2. ESD Protection
4.3.5.3. Short Circuit Requirements
4.3.5.4. Transmitter and Receiver Termination
4.3.5.5. Electrical Idle
4.3.5.6. DC Common Mode Voltage
4.3.5.7. Receiver Detection
4.3.5.7.1. Differential Receiver Detect
4.3.5.8. Beacon
4.3.5.8.1. Beacon Example
4.3.6. Channel Specifications
4.3.6.1. Channel Characteristics at 2.5 GT/s
4.3.6.2. Channel Characteristics at 5.0 GT/s
4.3.6.2.1. Procedure for Channel Measurement and Margin Extraction
4.3.6.2.2. Acquiring the Channel's s-parameters
4.3.6.2.3. Defining the Simulation Environment
4.3.6.2.4. Defining Worst Case Data Patterns and Tx Corners
4.3.6.2.5. Accounting for Jitter When Characterizing the Channel
4.3.6.2.6. Specifying the Channel for the Low Voltage Swing Option
4.3.6.2.7. Multi-Segment Channels
4.3.6.3. Upper Limit on Channel Capacitance
4.3.7. Reference Clock Specifications
4.3.7.1. Spread Spectrum Clock (SSC) Sources
4.3.7.2. Refclk Architectures
4.3.7.2.1. Filtering Functions Applied to Refclk Measurements
4.3.7.2.2. Common Refclk Rx Architecture
4.3.7.2.3. Refclk Compliance Parameters for Common Refclk Rx Architecture
4.3.7.2.4. Data Clocked Rx Architecture
4.3.7.2.5. Refclk Compliance Parameters for Data Clocked Rx Architecture
4.3.7.3. Refclk Test Setup
4.3.7.4. Bit Rate Tolerance and Spread Spectrum Clocking
4.3.7.5. Separate Refclk Architecture
5. Power Management
5.1. Overview
5.1.1. Statement of Requirements
5.2. Link State Power Management
5.3. PCI-PM Software Compatible Mechanisms
5.3.1. Device Power Management States (D-States) of a Function
5.3.1.1. D0 State
5.3.1.2. D1 State
5.3.1.3. D2 State
5.3.1.4. D3 State
5.3.1.4.1. D3hot State
5.3.1.4.2. D3cold State
5.3.2. PM Software Control of the Link Power Management State
5.3.2.1. Entry into the L1 State
5.3.2.2. Exit from L1 State
5.3.2.3. Entry into the L2/L3 Ready State
5.3.3. Power Management Event Mechanisms
5.3.3.1. Motivation
5.3.3.2. Link Wakeup
5.3.3.2.1. PME Synchronization
5.3.3.3. PM_PME Messages
5.3.3.3.1. PM_PME “Backpressure” Deadlock Avoidance
5.3.3.4. PME Rules
5.3.3.5. PM_PME Delivery State Machine
5.4. Native PCI Express Power Management Mechanisms
5.4.1. Active State Power Management (ASPM)
5.4.1.1. L0s ASPM State
5.4.1.1.1. Entry into the L0s State
5.4.1.1.2. Exit from the L0s State
5.4.1.2. L1 ASPM State
5.4.1.2.1. Entry into the L1 State
5.4.1.2.2. Exit from the L1 State
5.4.1.3. ASPM Configuration
5.4.1.3.1. Software Flow for Enabling or Disabling ASPM
5.5. Auxiliary Power Support
5.5.1. Auxiliary Power Enabling
5.6. Power Management System Messages and DLLPs
6. System Architecture
6.1. Interrupt and PME Support
6.1.1. Rationale for PCI Express Interrupt Model
6.1.2. PCI Compatible INTx Emulation
6.1.3. INTx Emulation Software Model
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support
6.1.5. PME Support
6.1.6. Native PME Software Model
6.1.7. Legacy PME Software Model
6.1.8. Operating System Power Management Notification
6.1.9. PME Routing Between PCI Express and PCI Hierarchies
6.2. Error Signaling and Logging
6.2.1. Scope
6.2.2. Error Classification
6.2.2.1. Correctable Errors
6.2.2.2. Uncorrectable Errors
6.2.2.2.1. Fatal Errors
6.2.2.2.2. Non-Fatal Errors
6.2.3. Error Signaling
6.2.3.1. Completion Status
6.2.3.2. Error Messages
6.2.3.2.1. Uncorrectable Error Severity Programming (Advanced Error Reporting)
6.2.3.2.2. Masking Individual Errors
6.2.3.2.3. Error Pollution
6.2.3.2.4. Advisory Non-Fatal Error Cases
6.2.3.2.4.1. Completer Sending a Completion with UR/CA Status
6.2.3.2.4.2. Intermediate Receiver
6.2.3.2.4.3. Ultimate PCI Express Receiver of a Poisoned TLP
6.2.3.2.4.4. Requester with Completion Timeout
6.2.3.2.4.5. Receiver of an Unexpected Completion
6.2.3.2.5. Requester Receiving a Completion with UR/CA Status
6.2.3.3. Error Forwarding (Data Poisoning)
6.2.4. Error Logging
6.2.4.1. Root Complex Considerations (Advanced Error Reporting)
6.2.4.1.1. Error Source Identification
6.2.4.1.2. Interrupt Generation
6.2.4.2. Multiple Error Handling (Advanced Error Reporting Capability)
6.2.4.3. Advisory Non-Fatal Error Logging
6.2.5. Sequence of Device Error Signaling and Logging Operations
6.2.6. Error Message Controls
6.2.7. Error Listing and Rules
6.2.7.1. Conventional PCI Mapping
6.2.8. Virtual PCI Bridge Error Handling
6.2.8.1. Error Message Forwarding and PCI Mapping for Bridge - Rules
6.3. Virtual Channel Support
6.3.1. Introduction and Scope
6.3.2. TC/VC Mapping and Example Usage
6.3.3. VC Arbitration
6.3.3.1. Traffic Flow and Switch Arbitration Model
6.3.3.2. VC Arbitration ( Arbitration Between VCs
6.3.3.2.1. Strict Priority Arbitration Model
6.3.3.2.2. Round Robin Arbitration Model
6.3.3.3. Port Arbitration ( Arbitration Within VC
6.3.3.4. Multi-Function Devices and Function Arbitration
6.3.4. Isochronous Support
6.3.4.1. Rules for Software Configuration
6.3.4.2. Rules for Requesters
6.3.4.3. Rules for Completers
6.3.4.4. Rules for Switches and Root Complexes
6.3.4.5. Rules for Multi-Function Devices
6.4. Device Synchronization
6.5. Locked Transactions
6.5.1. Introduction
6.5.2. Initiation and Propagation of Locked Transactions - Rules
6.5.3. Switches and Lock - Rules
6.5.4. PCI Express/PCI Bridges and Lock - Rules
6.5.5. Root Complex and Lock - Rules
6.5.6. Legacy Endpoints
6.5.7. PCI Express Endpoints
6.6. PCI Express Reset - Rules
6.6.1. Conventional Reset
6.6.2. Function-Level Reset (FLR)
6.7. PCI Express Hot-Plug Support
6.7.1. Elements of Hot-Plug
6.7.1.1. Indicators
6.7.1.1.1. Attention Indicator
6.7.1.1.2. Power Indicator
6.7.1.2. Manually-operated Retention Latch (MRL)
6.7.1.3. MRL Sensor
6.7.1.4. Electromechanical Interlock
6.7.1.5. Attention Button
6.7.1.6. Software User Interface
6.7.1.7. Slot Numbering
6.7.1.8. Power Controller
6.7.2. Registers Grouped by Hot-Plug Element Association
6.7.2.1. Attention Button Registers
6.7.2.2. Attention Indicator Registers
6.7.2.3. Power Indicator Registers
6.7.2.4. Power Controller Registers
6.7.2.5. Presence Detect Registers
6.7.2.6. MRL Sensor Registers
6.7.2.7. Electromechanical Interlock Registers
6.7.2.8. Command Completed Registers
6.7.2.9. Port Capabilities and Slot Information Registers
6.7.2.10. Hot-Plug Interrupt Control Register
6.7.3. PCI Express Hot-Plug Events
6.7.3.1. Slot Events
6.7.3.2. Command Completed Events
6.7.3.3. Data Link Layer State Changed Events
6.7.3.4. Software Notification of Hot-Plug Events
6.7.4. Firmware Support for Hot-Plug
6.8. Power Budgeting Capability
6.8.1. System Power Budgeting Process Recommendations
6.9. Slot Power Limit Control
6.10. Root Complex Topology Discovery
6.11. Link Speed Management
6.12. Access Control Services (ACS)
6.12.1. ACS Component Capability Requirements
6.12.1.1. ACS Downstream Ports
6.12.1.2. ACS Functions in Multi-Function Devices
6.12.1.3. Functions in Single-Function Devices
6.12.2. Interoperability
6.12.3. ACS Peer-to-Peer Control Interactions
6.12.4. ACS Violation Error Handling
6.12.5. ACS Redirection Impacts on Ordering Rules
6.12.5.1. Completions Passing Posted Requests
6.12.5.2. Requests Passing Posted Requests
7. Software Initialization and Configuration
7.1. Configuration Topology
7.2. PCI Express Configuration Mechanisms
7.2.1. PCI 3.0 Compatible Configuration Mechanism
7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM)
7.2.2.1. Host Bridge Requirements
7.2.2.2. PCI Express Device Requirements
7.2.3. Root Complex Register Block
7.3. Configuration Transaction Rules
7.3.1. Device Number
7.3.2. Configuration Transaction Addressing
7.3.3. Configuration Request Routing Rules
7.3.4. PCI Special Cycles
7.4. Configuration Register Types
7.5. PCI-Compatible Configuration Registers
7.5.1. Type 0/1 Common Configuration Space
7.5.1.1. Command Register (Offset 04h)
7.5.1.2. Status Register (Offset 06h)
7.5.1.3. Cache Line Size Register (Offset 0Ch)
7.5.1.4. Latency Timer Register (Offset 0Dh)
7.5.1.5. Interrupt Line Register (Offset 3Ch)
7.5.1.6. Interrupt Pin Register (Offset 3Dh)
7.5.1.7. Error Registers
7.5.2. Type 0 Configuration Space Header
7.5.2.1. Base Address Registers (Offset 10h - 24h)
7.5.2.2. Min_Gnt/Max_Lat Registers (Offset 3Eh/3Fh)
7.5.3. Type 1 Configuration Space Header
7.5.3.1. Base Address Registers (Offset 10h/14h)
7.5.3.2. Primary Bus Number (Offset 18h)
7.5.3.3. Secondary Latency Timer (Offset 1Bh)
7.5.3.4. Secondary Status Register (Offset 1Eh)
7.5.3.5. Prefetchable Memory Base/Limit (Offset 24h)
7.5.3.6. Bridge Control Register (Offset 3Eh)
7.6. PCI Power Management Capability Structure
7.7. MSI and MSI-X Capability Structures
7.8. PCI Express Capability Structure
7.8.1. PCI Express Capability List Register (Offset 00h)
7.8.2. PCI Express Capabilities Register (Offset 02h)
7.8.3. Device Capabilities Register (Offset 04h)
7.8.4. Device Control Register (Offset 08h)
7.8.5. Device Status Register (Offset 0Ah)
7.8.6. Link Capabilities Register (Offset 0Ch)
7.8.7. Link Control Register (Offset 10h)
7.8.8. Link Status Register (Offset 12h)
7.8.9. Slot Capabilities Register (Offset 14h)
7.8.10. Slot Control Register (Offset 18h)
7.8.11. Slot Status Register (Offset 1Ah)
7.8.12. Root Control Register (Offset 1Ch)
7.8.13. Root Capabilities Register (Offset 1Eh)
7.8.14. Root Status Register (Offset 20h)
7.8.15. Device Capabilities 2 Register (Offset 24h)
7.8.16. Device Control 2 Register (Offset 28h)
7.8.17. Device Status 2 Register (Offset 2Ah)
7.8.18. Link Capabilities 2 Register (Offset 2Ch)
7.8.19. Link Control 2 Register (Offset 30h)
7.8.20. Link Status 2 Register (Offset 32h)
7.8.21. Slot Capabilities 2 Register (Offset 34h)
7.8.22. Slot Control 2 Register (Offset 38h)
7.8.23. Slot Status 2 Register (Offset 3Ah)
7.9. PCI Express Extended Capabilities
7.9.1. Extended Capabilities in Configuration Space
7.9.2. Extended Capabilities in the Root Complex Register Block
7.9.3. PCI Express Enhanced Capability Header
7.10. Advanced Error Reporting Capability
7.10.1. Advanced Error Reporting Enhanced Capability Header (Offset 00h)
7.10.2. Uncorrectable Error Status Register (Offset 04h)
7.10.3. Uncorrectable Error Mask Register (Offset 08h)
7.10.4. Uncorrectable Error Severity Register (Offset 0Ch)
7.10.5. Correctable Error Status Register (Offset 10h)
7.10.6. Correctable Error Mask Register (Offset 14h)
7.10.7. Advanced Error Capabilities and Control Register (Offset 18h)
7.10.8. Header Log Register (Offset 1Ch)
7.10.9. Root Error Command Register (Offset 2Ch)
7.10.10. Root Error Status Register (Offset 30h)
7.10.11. Error Source Identification Register (Offset 34h)
7.11. Virtual Channel Capability
7.11.1. Virtual Channel Enhanced Capability Header
7.11.2. Port VC Capability Register 1
7.11.3. Port VC Capability Register 2
7.11.4. Port VC Control Register
7.11.5. Port VC Status Register
7.11.6. VC Resource Capability Register
7.11.7. VC Resource Control Register
7.11.8. VC Resource Status Register
7.11.9. VC Arbitration Table
7.11.10. Port Arbitration Table
7.12. Device Serial Number Capability
7.12.1. Device Serial Number Enhanced Capability Header (Offset 00h)
7.12.2. Serial Number Register (Offset 04h)
7.13. PCI Express Root Complex Link Declaration Capability
7.13.1. Root Complex Link Declaration Enhanced Capability Header
7.13.2. Element Self Description
7.13.3. Link Entries
7.13.3.1. Link Description
7.13.3.2. Link Address
7.13.3.2.1. Link Address for Link Type 0
7.13.3.2.2. Link Address for Link Type 1
7.14. PCI Express Root Complex Internal Link Control Capability
7.14.1. Root Complex Internal Link Control Enhanced Capability Header
7.14.2. Root Complex Link Capabilities Register
7.14.3. Root Complex Link Control Register
7.14.4. Root Complex Link Status Register
7.15. Power Budgeting Capability
7.15.1. Power Budgeting Enhanced Capability Header (Offset 00h)
7.15.2. Data Select Register (Offset 04h)
7.15.3. Data Register (Offset 08h)
7.15.4. Power Budget Capability Register (Offset 0Ch)
7.16. ACS Extended Capability
7.16.1. ACS Extended Capability Header (Offset 00h)
7.16.2. ACS Capability Register (Offset 04h)
7.16.3. ACS Control Register (Offset 06h)
7.16.4. Egress Control Vector (Offset 08h)
7.17. PCI Express Root Complex Event Collector Endpoint Association Capability
7.17.1. Root Complex Event Collector Endpoint Association Enhanced Capability Header
7.17.2. Association Bitmap for Root Complex Integrated Endpoints
7.18. Multi-Function Virtual Channel Capability
7.18.1. MFVC Enhanced Capability Header
7.18.2. Port VC Capability Register 1
7.18.3. Port VC Capability Register 2
7.18.4. Port VC Control Register
7.18.5. Port VC Status Register
7.18.6. VC Resource Capability Register
7.18.7. VC Resource Control Register
7.18.8. VC Resource Status Register
7.18.9. VC Arbitration Table
7.18.10. Function Arbitration Table
7.19. Vendor-Specific Capability
7.19.1. Vendor-Specific Enhanced Capability Header (Offset 00h)
7.19.2. Vendor-Specific Header (Offset 04h)
7.20. RCRB Header Capability
7.20.1. RCRB Header Enhanced Capability Header (Offset 00h)
7.20.2. Vendor ID (Offset 04h) and Device ID (Offset 06h)
7.20.3. RCRB Capabilities (Offset 08h)
7.20.4. RCRB Control (Offset 0Ch)
A. Isochronous Applications
A.1. Introduction
A.2. Isochronous Contract and Contract Parameters
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot
A.2.2. Isochronous Payload Size
A.2.3. Isochronous Bandwidth Allocation
A.2.4. Isochronous Transaction Latency
A.2.5. An Example Illustrating Isochronous Parameters
A.3. Isochronous Transaction Rules
A.4. Transaction Ordering
A.5. Isochronous Data Coherency
A.6. Flow Control
A.7. Considerations for Bandwidth Allocation
A.7.1. Isochronous Bandwidth of PCI Express Links
A.7.2. Isochronous Bandwidth of Endpoints
A.7.3. Isochronous Bandwidth of Switches
A.7.4. Isochronous Bandwidth of Root Complex
A.8. Considerations for PCI Express Components
A.8.1. An Endpoint as a Requester
A.8.2. An Endpoint as a Completer
A.8.3. Switches
A.8.4. Root Complex
B. Symbol Encoding
C. Physical Layer Appendix
C.1. Data Scrambling
D. Request Dependencies
Acknowledgements
PCI Express®
Base Specification
Revision 2.0
December 20, 2006
Revision
1.0
1.0a
1.1
2.0
Revision History
Initial release.
Incorporated Errata C1-C66 and E1-E4.17.
Incorporated approved Errata and ECNs.
Added 5.0 GT/s data rate and incorporated approved Errata
and ECNs.
DATE
07/22/02
04/15/03
03/28/05
12/20/06
PCI-SIG® disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be
forwarded to:
Membership Services
www.pcisig.com
E-mail:
Phone:
Fax:
Technical Support
techsupp@pcisig.com
administration@pcisig.com
503-619-0569
503-644-6708
DISCLAIMER
This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including
any warranty of merchantability, noninfringement, fitness for any particular purpose, or any
warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all
liability for infringement of proprietary rights, relating to use of information in this specification.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is
granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Copyright © 2002-2006 PCI-SIG
2
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
Contents
OBJECTIVE OF THE SPECIFICATION.................................................................................... 21
DOCUMENT ORGANIZATION ................................................................................................ 21
DOCUMENTATION CONVENTIONS...................................................................................... 22
TERMS AND ACRONYMS........................................................................................................ 23
REFERENCE DOCUMENTS...................................................................................................... 29
1.
1.4.
1.5.
1.5.1.
1.5.2.
1.5.3.
1.5.4.
1.3.1.
1.3.2.
1.3.3.
1.3.4.
1.3.5.
INTRODUCTION ................................................................................................................ 31
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 31
PCI EXPRESS LINK......................................................................................................... 33
1.2.
1.3.
PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 35
Root Complex........................................................................................................ 35
Endpoints .............................................................................................................. 36
Switch.................................................................................................................... 39
Root Complex Event Collector.............................................................................. 40
PCI Express to PCI/PCI-X Bridge........................................................................ 40
PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 40
PCI EXPRESS LAYERING OVERVIEW.............................................................................. 41
Transaction Layer................................................................................................. 42
Data Link Layer .................................................................................................... 42
Physical Layer ...................................................................................................... 43
Layer Functions and Services............................................................................... 43
2. TRANSACTION LAYER SPECIFICATION ..................................................................... 47
TRANSACTION LAYER OVERVIEW.................................................................................. 47
Address Spaces, Transaction Types, and Usage................................................... 48
Packet Format Overview ...................................................................................... 50
TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 51
Common Packet Header Fields ............................................................................ 51
2.2.1.
TLPs with Data Payloads - Rules ......................................................................... 54
2.2.2.
TLP Digest Rules .................................................................................................. 56
2.2.3.
Routing and Addressing Rules.............................................................................. 56
2.2.4.
First/Last DW Byte Enables Rules........................................................................ 59
2.2.5.
2.2.6.
Transaction Descriptor......................................................................................... 61
2.2.7. Memory, I/O, and Configuration Request Rules................................................... 66
2.2.8. Message Request Rules......................................................................................... 69
2.2.9.
Completion Rules.................................................................................................. 80
2.3. HANDLING OF RECEIVED TLPS...................................................................................... 82
Request Handling Rules........................................................................................ 85
2.1.
2.2.
2.1.1.
2.1.2.
2.3.1.
3
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
2.3.2.
2.4.
2.5.1.
2.5.2.
2.5.3.
2.6.1.
2.7.1.
2.7.2.
2.4.1.
2.4.2.
2.4.3.
Completion Handling Rules.................................................................................. 98
TRANSACTION ORDERING............................................................................................ 100
Transaction Ordering Rules ............................................................................... 100
Update Ordering and Granularity Observed by a Read Transaction................ 104
Update Ordering and Granularity Provided by a Write Transaction ................ 105
2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 105
Virtual Channel Identification (VC ID) .............................................................. 108
TC to VC Mapping.............................................................................................. 109
VC and TC Rules................................................................................................. 110
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 111
Flow Control Rules............................................................................................. 112
2.7. DATA INTEGRITY ......................................................................................................... 122
ECRC Rules ........................................................................................................ 123
Error Forwarding ............................................................................................... 127
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 129
LINK STATUS DEPENDENCIES ...................................................................................... 130
2.9.
Transaction Layer Behavior in DL_Down Status............................................... 130
Transaction Layer Behavior in DL_Up Status ................................................... 131
3. DATA LINK LAYER SPECIFICATION.......................................................................... 133
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 133
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 135
Data Link Control and Management State Machine Rules ................................ 136
FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 138
Flow Control Initialization State Machine Rules ............................................... 138
3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 142
Data Link Layer Packet Rules ............................................................................ 142
3.5. DATA INTEGRITY ......................................................................................................... 147
Introduction......................................................................................................... 147
LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 147
LCRC and Sequence Number (TLP Receiver).................................................... 159
4. PHYSICAL LAYER SPECIFICATION ............................................................................ 167
INTRODUCTION ............................................................................................................ 167
LOGICAL SUB-BLOCK................................................................................................... 167
Symbol Encoding ................................................................................................ 168
4.2.1.
Framing and Application of Symbols to Lanes................................................... 171
4.2.2.
Data Scrambling ................................................................................................. 174
4.2.3.
Link Initialization and Training.......................................................................... 176
4.2.4.
Link Training and Status State Machine (LTSSM) Descriptions........................ 188
4.2.5.
Link Training and Status State Rules.................................................................. 192
4.2.6.
Clock Tolerance Compensation.......................................................................... 237
4.2.7.
4.2.8.
Compliance Pattern ............................................................................................ 239
4.2.9. Modified Compliance Pattern............................................................................. 240
ELECTRICAL SUB-BLOCK ............................................................................................. 241
4.3.1. Maintaining Backwards Compatibility............................................................... 241
4.3.2.
Jitter Budgeting and Measurement..................................................................... 243
3.5.1.
3.5.2.
3.5.3.
3.3.
3.2.1.
3.3.1.
4.1.
4.2.
2.9.1.
2.9.2.
3.4.1.
4.3.
4
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
5.1.1.
5.2.
5.3.
6.2.
5.6.
6.1.
5.3.1.
5.3.2.
5.3.3.
5.4.1.
5.5.1.
4.3.3.
4.3.4.
4.3.5.
4.3.6.
4.3.7.
Transmitter Specification.................................................................................... 244
Receiver Specification......................................................................................... 259
Transmitter and Receiver DC Specifications...................................................... 273
Channel Specifications........................................................................................ 278
Reference Clock Specifications........................................................................... 285
5. POWER MANAGEMENT................................................................................................. 293
5.1. OVERVIEW ................................................................................................................... 293
Statement of Requirements.................................................................................. 294
LINK STATE POWER MANAGEMENT............................................................................. 294
PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 299
Device Power Management States (D-States) of a Function.............................. 299
PM Software Control of the Link Power Management State.............................. 303
Power Management Event Mechanisms ............................................................. 308
5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 315
Active State Power Management (ASPM) .......................................................... 315
5.5. AUXILIARY POWER SUPPORT....................................................................................... 331
Auxiliary Power Enabling................................................................................... 331
POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 332
6. SYSTEM ARCHITECTURE ............................................................................................. 335
INTERRUPT AND PME SUPPORT................................................................................... 335
Rationale for PCI Express Interrupt Model........................................................ 335
6.1.1.
PCI Compatible INTx Emulation........................................................................ 336
6.1.2.
6.1.3.
INTx Emulation Software Model ........................................................................ 336
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 336
6.1.5.
PME Support....................................................................................................... 338
Native PME Software Model .............................................................................. 338
6.1.6.
Legacy PME Software Model ............................................................................. 339
6.1.7.
6.1.8.
Operating System Power Management Notification........................................... 339
PME Routing Between PCI Express and PCI Hierarchies ................................ 339
6.1.9.
ERROR SIGNALING AND LOGGING................................................................................ 340
Scope................................................................................................................... 340
Error Classification ............................................................................................ 340
Error Signaling ................................................................................................... 342
Error Logging ..................................................................................................... 349
Sequence of Device Error Signaling and Logging Operations .......................... 352
Error Message Controls ..................................................................................... 354
Error Listing and Rules ...................................................................................... 355
Virtual PCI Bridge Error Handling.................................................................... 359
6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 360
Introduction and Scope....................................................................................... 360
TC/VC Mapping and Example Usage................................................................. 361
VC Arbitration .................................................................................................... 363
Isochronous Support ........................................................................................... 371
6.4. DEVICE SYNCHRONIZATION......................................................................................... 374
6.5.
LOCKED TRANSACTIONS.............................................................................................. 375
6.2.1.
6.2.2.
6.2.3.
6.2.4.
6.2.5.
6.2.6.
6.2.7.
6.2.8.
6.3.1.
6.3.2.
6.3.3.
6.3.4.
5
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
6.6.
6.7.
6.6.1.
6.6.2.
6.8.
6.9.
6.10.
6.11.
6.12.
6.7.1.
6.7.2.
6.7.3.
6.7.4.
6.5.1.
6.5.2.
6.5.3.
6.5.4.
6.5.5.
6.5.6.
6.5.7.
Introduction......................................................................................................... 375
Initiation and Propagation of Locked Transactions - Rules............................... 376
Switches and Lock - Rules................................................................................... 377
PCI Express/PCI Bridges and Lock - Rules ....................................................... 377
Root Complex and Lock - Rules.......................................................................... 378
Legacy Endpoints................................................................................................ 378
PCI Express Endpoints ....................................................................................... 378
PCI EXPRESS RESET - RULES....................................................................................... 378
Conventional Reset ............................................................................................. 378
Function-Level Reset (FLR)................................................................................ 381
PCI EXPRESS HOT-PLUG SUPPORT .............................................................................. 384
Elements of Hot-Plug.......................................................................................... 385
Registers Grouped by Hot-Plug Element Association........................................ 391
PCI Express Hot-Plug Events............................................................................. 393
Firmware Support for Hot-Plug ......................................................................... 396
POWER BUDGETING CAPABILITY................................................................................. 396
System Power Budgeting Process Recommendations......................................... 397
SLOT POWER LIMIT CONTROL ..................................................................................... 397
ROOT COMPLEX TOPOLOGY DISCOVERY................................................................. 400
LINK SPEED MANAGEMENT ..................................................................................... 402
ACCESS CONTROL SERVICES (ACS) ........................................................................ 403
6.12.1. ACS Component Capability Requirements ......................................................... 404
6.12.2.
Interoperability ................................................................................................... 408
6.12.3. ACS Peer-to-Peer Control Interactions.............................................................. 408
6.12.4. ACS Violation Error Handling ........................................................................... 409
6.12.5. ACS Redirection Impacts on Ordering Rules ..................................................... 410
7. SOFTWARE INITIALIZATION AND CONFIGURATION............................................ 413
7.1. CONFIGURATION TOPOLOGY........................................................................................ 413
7.2.
PCI EXPRESS CONFIGURATION MECHANISMS ............................................................. 414
PCI 3.0 Compatible Configuration Mechanism ................................................. 415
PCI Express Enhanced Configuration Access Mechanism (ECAM).................. 416
Root Complex Register Block ............................................................................. 420
7.3. CONFIGURATION TRANSACTION RULES....................................................................... 421
Device Number.................................................................................................... 421
Configuration Transaction Addressing............................................................... 422
Configuration Request Routing Rules................................................................. 422
PCI Special Cycles.............................................................................................. 423
7.4. CONFIGURATION REGISTER TYPES .............................................................................. 424
PCI-COMPATIBLE CONFIGURATION REGISTERS........................................................... 425
7.5.
Type 0/1 Common Configuration Space............................................................. 426
Type 0 Configuration Space Header................................................................... 432
Type 1 Configuration Space Header................................................................... 434
7.6.
PCI POWER MANAGEMENT CAPABILITY STRUCTURE.................................................. 438
7.7. MSI AND MSI-X CAPABILITY STRUCTURES................................................................ 439
PCI EXPRESS CAPABILITY STRUCTURE........................................................................ 440
7.8.
PCI Express Capability List Register (Offset 00h)............................................. 441
7.2.1.
7.2.2.
7.2.3.
7.3.1.
7.3.2.
7.3.3.
7.3.4.
7.5.1.
7.5.2.
7.5.3.
6.8.1.
7.8.1.
6
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
PCI Express Capabilities Register (Offset 02h) ................................................. 442
7.8.2.
Device Capabilities Register (Offset 04h) .......................................................... 444
7.8.3.
Device Control Register (Offset 08h) ................................................................. 449
7.8.4.
Device Status Register (Offset 0Ah).................................................................... 455
7.8.5.
Link Capabilities Register (Offset 0Ch).............................................................. 458
7.8.6.
Link Control Register (Offset 10h) ..................................................................... 462
7.8.7.
Link Status Register (Offset 12h) ........................................................................ 469
7.8.8.
Slot Capabilities Register (Offset 14h) ............................................................... 472
7.8.9.
Slot Control Register (Offset 18h) ...................................................................... 474
7.8.10.
7.8.11.
Slot Status Register (Offset 1Ah)......................................................................... 478
7.8.12. Root Control Register (Offset 1Ch) .................................................................... 480
7.8.13. Root Capabilities Register (Offset 1Eh) ............................................................. 482
7.8.14. Root Status Register (Offset 20h)........................................................................ 482
7.8.15. Device Capabilities 2 Register (Offset 24h) ....................................................... 483
7.8.16. Device Control 2 Register (Offset 28h) .............................................................. 485
7.8.17. Device Status 2 Register (Offset 2Ah)................................................................. 487
7.8.18. Link Capabilities 2 Register (Offset 2Ch)........................................................... 487
7.8.19. Link Control 2 Register (Offset 30h) .................................................................. 487
7.8.20. Link Status 2 Register (Offset 32h) ..................................................................... 492
Slot Capabilities 2 Register (Offset 34h) ............................................................ 492
7.8.21.
Slot Control 2 Register (Offset 38h) ................................................................... 492
7.8.22.
Slot Status 2 Register (Offset 3Ah)...................................................................... 492
7.8.23.
PCI EXPRESS EXTENDED CAPABILITIES....................................................................... 493
Extended Capabilities in Configuration Space................................................... 493
Extended Capabilities in the Root Complex Register Block............................... 493
PCI Express Enhanced Capability Header......................................................... 494
ADVANCED ERROR REPORTING CAPABILITY........................................................... 495
7.10.1. Advanced Error Reporting Enhanced Capability Header (Offset 00h).............. 496
7.10.2. Uncorrectable Error Status Register (Offset 04h).............................................. 497
7.10.3. Uncorrectable Error Mask Register (Offset 08h)............................................... 498
7.10.4. Uncorrectable Error Severity Register (Offset 0Ch).......................................... 499
7.10.5. Correctable Error Status Register (Offset 10h).................................................. 501
7.10.6. Correctable Error Mask Register (Offset 14h)................................................... 502
7.10.7. Advanced Error Capabilities and Control Register (Offset 18h) ....................... 503
7.10.8. Header Log Register (Offset 1Ch) ...................................................................... 504
7.10.9. Root Error Command Register (Offset 2Ch) ...................................................... 505
7.10.10.
Root Error Status Register (Offset 30h).......................................................... 506
Error Source Identification Register (Offset 34h) .......................................... 509
7.10.11.
VIRTUAL CHANNEL CAPABILITY ............................................................................. 510
7.11.1. Virtual Channel Enhanced Capability Header................................................... 512
7.11.2. Port VC Capability Register 1 ............................................................................ 513
7.11.3. Port VC Capability Register 2 ............................................................................ 514
7.11.4. Port VC Control Register.................................................................................... 515
7.11.5. Port VC Status Register ...................................................................................... 516
7.11.6. VC Resource Capability Register ....................................................................... 517
7.11.7. VC Resource Control Register............................................................................ 519
7.9.1.
7.9.2.
7.9.3.
7.11.
7.9.
7.10.
7
PCI EXPRESS BASE SPECIFICATION, REV. 2.0
7.15.
7.16.
7.12.
7.13.
7.14.
7.11.8. VC Resource Status Register .............................................................................. 521
7.11.9. VC Arbitration Table .......................................................................................... 522
7.11.10.
Port Arbitration Table .................................................................................... 523
DEVICE SERIAL NUMBER CAPABILITY..................................................................... 525
7.12.1. Device Serial Number Enhanced Capability Header (Offset 00h)..................... 526
Serial Number Register (Offset 04h)................................................................... 527
7.12.2.
PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ............................ 527
7.13.1. Root Complex Link Declaration Enhanced Capability Header ......................... 529
7.13.2. Element Self Description..................................................................................... 530
7.13.3. Link Entries......................................................................................................... 531
PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY................... 535
7.14.1. Root Complex Internal Link Control Enhanced Capability Header .................. 535
7.14.2. Root Complex Link Capabilities Register........................................................... 536
7.14.3. Root Complex Link Control Register.................................................................. 538
7.14.4. Root Complex Link Status Register..................................................................... 540
POWER BUDGETING CAPABILITY............................................................................. 541
7.15.1. Power Budgeting Enhanced Capability Header (Offset 00h)............................. 541
7.15.2. Data Select Register (Offset 04h) ....................................................................... 542
7.15.3. Data Register (Offset 08h).................................................................................. 542
7.15.4. Power Budget Capability Register (Offset 0Ch)................................................. 545
ACS EXTENDED CAPABILITY .................................................................................. 545
7.16.1. ACS Extended Capability Header (Offset 00h) .................................................. 546
7.16.2. ACS Capability Register (Offset 04h)................................................................. 546
7.16.3. ACS Control Register (Offset 06h) ..................................................................... 548
7.16.4. Egress Control Vector (Offset 08h) .................................................................... 549
7.17.
CAPABILITY ............................................................................................................................. 551
PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION
7.17.1. Root Complex Event Collector Endpoint Association Enhanced Capability
Header
............................................................................................................................. 551
7.17.2. Association Bitmap for Root Complex Integrated Endpoints............................. 552
7.18. MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY................................................ 552
7.18.1. MFVC Enhanced Capability Header.................................................................. 553
7.18.2. Port VC Capability Register 1 ............................................................................ 554
7.18.3. Port VC Capability Register 2 ............................................................................ 556
7.18.4. Port VC Control Register.................................................................................... 557
7.18.5. Port VC Status Register ...................................................................................... 558
7.18.6. VC Resource Capability Register ....................................................................... 558
7.18.7. VC Resource Control Register............................................................................ 560
7.18.8. VC Resource Status Register .............................................................................. 562
7.18.9. VC Arbitration Table .......................................................................................... 563
7.18.10.
Function Arbitration Table............................................................................. 563
VENDOR-SPECIFIC CAPABILITY ............................................................................... 565
7.19.1. Vendor-Specific Enhanced Capability Header (Offset 00h)............................... 566
7.19.2. Vendor-Specific Header (Offset 04h).................................................................. 567
RCRB HEADER CAPABILITY ................................................................................... 568
7.20.1. RCRB Header Enhanced Capability Header (Offset 00h) ................................. 568
7.19.
7.20.
8
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