Table of Contents
List of Figures
List of Tables
1 Introduction
1.1 About XWAY™ PHY11G
1.2 Overview
1.2.1 Logic Symbol
1.2.2 Features
1.2.3 Typical Applications
1.2.3.1 Copper Application
1.2.3.2 Media Converter Application
1.2.3.3 Gigabit Interface Converter (GBIC) Application
1.2.4 Terminology and Nomenclature
2 External Signals
2.1 Pin Diagram
2.2 Pin Description
2.2.1 Pin Identifications
2.2.2 General Pins
2.2.3 Media-Dependent Interface (MDI) Pins
2.2.4 Media-Independent Interface (MII) Pins
2.2.5 Control Interface Pins
2.2.6 JTAG Interface
2.2.7 Power Supply Pins
3 Functional Description
3.1 Modes of Operation
3.1.1 Copper Flow
3.1.2 Media Converter Flow
3.2 Media-Independent Interfaces (MII)
3.2.1 X-speed Media-Independent Interface (xMII)
3.2.1.1 xMII Signal Multiplexing
3.2.1.2 xMII Signal Conditioning
3.2.2 Reduced Media-Independent Interface (RMII)
3.2.3 Reduced Gigabit Media-Independent Interface (RGMII)
3.2.4 Serial Gigabit Media-Independent Interface (SGMII)
3.2.5 Reduced Ten Bit Interface (RTBI)
3.3 Media Functions
3.3.1 Media-Dependent Interfaces (MDI)
3.3.1.1 Copper Interface
3.3.1.2 Fiber Interface
3.3.2 Auto-Negotiation
3.3.3 Auto-Downspeed
3.3.4 Auto-Crossover and Polarity-Reversal Correction
3.3.5 Transformerless Ethernet (TLE)
3.4 Configuration, Control and Status Functions
3.4.1 Configuration of XWAY™ PHY11G via Pin-Strapping
3.4.2 Configuration of XWAY™ PHY11G via External EEPROM
3.4.2.1 EEPROM Applications
3.4.2.2 EEPROM Detection
3.4.2.3 EEPROM Content
3.4.2.4 EEPROM Frame Formats
3.4.3 Configuration and Control Via MDIO
3.4.3.1 MDIO Interface
3.4.3.2 MDIO Address Space
3.4.3.3 MDIO Interrupt
3.4.4 LED Interface
3.4.4.1 Single Color LED Mode
3.4.4.2 Bi-Color LED Mode
3.4.4.3 LED Operations
3.5 Power Management
3.5.1 Power Supply
3.5.1.1 Power Supply Using Integrated Switching Regulator
3.5.1.2 Power Supply Without Using Integrated Switching Regulator
3.5.2 Power Over Ethernet (PoE)
3.5.2.1 Powered Device (PD)
3.5.2.2 Power Sourcing Equipment (PSE)
3.5.3 Energy-Efficient Ethernet
3.5.3.1 EEE for 10BASE-Te
3.5.3.2 EEE for 100BASE-TX
3.5.3.3 EEE for 1000BASE-T
3.5.3.4 Auto-Negotiation for EEE Modes
3.5.3.5 Support of Legacy MACs
3.5.4 Wake-on-LAN (WoL)
3.5.5 Power Down Modes
3.5.5.1 PD_FORCE Mode
3.5.5.2 ANEG Mode
3.5.5.3 PD_IDLE Mode
3.5.5.4 DATA Mode
3.5.5.5 EEE Mode
3.6 Testing Functions
3.6.1 JTAG Interface
3.6.2 Payload Data Tests
3.6.2.1 Test Packet Generator (TPG)
3.6.2.2 Error Counters
3.6.3 Test Loops
3.6.3.1 Near-End Test Loops
3.6.3.2 Far-End Test Loop
4 MDIO Registers
4.1 STD: Standard Management Registers
4.2 PHY: PHY-Specific Management Registers
5 MMD Registers
5.1 EEE: Standard EEE Registers for MMD=0x03
5.2 ANEG: Standard Auto-Negotiation Registers for MMD=0x07
5.3 EEPROM: EEPROM Address Space (MMD=0x1E)
5.4 INTERNAL: Internal Address Space (MMD=0x1F)
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
6.2 Operating Range
6.3 Recommended Operating Conditions
6.4 Power-Up Sequence
6.5 DC Characteristics
6.5.1 Digital Interfaces
6.5.1.1 GPIO Interfaces
6.5.1.2 MII Receive Interface
6.5.1.3 MII Transmit Interface
6.5.1.4 LED Interface
6.5.1.5 JTAG Interface
6.5.2 Twisted-Pair Interface
6.5.3 SGMII Interface
6.5.4 1000BASE-X Interface
6.6 AC Characteristics
6.6.1 Reset
6.6.2 Power Supply
6.6.3 Input Clock
6.6.4 Output Clock
6.6.5 MDIO Interface
6.6.6 RMII Interface
6.6.7 RGMII Interface
6.6.7.1 Transmit Timing Characteristics
6.6.7.2 Receive Timing Characteristics
6.6.8 RTBI Interface
6.6.8.1 Transmit Timing Characteristics
6.6.8.2 Receive Timing Characteristics
6.6.9 SGMII Interface
6.6.9.1 Transmit Timing Characteristics
6.6.9.2 Receive Timing Characteristics
6.6.10 1000BASE-X Interface
6.6.10.1 Transmit Timing Characteristics
6.6.10.2 Receive Timing Characteristics
6.6.11 Twisted-Pair Interface
6.7 Isolation Requirements
6.8 External Circuitry
6.8.1 Crystal
6.8.2 LED
6.8.3 Transformer (Magnetics)
6.8.4 RJ45 Plug
6.8.5 Twisted-Pair Common-Mode Rejection and Termination Circuitry
6.8.6 SGMII Interface
6.8.7 1000BASE-X Interface
7 Package Outline
References
Terminology