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FlexRay 总线协议.pdf
Disclaimer
Chapter 1 Introduction
1.1 Scope
1.2 References
1.2.1 FlexRay consortium documents
[EPL10]
[EPLAN10]
[PCT10]
1.2.2 Non-consortium documents
[Cas93]
[Koo02]
[Ung09]
[Wad01]
[Wel88]
[Z100]
1.3 Revision history
Table 1-1: Revision history
1.4 Terms and definitions
application data
bus
bus driver
channel
channel idle
clique
cluster
coldstart node
communication channel
communication controller (CC)
communication cycle
communication slot
cycle-dependent slot assignment
cycle-independent slot assignment
cycle number
cycle time
dynamic segment
dynamic slot / dynamic communication slot
frame
frame identifier
gateway
global time
Hamming distance
host
implementation dependent
key slot
macrotick
microtick
minislot
non-coldstart node
non-sync node
non-synchronized operation
network
network topology
node
null frame
physical communication link
precision
slot
slot ID (identifier)
slot multiplexing
slot number
star
startup frame
static slot / static communication slot
static segment
sync frame
synchronized operation
time gateway
time gateway interface
time gateway sink node
time gateway source node
time sink cluster
time source cluster
transmission slot assignment list
TT-D cluster
TT-D coldstart node
TT-D non-coldstart sync node
TT-D synchronization method
TT-E cluster
TT-E coldstart node
TT-E synchronization method
TT-L cluster
TT-L coldstart node
TT-L synchronization method
1.5 Acronyms and abbreviations
1.6 Notational conventions
1.6.1 Parameter prefix conventions
Table 1-2: Parameter prefix 1.
Table 1-3: Parameter prefix 2.
1.6.2 Color coding
1.6.3 Implementation dependent behavior
1.7 SDL conventions
1.7.1 General
1.7.2 SDL notational conventions
1.7.3 SDL extensions
1.7.3.1 Microtick, macrotick and sample tick timers
1.7.3.2 Microtick behavior of the 'now' - expression
1.7.3.3 Channel-specific process replication
1.7.3.4 Handling of priority input symbols
1.7.3.5 Signals to non-instantiated processes
1.7.3.6 Exported and imported signals
1.8 Bit rates
1.9 Roles of a node in a FlexRay cluster
1.10 Synchronization methods
1.10.1 TT-D synchronization method
Figure 1-1: TT-D cluster.
1.10.2 TT-L synchronization method
Figure 1-2: TT-L cluster.
1.10.3 TT-E synchronization method
Figure 1-3: Time synchronized cluster pair.
Figure 1-4: TT-E cluster.
1.11 Network topology considerations
1.11.1 Passive bus topology
Figure 1-5: Dual channel bus configuration.
1.11.2 Active star topology
Figure 1-6: Dual channel single star configuration.
Figure 1-7: Single channel cascaded star configuration.
Figure 1-8: Dual channel cascaded star configuration.
1.11.3 Active star topology combined with a passive bus topology
Figure 1-9: Single channel hybrid example.
Figure 1-10: Dual channel hybrid example.
1.12 Example node architecture
1.12.1 Objective
1.12.2 Overview
Figure 1-11: Logical interfaces.
1.12.3 Host - communication controller interface
Figure 1-12: Host - communication controller interfaces.
1.12.4 Communication controller - bus driver interface
Figure 1-13: Communication controller - bus driver interface.
1.12.5 Bus driver - host interface
1.12.5.1 Hard wired signals (option A)
Figure 1-14: Example bus driver - host interface (option A).
1.12.5.2 Serial peripheral interface (SPI) (option B)
Figure 1-15: Example bus driver - host interface (option B).
1.12.6 Bus driver - power supply interface (optional)
Figure 1-16: Bus driver - power supply interface.
1.12.7 Time gateway interface
Figure 1-17: Time gateway interface.
1.13 Testability requirements
Chapter 2 Protocol Operation Control
2.1 Principles
2.1.1 Communication controller power moding
Figure 2-1: Power moding of the communication controller.
2.2 Description
Figure 2-2: Protocol operation control context.
2.2.1 Operational overview
2.2.1.1 Host commands
Table 2-1: CHI host command summary.
2.2.1.2 Error conditions
2.2.1.2.1 Errors causing immediate entry to the POC:halt state
2.2.1.2.2 Errors handled by the degradation model
2.2.1.3 POC status
Definition 2-1: Formal definition of T_POCStatus.
Definition 2-2: Formal definition of T_POCState.
Definition 2-3: Formal definition of T_SlotMode.
Definition 2-4: Formal definition of T_ErrorMode.
Definition 2-5: Formal definition of T_WakeupStatus.
Definition 2-6: Formal definition of T_StartupState.
2.2.1.4 SDL considerations for single channel nodes
2.3 The protocol operation control process
Figure 2-3: Overview of protocol operation control.
2.3.1 POC SDL utilities
Figure 2-4: Macros to mode the core mechanisms for transitions to the POC:ready and POC:halt states [POC].
Figure 2-5: Macros for creating and terminating processes [POC].
2.3.2 SDL organization
2.3.3 Preempting commands
Figure 2-6: POC preempting immediate commands [POC].
2.3.4 Deferred commands
2.3.4.1 DEFERRED_HALT, DEFERRED_READY and CLEAR_DEFERRED commands
Figure 2-7: POC preempting deferred commands [POC].
Figure 2-8: Macro to handle deferred CHI commands [POC].
Figure 2-9: Cancelation of deferred commands [POC].
2.3.4.2 ALL_SLOTS command
Figure 2-10: Capture of the ALL_SLOTS command for end-of-cycle processing [POC].
2.3.5 Reaching the POC:ready state
Figure 2-11: Reaching the POC:ready state [POC].
2.3.5.1 Default configuration requirements
2.3.6 Reaching the POC:normal active state
Figure 2-12: POC behavior in preparation for normal operation [POC].
2.3.6.1 Wakeup and startup support
Figure 2-13: Conditions detected in support of the wakeup and startup procedures [POC].
Definition 2-7: Formal definition of T_ChannelBoolArray.
Definition 2-8: Formal definition of T_Channel.
2.3.7 Behavior during normal operation
2.3.7.1 Cyclical behavior
2.3.7.1.1 Cycle counter
Figure 2-14: POC determination of the cycle counter value [POC].
2.3.7.1.2 POC:normal active state
Figure 2-15: Cyclical behavior in the POC:normal active state [POC].
2.3.7.1.3 POC:normal passive state
Figure 2-16: Cyclical behavior in the POC:normal passive state [POC].
2.3.7.1.4 Error checking during normal operation
2.3.7.1.4.1 Error checking overview
2.3.7.1.4.2 Error checking details for the POC:normal active state
Figure 2-17: Error checking in the POC:normal active state [POC].
2.3.7.1.4.3 Error checking details for the POC:normal passive state
Figure 2-18: Error checking in the POC:normal passive state [POC].
Chapter 3 Coding and Decoding
3.1 Principles
3.2 Description
Figure 3-1: Coding / Decoding context.
3.2.1 Frame and symbol encoding
3.2.1.1 Frame encoding
3.2.1.1.1 Transmission start sequence
3.2.1.1.2 Frame start sequence
3.2.1.1.3 Byte start sequence
3.2.1.1.4 Frame end sequence
3.2.1.1.5 Dynamic trailing sequence
3.2.1.1.6 Frame bit stream assembly
Figure 3-2: Frame encoding in the static segment.
Figure 3-3: Frame encoding in the dynamic segment.
3.2.1.2 Symbol encoding
3.2.1.2.1 Collision avoidance symbol and media access test symbol
Figure 3-4: CAS and MTS symbol encoding.
3.2.1.2.2 Wakeup symbol
Figure 3-5: Wakeup pattern consisting of two wakeup symbols.
Figure 3-6: Wakeup symbol collision and wakeup pattern reception.
3.2.1.2.3 Wakeup During Operation Pattern (WUDOP)
Figure 3-7: Wakeup During Operation Pattern.
3.2.2 Sampling and majority voting
Figure 3-8: Sampling and majority voting of the RxD input (adInternalRxDelay = 1).
3.2.3 Bit clock alignment and bit strobing
Figure 3-9: Bit synchronization.
3.2.4 Implementation specific delays
3.2.5 Channel idle detection
3.2.6 Action point and time reference point
Figure 3-10: TSS length change and propagation.
Figure 3-11: Time reference point definitions.
3.2.7 Frame and symbol decoding
3.2.7.1 Frame decoding
Figure 3-12: Received frame bit stream.
3.2.7.2 Symbol decoding
3.2.7.2.1 Collision avoidance symbol and media access test symbol decoding
Figure 3-13: Received CAS/MTS bit stream.
3.2.7.2.2 Wakeup symbol decoding
3.2.7.3 Decoding error
Figure 3-14: Start of frame with FSS BSS decoding.
3.2.8 Signal integrity
3.3 Coding and decoding process
3.3.1 Operating modes
Definition 3-1: Formal definition of T_CodecMode.
3.3.2 Coding and decoding process behavior
Figure 3-15: CODEC process [CODEC_A].
Figure 3-16: Mode control of the CODEC process [CODEC_A].
Figure 3-17: Termination of the CODEC process [CODEC_A].
3.3.3 Encoding behavior
Definition 3-2: Formal definition of T_TransmitFrame.
Definition 3-3: Formal definition of T_BitLevel.
Definition 3-4: Formal definition of T_BitStreamArray.
Figure 3-18: Encoding mechanism [CODEC_A].
Definition 3-5: Formal definition of T_CEType.
3.3.4 Encoding macros
Figure 3-19: Encoding macro FRAME_ENCODING_A [CODEC_A].
Figure 3-20: Encoding macro TRANSMIT_FES_A [CODEC_A].
Figure 3-21: Encoding macro TRANSMIT_DTS_A [CODEC_A].
Figure 3-22: Procedure WAIT_A [CODEC_A].
Figure 3-23: Encoding macro WUP_ENCODING_A [CODEC_A].
Figure 3-24: Encoding macro CAS_MTS_ENCODING_A [CODEC_A].
Figure 3-25: Encoding macro WUDOP_ENCODING_A [CODEC_A].
3.3.5 Decoding behavior
Figure 3-26: Decoding macro DECODING_A [CODEC_A].
3.3.6 Decoding macros
Definition 3-6: Formal definition of T_ByteArray.
Definition 3-7: Formal definition of T_ByteStreamArray.
Definition 3-8: Formal definition of T_CRCCheckPassed.
Definition 3-9: Formal definition of T_MicrotickTime.
Definition 3-10: Formal definition of T_ReceiveFrame.
Definition 3-11: Formal definition of T_DecodingError.
Figure 3-27: Decoding macro WAIT_FOR_CE_START_A [CODEC_A].
Figure 3-28: Decoding macro TSS_DECODING_A [CODEC_A].
Figure 3-29: Decoding macro CAS_MTS_DECODING_A [CODEC_A].
Figure 3-30: Decoding macro FSS_BSS_DECODING_A [CODEC_A].
Figure 3-31: Decoding macro HEADER_DECODING_A [CODEC_A].
Figure 3-32: Procedure BYTE_DECODING_A [CODEC_A].
Figure 3-33: Procedure BSS_DECODING_A [CODEC_A].
Figure 3-34: Decoding macro FES_DECODING_A [CODEC_A].
Figure 3-35: Decoding macro PAYLOAD_DECODING_A [CODEC_A].
Figure 3-36: Decoding macro TRAILER_DECODING_A [CODEC_A].
Figure 3-37: Decoding macro DTS_DECODING_A [CODEC_A].
3.4 Bit strobing process
3.4.1 Operating modes
Definition 3-12: Formal definition of T_StrbMode.
3.4.2 Bit strobing process behavior
Figure 3-38: BITSTRB process [BITSTRB_A].
Figure 3-39: Wait for voted sample [BITSTRB_A].
Figure 3-40: BITSTRB process control and process termination [BITSTRB_A].
3.5 Wakeup pattern decoding process
3.5.1 Operating modes
Definition 3-13: Formal definition of T_WupDecMode.
3.5.2 Wakeup pattern decoding process behavior
Figure 3-41: Control of the wakeup pattern decoding process and its termination [WUPDEC_A].
Figure 3-42: Control of the wakeup timer [WUPDEC_A].
Figure 3-43: Wakeup pattern decoding [WUPDEC_A].
Chapter 4 Frame Format
4.1 Overview
Figure 4-1: FlexRay frame format.
4.2 FlexRay header segment (5 bytes)
4.2.1 Reserved bit (1 bit)
Definition 4-1: Formal definition of T_Reserved.
4.2.2 Payload preamble indicator (1 bit)
Definition 4-2: Formal definition of T_PPIndicator.
4.2.3 Null frame indicator (1 bit)
Definition 4-3: Formal definition of T_NFIndicator.
4.2.4 Sync frame indicator (1 bit)
Definition 4-4: Formal definition of T_SyFIndicator.
4.2.5 Startup frame indicator (1 bit)
Definition 4-5: Formal definition of T_SuFIndicator.
4.2.6 Frame ID (11 bits)
Definition 4-6: Formal definition of T_FrameID.
4.2.7 Payload length (7 bits)
Definition 4-7: Formal definition of T_Length.
4.2.8 Header CRC (11 bits)
Definition 4-8: Formal definition of T_HeaderCRC.
4.2.9 Cycle count (6 bits)
Definition 4-9: Formal definition of T_CycleCounter.
4.2.10 Formal header definition
Definition 4-10: Formal definition of T_Header.
4.3 FlexRay payload segment (0 - 254 bytes)
Definition 4-11: Formal definition of T_Payload.
4.3.1 NMVector
Figure 4-2: Payload segment of frames transmitted in the static segment.
4.3.2 Message ID (16 bits)
Figure 4-3: Payload segment of frames transmitted in the dynamic segment.
4.4 FlexRay trailer segment
Definition 4-12: Formal definition of T_FrameCRC.
4.5 CRC calculation details
4.5.1 CRC calculation algorithm
4.5.2 Header CRC calculation
4.5.3 Frame CRC calculation
Chapter 5 Media Access Control
5.1 Principles
5.1.1 Communication cycle
Figure 5-1: Timing hierarchy within the communication cycle.
5.1.2 Communication cycle execution
Figure 5-2: Time base triggered communication cycle.
5.1.3 Static segment
5.1.3.1 Structure of the static segment
5.1.3.2 Execution and timing of the static segment
Figure 5-3: Structure of the static segment.
Figure 5-4: Timing within a static slot.
5.1.4 Dynamic segment
5.1.4.1 Structure of the dynamic segment
5.1.4.2 Execution and timing of the dynamic segment
Figure 5-5: Structure of the dynamic segment.
Figure 5-6: Timing within a minislot.
Figure 5-7: Structure of dynamic slots.
Figure 5-8: Timing at the boundary between the static and dynamic segments.
5.1.5 Symbol window
Figure 5-9: Timing within the symbol window.
5.1.6 Network idle time
5.2 Description
Figure 5-10: Media access control context.
5.2.1 Operating modes
Definition 5-1: Formal definition of T_MacMode.
5.2.2 Significant events
5.2.2.1 Reception-related events
Figure 5-11: Reception-related events for MAC.
5.2.2.2 Transmission-related events
Figure 5-12: Transmission-related events for MAC.
5.2.2.3 Timing-related events
5.3 Media access control process
5.3.1 Initialization and MAC:standby state
Figure 5-13: Media access process [MAC_A].
Figure 5-14: Media access control [MAC_A].
Figure 5-15: Termination of the MAC process [MAC_A].
5.3.2 Static segment related states
5.3.2.1 State machine for the static segment media access control
Figure 5-16: Media access in the static segment [MAC_A].
Definition 5-2: Formal definition of T_SlotCounter.
5.3.2.2 Transmission conditions and frame assembly in the static segment
Definition 5-3: Formal definition of T_CHITransmission.
Definition 5-4: Formal definition of T_Assignment.
Figure 5-17: Frame assembly in the static segment [MAC_A].
Figure 5-18: Message copying and padding in the static segment [MAC_A].
5.3.3 Dynamic segment related states
5.3.3.1 State machine for the dynamic segment media access control
Figure 5-19: Media access in the dynamic segment [MAC_A].
Figure 5-20: Channel idle tracking [MAC_A].
Figure 5-21: Media access in the dynamic segment arbitration [MAC_A].
Figure 5-22: Transmission in the dynamic segment macro [MAC_A].
Figure 5-23: Slot counter increase macro [MAC_A].
Figure 5-24: Counting of active bits [MAC_A].
5.3.3.2 Transmission conditions and frame assembly in the dynamic segment
Figure 5-25: Frame assembly in the dynamic segment [MAC_A].
5.3.4 Symbol window related states
Figure 5-26: Media access in the symbol window [MAC_A].
5.3.5 Network idle time
Figure 5-27: Network idle time [MAC_A].
Chapter 6 Frame and Symbol Processing
6.1 Principles
6.2 Description
Figure 6-1: Frame and symbol processing context.
6.2.1 Operating modes
Definition 6-1: Formal definition of T_FspMode.
6.2.2 Significant events
6.2.2.1 Reception-related events
Figure 6-2: Reception-related events for FSP.
6.2.2.2 Decoding-related events
6.2.2.3 Timing-related events
Figure 6-3: Timing-related events for FSP.
6.2.3 Status data
Definition 6-2: Formal definition of T_SlotStatus.
Definition 6-3: Formal definition of T_Segment.
6.3 Frame and symbol processing process
Figure 6-4: State overview of the FSP state machine (shown for one channel).
6.3.1 Initialization and FSP:standby state
Figure 6-5: FSP process [FSP_A].
Figure 6-6: FSP control [FSP_A].
Figure 6-7: Termination of the FSP process [FSP_A].
Figure 6-8: CHI update of a decoded wakeup pattern [FSP_A].
6.3.2 Macro SLOT_SEGMENT_END
Figure 6-9: Slot and segment end macro [FSP_A].
6.3.3 FSP:wait for CE start state
Figure 6-10: Transitions from the FSP:wait for CE start state [FSP_A].
6.3.4 FSP:decoding in progress state
Figure 6-11: Transitions from the FSP:decoding in progress state [FSP_A].
Figure 6-12: Transitions from the FSP:decoding in progress state [FSP_A].
6.3.4.1 Frame reception checks during non-synchronized operation
Figure 6-13: Frame acceptance checks during non-synchronized operation [FSP_A].
6.3.4.2 Frame reception checks during synchronized operation
6.3.4.2.1 Frame reception checks in the static segment
Figure 6-14: Frame reception timing for a static slot.
Figure 6-15: Frame acceptance checks for the static segment [FSP_A].
6.3.4.2.2 Frame reception checks in the dynamic segment
Figure 6-16: Frame reception timing for a dynamic slot.
Figure 6-17: Frame acceptance checks for the dynamic segment [FSP_A].
6.3.5 FSP:wait for CHIRP state
Figure 6-18: Transitions from the FSP:wait for CHIRP state [FSP_A].
6.3.6 FSP:wait for transmission end state
Figure 6-19: Transitions from the FSP:wait for transmission end state [FSP_A].
Chapter 7 Wakeup and Startup
7.1 Cluster wakeup
7.1.1 Principles
7.1.2 Description
Figure 7-1: Protocol operation control context.
7.1.3 Wakeup support by the communication controller
7.1.3.1 Wakeup state diagram
Figure 7-2: Structure of the wakeup state machine [POC].
7.1.3.2 The POC:wakeup listen state
Figure 7-3: Transitions from the POC:wakeup listen state [POC].
7.1.3.3 The POC:wakeup send state
Figure 7-4: Transitions from the POC:wakeup send state [POC].
7.1.3.4 The POC:wakeup detect state
Figure 7-5: Transitions from the POC:wakeup detect state [POC].
7.2 Communication startup and reintegration
7.2.1 Principles
7.2.1.1 Definition and properties
7.2.1.2 Principle of operation
7.2.1.2.1 Startup performed by the coldstart nodes
7.2.1.2.2 Integration of the non-coldstart nodes
7.2.2 Description
Figure 7-6: Protocol operation control context.
7.2.3 Coldstart inhibit mode
7.2.4 Startup state diagram
Figure 7-7: Startup state diagram [POC].
Figure 7-8: Helpful macros for startup [POC].
Figure 7-9: Example of state transitions for a fault-free startup.
7.2.4.1 Path of a TT-D leading coldstart node
7.2.4.2 Path of a TT-D following coldstart node
7.2.4.3 Path of a TT-L coldstart node
Figure 7-10: Example of state transitions for a fault-free startup in a TT-L cluster.
7.2.4.4 Path of a TT-E coldstart node
Figure 7-11: Topology for the startup example of a TT-E cluster shown in Figure 7-12.
Figure 7-12: Example of state transitions for a fault-free startup in a TT-E cluster.
Figure 7-13: External startup state [POC].
7.2.4.5 Path of a non-coldstart node
7.2.4.6 The POC:coldstart listen state
Figure 7-14: Transitions from the POC:coldstart listen state [POC].
Figure 7-15: Macro CHECK_ATTACHED_CHANNELS [POC].
7.2.4.7 The POC:coldstart collision resolution state
Figure 7-16: Transitions from the POC:coldstart collision resolution state [POC].
7.2.4.8 The POC:coldstart consistency check state
Figure 7-17: Transitions from the POC:coldstart consistency check state [POC].
7.2.4.9 The POC:coldstart gap state
Figure 7-18: Transitions from the POC:coldstart gap state [POC].
7.2.4.10 The POC:initialize schedule state
Figure 7-19: Transitions from the POC:initialize schedule state [POC].
7.2.4.11 The POC:integration coldstart check state
Figure 7-20: Transitions from the POC:integration coldstart check state [POC].
7.2.4.12 The POC:coldstart join state
Figure 7-21: Transitions from the POC:coldstart join state [POC].
7.2.4.13 The POC:integration listen state
Figure 7-22: Transitions from the POC:integration listen state [POC].
7.2.4.14 The POC:integration consistency check state
Figure 7-23: Transitions from the POC:integration consistency check state [POC].
Chapter 8 Clock Synchronization
8.1 Introduction
Figure 8-1: Clock synchronization context.
8.2 Time representation
8.2.1 Timing hierarchy
Figure 8-2: Timing hierarchy.
8.2.2 Global and local time
8.2.3 Parameters and variables
Definition 8-1: Formal definition of T_Macrotick and T_Microtick.
8.3 Synchronization process
Figure 8-3: Timing relationship between clock synchronization, media access schedule, and the execution of clock synchronization functions.
Definition 8-2: Formal definition of T_EvenOdd and T_Deviation.
Definition 8-3: Formal definition of T_CspMode and T_SyncCalcResult.
Definition 8-4: Formal definition of T_ArrayIndex, T_SyncFrameIDCount, and T_FrameIDTable.
Definition 8-5: Formal definition of T_SyncExtern.
Figure 8-4: Declarations for the clock synchronization process [CSP].
Figure 8-5: Start of the clock synchronization process [CSP].
Figure 8-6: Wait for cycle start [CSP].
Figure 8-7: Measurement initialization for TT-E coldstart [CSP].
Figure 8-8: Clock synchronization control and termination [CSP].
8.4 Startup of the clock synchronization
Figure 8-9: Integration control [CSP].
8.4.1 Coldstart startup
8.4.2 Integration startup
Figure 8-10: Termination of the CSS process [CSS_A].
Figure 8-11: Clock synchronization startup process on channel A [CSS_A].
8.5 Time measurement
8.5.1 Data structure
Definition 8-6: Formal definition of T_DevValid.
Definition 8-7: Formal definition of T_ChannelDev, T_EOChDev, and T_DevTable.
Figure 8-12: Data structure example.
8.5.2 Initialization
Figure 8-13: Initialization of the data structure for measurement [CSP].
8.5.3 Time measurement storage
Figure 8-14: Measurement and storage of the deviation values [CSP].
8.6 Correction term calculation
8.6.1 Fault-tolerant midpoint algorithm
Table 8-1: FTM term deletion as a function of list size.
Figure 8-15: Example clock correction value calculation with k=2.
Figure 8-16: Fault-Tolerant Midpoint Procedure [CSP].
8.6.2 Calculation of the offset correction value
Definition 8-8: Formal definition of T_DeviationTable.
Figure 8-17: Calculation of the offset correction value [CSP].
8.6.3 Calculation of the rate correction value
Figure 8-18: Calculation of the rate correction value [CSP].
8.6.4 Value limitations
8.6.5 Host-controlled external clock synchronization
Table 8-2: External clock correction control.
Definition 8-9: Formal definition of T_ExternCorrection.
8.6.6 TT-E time gateway sink correction determination
Figure 8-19: Cycle start supervision [CSP].
Figure 8-20: External cycle start delay [CSP].
Figure 8-21: Obtain external clock sync signals [CSP].
Figure 8-22: Macro EXT_WAIT_OFFSET [CSP].
Figure 8-23: Macro EXT_WAIT_SYNC [CSP].
Figure 8-24: Macro EXT_SYNC_ERROR [CSP].
8.7 Clock correction
Figure 8-25: Macrotick generation [MTG].
Figure 8-26: Macro GENERATE_IMMINENT [MTG].
Figure 8-27: Termination of the MTG process [MTG].
8.8 Sync frame configuration rules
Table 8-3: Configuration rules for the clock synchronization.
8.8.1 TT-D cluster
8.8.2 TT-E cluster
8.8.3 TT-L cluster
8.9 Time gateway interface
Chapter 9 Controller Host Interface
9.1 Principles
Figure 9-1: Conceptual architecture of the controller host interface.
9.2 Description
Figure 9-2: Controller host interface context.
9.3 Interfaces
9.3.1 Protocol data interface
9.3.1.1 Protocol configuration data
9.3.1.1.1 Communication cycle timing configuration
9.3.1.1.2 Protocol operation configuration
9.3.1.1.3 Wakeup and startup configuration
9.3.1.1.4 Network Management Vector configuration
9.3.1.2 Protocol control data
9.3.1.2.1 Control of the protocol operation control
9.3.1.2.2 Control of MTS and WUDOP transmission
9.3.1.2.3 Control of external clock synchronization
9.3.1.3 Protocol status data
9.3.1.3.1 Protocol operation control status
9.3.1.3.2 Wakeup and startup status
9.3.1.3.3 Communication cycle timing status
9.3.1.3.4 Synchronization frame status
9.3.1.3.5 Startup frame status
9.3.1.3.6 Symbol window status
9.3.1.3.7 NIT status
9.3.1.3.8 Aggregated channel status
9.3.1.3.9 Dynamic segment status
9.3.2 Message data interface
9.3.2.1 Communication slot assignment
9.3.2.2 Communication slot assignment for transmission
9.3.2.2.1 Cycle-independent and cycle-dependent slot assignment
9.3.2.2.2 Transmission slot assignment list
9.3.2.2.3 Key slot assignment
9.3.2.3 Communication slot assignment for reception
9.3.2.4 Conflicting communication slot assignment for reception and transmission
9.3.2.5 Non-queued message buffers
9.3.2.5.1 Message buffer configuration data
9.3.2.5.2 Message buffer status data
9.3.2.5.3 Message buffer payload data and payload data valid flag
9.3.2.5.4 Buffer Enabling and Buffer Locking
9.3.2.6 Non-queued message buffer identification
9.3.2.6.1 Candidate transmit message buffer identification
Table 9-1: Transmit message buffer candidate.
9.3.2.6.2 Candidate receive message buffer identification
9.3.2.6.3 Selected transmit buffer identification
9.3.2.6.4 Selected receive buffer identification
9.3.2.6.5 Active message buffer identification
9.3.2.7 Message transmission
9.3.2.7.1 Transmit buffer configuration
9.3.2.7.2 Transmit buffer identification for message retrieval
9.3.2.7.3 Transmit buffer status
9.3.2.8 Message reception
9.3.2.8.1 Non-queued receive buffer configuration
9.3.2.8.2 Non-queued receive buffer contents
9.3.2.8.2.1 Slot status data
Table 9-2: Slot status interpretation.
9.3.2.8.2.2 Frame contents data
9.3.2.9 Non-queued message buffer status update
9.3.2.10 Queued receive buffers (FIFO's)
9.3.2.10.1 Basic FIFO behavior
9.3.2.10.1.1 Admittance into a FIFO
9.3.2.10.1.2 Reading and removal from a FIFO
9.3.2.10.2 FIFO admittance criteria
9.3.2.10.2.1 FIFO frame validity admittance criteria
9.3.2.10.2.2 FIFO channel admittance criteria
9.3.2.10.2.3 FIFO frame identifier admittance criteria
9.3.2.10.2.4 FIFO cycle counter admittance criteria
9.3.2.10.2.5 Message identifier admittance criteria
9.3.2.10.3 FIFO performance requirements
9.3.2.10.4 FIFO status information
9.3.3 CHI Services
9.3.3.1 Macrotick timer service
9.3.3.2 Interrupt service
9.3.3.3 Message ID filtering service
9.3.3.4 Network management service
Appendix A System Parameters
A.1 Protocol constants
Table A-1: Protocol constants.
A.2 Performance constants
Table A-2: Performance constants.
Appendix B Configuration Constraints
B.1 General
B.2 Bit rates
B.3 Parameters
B.3.1 Global cluster parameters
B.3.1.1 Protocol relevant
Table B-1: Global protocol relevant parameters.
B.3.1.2 Protocol related
Table B-2: Global protocol related parameters.
B.3.2 Node parameters
B.3.2.1 Protocol relevant
Table B-3: Local node protocol relevant parameters.
B.3.2.2 Protocol related
Table B-4: Local node protocol related parameters.
B.3.3 Physical layer parameters
Table B-5: Physical layer parameters.
B.3.4 Auxiliary parameters
Table B-6: Auxiliary parameters for configuration constraints.
B.4 Calculation of configuration parameters for nodes in a TT-D cluster
B.4.1 gClockDeviationMax
B.4.2 Attainable precision
B.4.2.1 Propagation Delay
B.4.2.1.1 adInternalRxDelay
B.4.2.1.2 adPropagationDelayMax
Table B-7: Calculations for adPropagationDelayMaxMax.
Table B-8: Calculations for adPropagationDelayMaxMin.
B.4.2.1.3 adPropagationDelayMin
Table B-9: Calculations for adPropagationDelayMinMin.
Table B-10: Calculations for adPropagationDelayMinMax.
B.4.2.2 Microtick Distribution Error
Table B-11: Calculations for adMicrotickDistError.
Table B-12: Calculations for adMicrotickMaxDistError.
B.4.2.3 Worst-case precision
Table B-13: Calculation of the worst-case precision.
B.4.2.4 Best-case precision
Table B-14: Calculation of the best-case precision.
B.4.2.5 Assumed precision
B.4.3 Ringing
B.4.4 Definition of microtick, macrotick, and bit time
Table B-15: Calculations for adBitMax and adBitMin.
Table B-16: pdMicrotick depending on pSamplesPerMicrotick and gdSampleClockPeriod.
Table B-17: Examples of gdMacrotick as a function of aMicroPerMacroNom and pdMicrotick.
B.4.5 adInitializationErrorMax
Table B-18: Calculations for adInitializationErrorMax.
B.4.6 pdAcceptedStartupRange
Table B-19: Calculations for pdAcceptedStartupRange.
B.4.7 pClusterDriftDamping
B.4.8 gdActionPointOffset
Table B-20: Calculations for gdActionPointOffset.
B.4.9 gdMinislotActionPointOffset
B.4.10 gdSymbolWindowActionPointOffset
B.4.11 gdMinislot
B.4.12 gdStaticSlot
Table B-21: Calculations for gdStaticSlot.
B.4.13 gdSymbolWindow
Table B-22: Calculations for gdSymbolWindow.
B.4.14 gMacroPerCycle
Table B-23: Calculations for gMacroPerCycle.
Table B-24: Calculations for gMacroPerCycle.
B.4.15 pMicroPerCycle
Table B-25: Calculations for pMicroPerCycle.
Table B-26: Calculations for pMicroPerCycle.
B.4.16 gdDynamicSlotIdlePhase
Table B-27: Calculations for gdDynamicSlotIdlePhase.
B.4.17 gNumberOfMinislots
Table B-28: Calculations for gNumberOfMinislots.
B.4.18 pRateCorrectionOut
Table B-29: Calculations for pRateCorrectionOut.
Table B-30: Calculations for pRateCorrectionOut.
B.4.19 Offset Correction
B.4.19.1 aOffsetCorrectionMax
Table B-31: Calculations for aOffsetCorrectionMax.
B.4.19.2 pOffsetCorrectionOut
Table B-32: Calculations for pOffsetCorrectionOut.
B.4.20 pOffsetCorrectionStart
B.4.21 gdNIT
B.4.22 pExternRateCorrection
Table B-33: Calculations for pExternRateCorrection.
B.4.23 pExternOffsetCorrection
Table B-34: Calculations for pExternOffsetCorrection.
B.4.24 pdListenTimeout
Table B-35: Calculations for pdListenTimeout.
Table B-36: Calculations for pdListenTimeout.
B.4.25 pDecodingCorrection
Table B-37: Calculations for pDecodingCorrection.
B.4.26 pDelayCompensation
Table B-38: Calculations for pDelayCompensation[Ch].
B.4.27 pMacroInitialOffset
Table B-39: Calculations for pMacroInitialOffset[Ch].
B.4.28 pMicroInitialOffset
Figure B-1: Illustration of pMicroInitialOffset[Ch].
B.4.29 pLatestTx
B.4.30 gdTSSTransmitter
Table B-40: Calculations for gdTSSTransmitter.
B.4.31 gdCASRxLowMax
B.4.32 gdWakeupTxIdle
Table B-41: Calculations for gdWakeupTxIdle.
B.4.33 gdWakeupTxActive
Table B-42: Calculations for gdWakeupTxActive.
B.4.34 gdWakeupRxIdle
B.4.35 gdWakeupRxLow
B.4.36 gdWakeupRxWindow
B.4.37 gdIgnoreAfterTx
Table B-43: Calculations for gdIgnoreAfterTx.
B.4.38 pKeySlotID
B.4.39 adTxMax
B.4.40 gPayloadLengthStatic
B.4.41 pPayloadLengthDynMax
B.4.42 gCycleCountMax
B.5 Configuration of cluster synchronization method and node synchronization role
Table B-44: Relationship of configuration parameters that determine the role of a FlexRay node.
B.6 Calculation of configuration parameters for nodes in a TT-L cluster
B.6.1 gClusterDriftDamping
B.6.2 TT-L cluster precision
B.6.3 pSecondKeySlotID
B.6.4 gdActionPointOffset
B.7 Calculation of configuration parameters for nodes in a TT-E cluster
B.7.1 gClusterDriftDamping
B.7.2 TT-E cluster precision
Table B-45: Calculation of aMixedTopologyError.
B.7.2.1 TT-E cluster precision for a TT-D worst-case precision time source cluster
Table B-46: Calculation of maximum precision in a sink cluster.
B.7.2.2 TT-E cluster precision for a TT-L time source cluster
Table B-47: Calculation of the minimum precision in a sink cluster.
B.7.2.3 TT-E assumed precision
B.7.3 pSecondKeySlotID
B.7.4 Host-controlled external clock correction
B.7.5 gdActionPointOffset
B.7.6 gMacroPerCycle
B.7.7 gdMacrotick
B.7.8 aOffsetCorrectionMax
B.7.9 pOffsetCorrectionStart
B.7.10 gdNIT
B.7.11 pdMicrotick
B.7.12 adInitializationErrorMax
Table B-48: Calculations for adInitializationErrorMax.
B.7.13 pdAcceptedStartupRange
Table B-49: Calculations for pdAcceptedStartupRange.
B.7.14 gCycleCountMax
Appendix C Wakeup Application Notes
C.1 Wakeup initiation by the host
C.1.1 Single-channel nodes
C.1.2 Dual-channel nodes
Figure C-1: A short example of how the wakeup of two channels can be accomplished in a fault- tolerant way by coldstart nodes.
C.1.2.1 Wakeup pattern reception by the bus driver
C.1.2.2 Wakeup pattern reception by the communication controller
C.2 Host reactions to status flags signaled by the communication controller
C.2.1 Frame header reception without decoding error
C.2.2 Wakeup pattern reception
C.2.3 Wakeup pattern transmission
C.2.4 Termination due to unsuccessful wakeup pattern transmission
C.3 Retransmission of wakeup patterns
C.4 Transition to startup
C.5 Wakeup during operation
C.5.1 Principles
C.5.1.1 Frame-based wakeup during operation
C.5.1.2 Pattern-based wakeup during operation
FlexRay Communications System
Protocol Specification
Version 3.0.1
FlexRay Protocol Specification
Disclaimer
Disclaimer
This specification and the material contained in it, as released by the FlexRay Consortium, is for the purpose
of information only. The FlexRay Consortium and the companies that have contributed to it shall not be liable
for any use of the specification.
The material contained in this specification is protected by copyright and other types of Intellectual Property
Rights. The commercial exploitation of the material contained in this specification requires a license to such
Intellectual Property Rights.
This specification may be utilized or reproduced without any modification, in any form or by any means, for
informational purposes only.
For any other purpose, no part of the specification may be utilized or reproduced, in any form or by any
means, without permission in writing from the publisher.
Important Information
1. The FlexRay™ specifications V2.1 and V3.0.1 and the corresponding FlexRay™
Conformance Test specifications (hereinafter together "FlexRay™ specifications")
have been developed for automotive applications only. They have neither been
developed nor tested for non-automotive applications.
2. The FlexRay™ specifications are
www.flexray.com for information purposes only and without obligation.
retrievable on
the FlexRay Website
3. The technical expertise provided in the FlexRay™ specifications is subject to continu-
ous further development. The FlexRay™ specifications serve exclusively as an infor-
mation source to enable to manufacture and test products which comply with the
FlexRay™ specifications ("FlexRay™ compliant products"). Observation of the
FlexRay™ specifications does neither guarantee the operability and safety of the
FlexRay™ compliant products, nor does it guarantee the safe cooperation of multiple
FlexRay™ compliant products with each other or with other products. Therefore, the
members of the former FlexRay™ Consortium are not able to assume liability for the
operability and safety of such products and the safe cooperation of multiple
FlexRay™ compliant products with each other or with other products.
4. The FlexRay™ specifications V3.0.1 were submitted to ISO in order to be published
as a standard for road vehicles.
The word FlexRay and the FlexRay logo are registered trademarks.
Copyright © 2006 - 2010. All rights reserved.
The Core Partners of the FlexRay Consortium are Adam Opel GmbH, Bayerische Motoren Werke AG,
Daimler AG, Freescale Halbleiter Deutschland GmbH, NXP B.V., Robert Bosch GmbH, and Volkswagen AG.
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Table of Contents
Disclaimer..............................................................................................................................................2
Chapter 1
Introduction.............................................................................................................. 12
1.1 Scope .............................................................................................................................................12
1.2 References .....................................................................................................................................12
1.2.1 FlexRay consortium documents ........................................................................................... 12
1.2.2 Non-consortium documents.................................................................................................. 12
1.3 Revision history ..............................................................................................................................13
1.4 Terms and definitions .....................................................................................................................16
1.5 Acronyms and abbreviations ..........................................................................................................22
1.6 Notational conventions ...................................................................................................................24
1.6.1 Parameter prefix conventions............................................................................................... 24
1.6.2 Color coding ......................................................................................................................... 25
1.6.3 Implementation dependent behavior .................................................................................... 25
1.7 SDL conventions ............................................................................................................................25
1.7.1 General................................................................................................................................. 25
1.7.2 SDL notational conventions.................................................................................................. 26
1.7.3 SDL extensions .................................................................................................................... 26
1.7.3.1 Microtick, macrotick and sample tick timers ................................................................. 26
1.7.3.2 Microtick behavior of the 'now' - expression ................................................................. 27
1.7.3.3 Channel-specific process replication ............................................................................ 27
1.7.3.4 Handling of priority input symbols................................................................................. 27
1.7.3.5 Signals to non-instantiated processes.......................................................................... 28
1.7.3.6 Exported and imported signals ..................................................................................... 28
1.8 Bit rates ..........................................................................................................................................28
1.9 Roles of a node in a FlexRay cluster..............................................................................................28
1.10 Synchronization methods .............................................................................................................29
1.10.1 TT-D synchronization method ............................................................................................ 29
1.10.2 TT-L synchronization method ............................................................................................. 29
1.10.3 TT-E synchronization method............................................................................................. 30
1.11 Network topology considerations..................................................................................................32
1.11.1 Passive bus topology.......................................................................................................... 33
1.11.2 Active star topology ............................................................................................................ 33
1.11.3 Active star topology combined with a passive bus topology............................................... 35
1.12 Example node architecture...........................................................................................................37
1.12.1 Objective............................................................................................................................. 37
1.12.2 Overview............................................................................................................................. 37
1.12.3 Host - communication controller interface .......................................................................... 37
1.12.4 Communication controller - bus driver interface ................................................................. 38
1.12.5 Bus driver - host interface................................................................................................... 39
1.12.5.1 Hard wired signals (option A) ..................................................................................... 39
1.12.5.2 Serial peripheral interface (SPI) (option B)................................................................. 39
1.12.6 Bus driver - power supply interface (optional) .................................................................... 40
1.12.7 Time gateway interface ...................................................................................................... 40
1.13 Testability requirements ...............................................................................................................40
Chapter 2
Protocol Operation Control .................................................................................... 41
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2.1 Principles ........................................................................................................................................41
2.1.1 Communication controller power moding ............................................................................. 41
2.2 Description......................................................................................................................................42
2.2.1 Operational overview............................................................................................................ 43
2.2.1.1 Host commands............................................................................................................ 44
2.2.1.2 Error conditions ............................................................................................................ 45
2.2.1.2.1 Errors causing immediate entry to the POC:halt state ..........................................45
2.2.1.2.2 Errors handled by the degradation model .............................................................45
2.2.1.3 POC status ................................................................................................................... 46
2.2.1.4 SDL considerations for single channel nodes .............................................................. 47
2.3 The protocol operation control process ..........................................................................................48
2.3.1 POC SDL utilities.................................................................................................................. 48
2.3.2 SDL organization .................................................................................................................. 50
2.3.3 Preempting commands......................................................................................................... 50
2.3.4 Deferred commands ............................................................................................................. 51
2.3.4.1 DEFERRED_HALT, DEFERRED_READY and CLEAR_DEFERRED commands ...... 51
2.3.4.2 ALL_SLOTS command................................................................................................. 54
2.3.5 Reaching the POC:ready state............................................................................................. 54
2.3.5.1 Default configuration requirements............................................................................... 56
2.3.6 Reaching the POC:normal active state ................................................................................ 57
2.3.6.1 Wakeup and startup support ........................................................................................ 58
2.3.7 Behavior during normal operation ........................................................................................ 60
2.3.7.1 Cyclical behavior .......................................................................................................... 60
2.3.7.1.1 Cycle counter.........................................................................................................60
2.3.7.1.2 POC:normal active state........................................................................................60
2.3.7.1.3 POC:normal passive state.....................................................................................62
2.3.7.1.4 Error checking during normal operation ................................................................64
2.3.7.1.4.1 Error checking overview ................................................................................65
2.3.7.1.4.2 Error checking details for the POC:normal active state.................................65
2.3.7.1.4.3 Error checking details for the POC:normal passive state ..............................66
Chapter 3
Coding and Decoding ............................................................................................. 69
3.1 Principles ........................................................................................................................................69
3.2 Description......................................................................................................................................69
3.2.1 Frame and symbol encoding ................................................................................................ 70
3.2.1.1 Frame encoding............................................................................................................ 70
3.2.1.1.1 Transmission start sequence.................................................................................70
3.2.1.1.2 Frame start sequence............................................................................................71
3.2.1.1.3 Byte start sequence...............................................................................................71
3.2.1.1.4 Frame end sequence.............................................................................................71
3.2.1.1.5 Dynamic trailing sequence ....................................................................................71
3.2.1.1.6 Frame bit stream assembly ...................................................................................72
3.2.1.2 Symbol encoding .......................................................................................................... 73
3.2.1.2.1 Collision avoidance symbol and media access test symbol ..................................73
3.2.1.2.2 Wakeup symbol .....................................................................................................74
3.2.1.2.3 Wakeup During Operation Pattern (WUDOP) .......................................................77
3.2.2 Sampling and majority voting ............................................................................................... 77
3.2.3 Bit clock alignment and bit strobing ...................................................................................... 78
3.2.4 Implementation specific delays............................................................................................. 79
3.2.5 Channel idle detection .......................................................................................................... 80
3.2.6 Action point and time reference point ................................................................................... 80
3.2.7 Frame and symbol decoding ................................................................................................ 82
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3.2.7.1 Frame decoding............................................................................................................ 83
3.2.7.2 Symbol decoding .......................................................................................................... 84
3.2.7.2.1 Collision avoidance symbol and media access test symbol decoding ..................84
3.2.7.2.2 Wakeup symbol decoding .....................................................................................84
3.2.7.3 Decoding error.............................................................................................................. 85
3.2.8 Signal integrity ...................................................................................................................... 86
3.3 Coding and decoding process ........................................................................................................86
3.3.1 Operating modes .................................................................................................................. 86
3.3.2 Coding and decoding process behavior ............................................................................... 86
3.3.3 Encoding behavior................................................................................................................ 88
3.3.4 Encoding macros.................................................................................................................. 91
3.3.5 Decoding behavior................................................................................................................ 96
3.3.6 Decoding macros.................................................................................................................. 97
3.4 Bit strobing process ......................................................................................................................104
3.4.1 Operating modes ................................................................................................................ 104
3.4.2 Bit strobing process behavior ............................................................................................. 105
3.5 Wakeup pattern decoding process ...............................................................................................107
3.5.1 Operating modes ................................................................................................................ 107
3.5.2 Wakeup pattern decoding process behavior ...................................................................... 108
Chapter 4
Frame Format......................................................................................................... 111
4.1 Overview.......................................................................................................................................111
4.2 FlexRay header segment (5 bytes) ..............................................................................................111
4.2.1 Reserved bit (1 bit) ............................................................................................................. 111
4.2.2 Payload preamble indicator (1 bit)...................................................................................... 112
4.2.3 Null frame indicator (1 bit) .................................................................................................. 112
4.2.4 Sync frame indicator (1 bit)................................................................................................. 112
4.2.5 Startup frame indicator (1 bit) ............................................................................................. 113
4.2.6 Frame ID (11 bits)............................................................................................................... 113
4.2.7 Payload length (7 bits)........................................................................................................ 114
4.2.8 Header CRC (11 bits) ......................................................................................................... 114
4.2.9 Cycle count (6 bits)............................................................................................................. 115
4.2.10 Formal header definition................................................................................................... 115
4.3 FlexRay payload segment (0 - 254 bytes)....................................................................................115
4.3.1 NMVector............................................................................................................................ 116
4.3.2 Message ID (16 bits) .......................................................................................................... 117
4.4 FlexRay trailer segment................................................................................................................117
4.5 CRC calculation details ................................................................................................................118
4.5.1 CRC calculation algorithm .................................................................................................. 118
4.5.2 Header CRC calculation ..................................................................................................... 119
4.5.3 Frame CRC calculation ...................................................................................................... 119
Chapter 5
Media Access Control ........................................................................................... 121
5.1 Principles ......................................................................................................................................121
5.1.1 Communication cycle ......................................................................................................... 121
5.1.2 Communication cycle execution ......................................................................................... 122
5.1.3 Static segment.................................................................................................................... 123
5.1.3.1 Structure of the static segment................................................................................... 123
5.1.3.2 Execution and timing of the static segment ................................................................ 123
5.1.4 Dynamic segment............................................................................................................... 124
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5.1.4.1 Structure of the dynamic segment.............................................................................. 124
5.1.4.2 Execution and timing of the dynamic segment ........................................................... 125
5.1.5 Symbol window................................................................................................................... 128
5.1.6 Network idle time ................................................................................................................ 129
5.2 Description....................................................................................................................................129
5.2.1 Operating modes ................................................................................................................ 130
5.2.2 Significant events ............................................................................................................... 131
5.2.2.1 Reception-related events............................................................................................ 131
5.2.2.2 Transmission-related events ...................................................................................... 132
5.2.2.3 Timing-related events ................................................................................................. 132
5.3 Media access control process ......................................................................................................132
5.3.1 Initialization and MAC:standby state .................................................................................. 133
5.3.2 Static segment related states ............................................................................................. 135
5.3.2.1 State machine for the static segment media access control ...................................... 135
5.3.2.2 Transmission conditions and frame assembly in the static segment.......................... 137
5.3.3 Dynamic segment related states ........................................................................................ 140
5.3.3.1 State machine for the dynamic segment media access control ................................. 140
5.3.3.2 Transmission conditions and frame assembly in the dynamic segment..................... 145
5.3.4 Symbol window related states ............................................................................................ 146
5.3.5 Network idle time ................................................................................................................ 147
Chapter 6
Frame and Symbol Processing ............................................................................ 149
6.1 Principles ......................................................................................................................................149
6.2 Description....................................................................................................................................149
6.2.1 Operating modes ................................................................................................................ 150
6.2.2 Significant events ............................................................................................................... 151
6.2.2.1 Reception-related events............................................................................................ 151
6.2.2.2 Decoding-related events............................................................................................. 152
6.2.2.3 Timing-related events ................................................................................................. 152
6.2.3 Status data ......................................................................................................................... 153
6.3 Frame and symbol processing process........................................................................................155
6.3.1 Initialization and FSP:standby state ................................................................................... 156
6.3.2 Macro SLOT_SEGMENT_END.......................................................................................... 157
6.3.3 FSP:wait for CE start state ................................................................................................. 158
6.3.4 FSP:decoding in progress state ......................................................................................... 159
6.3.4.1 Frame reception checks during non-synchronized operation..................................... 161
6.3.4.2 Frame reception checks during synchronized operation ............................................ 162
6.3.4.2.1 Frame reception checks in the static segment ....................................................162
6.3.4.2.2 Frame reception checks in the dynamic segment ...............................................163
6.3.5 FSP:wait for CHIRP state ................................................................................................... 164
6.3.6 FSP:wait for transmission end state ................................................................................... 165
Chapter 7
Wakeup and Startup.............................................................................................. 167
7.1 Cluster wakeup.............................................................................................................................167
7.1.1 Principles ............................................................................................................................ 167
7.1.2 Description.......................................................................................................................... 168
7.1.3 Wakeup support by the communication controller.............................................................. 169
7.1.3.1 Wakeup state diagram................................................................................................ 170
7.1.3.2 The POC:wakeup listen state ..................................................................................... 171
7.1.3.3 The POC:wakeup send state...................................................................................... 172
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7.1.3.4 The POC:wakeup detect state.................................................................................... 173
7.2 Communication startup and reintegration.....................................................................................173
7.2.1 Principles ............................................................................................................................ 173
7.2.1.1 Definition and properties............................................................................................. 173
7.2.1.2 Principle of operation.................................................................................................. 174
7.2.1.2.1 Startup performed by the coldstart nodes ...........................................................174
7.2.1.2.2 Integration of the non-coldstart nodes .................................................................174
7.2.2 Description.......................................................................................................................... 175
7.2.3 Coldstart inhibit mode......................................................................................................... 175
7.2.4 Startup state diagram ......................................................................................................... 176
7.2.4.1 Path of a TT-D leading coldstart node........................................................................ 179
7.2.4.2 Path of a TT-D following coldstart node ..................................................................... 179
7.2.4.3 Path of a TT-L coldstart node ..................................................................................... 180
7.2.4.4 Path of a TT-E coldstart node..................................................................................... 180
7.2.4.5 Path of a non-coldstart node ...................................................................................... 183
7.2.4.6 The POC:coldstart listen state.................................................................................... 184
7.2.4.7 The POC:coldstart collision resolution state............................................................... 186
7.2.4.8 The POC:coldstart consistency check state ............................................................... 187
7.2.4.9 The POC:coldstart gap state ...................................................................................... 188
7.2.4.10 The POC:initialize schedule state............................................................................. 189
7.2.4.11 The POC:integration coldstart check state ............................................................... 190
7.2.4.12 The POC:coldstart join state..................................................................................... 191
7.2.4.13 The POC:integration listen state............................................................................... 192
7.2.4.14 The POC:integration consistency check state.......................................................... 193
Chapter 8
Clock Synchronization.......................................................................................... 195
8.1 Introduction...................................................................................................................................195
8.2 Time representation......................................................................................................................196
8.2.1 Timing hierarchy ................................................................................................................. 196
8.2.2 Global and local time .......................................................................................................... 197
8.2.3 Parameters and variables................................................................................................... 197
8.3 Synchronization process ..............................................................................................................198
8.4 Startup of the clock synchronization.............................................................................................204
8.4.1 Coldstart startup ................................................................................................................. 206
8.4.2 Integration startup............................................................................................................... 206
8.5 Time measurement.......................................................................................................................209
8.5.1 Data structure ..................................................................................................................... 209
8.5.2 Initialization......................................................................................................................... 210
8.5.3 Time measurement storage................................................................................................ 211
8.6 Correction term calculation...........................................................................................................213
8.6.1 Fault-tolerant midpoint algorithm ........................................................................................ 213
8.6.2 Calculation of the offset correction value............................................................................ 214
8.6.3 Calculation of the rate correction value .............................................................................. 217
8.6.4 Value limitations ................................................................................................................. 219
8.6.5 Host-controlled external clock synchronization .................................................................. 220
8.6.6 TT-E time gateway sink correction determination .............................................................. 220
8.7 Clock correction............................................................................................................................226
8.8 Sync frame configuration rules .....................................................................................................229
8.8.1 TT-D cluster........................................................................................................................ 230
8.8.2 TT-E cluster ........................................................................................................................ 230
8.8.3 TT-L cluster ........................................................................................................................ 230
8.9 Time gateway interface ................................................................................................................231
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Chapter 9
Controller Host Interface ...................................................................................... 232
9.1 Principles ......................................................................................................................................232
9.2 Description....................................................................................................................................232
9.3 Interfaces......................................................................................................................................233
9.3.1 Protocol data interface........................................................................................................ 233
9.3.1.1 Protocol configuration data......................................................................................... 233
9.3.1.1.1 Communication cycle timing configuration ..........................................................234
9.3.1.1.2 Protocol operation configuration..........................................................................234
9.3.1.1.3 Wakeup and startup configuration.......................................................................236
9.3.1.1.4 Network Management Vector configuration ........................................................237
9.3.1.2 Protocol control data................................................................................................... 237
9.3.1.2.1 Control of the protocol operation control .............................................................237
9.3.1.2.2 Control of MTS and WUDOP transmission .........................................................237
9.3.1.2.3 Control of external clock synchronization ............................................................238
9.3.1.3 Protocol status data.................................................................................................... 239
9.3.1.3.1 Protocol operation control status .........................................................................239
9.3.1.3.2 Wakeup and startup status..................................................................................239
9.3.1.3.3 Communication cycle timing status .....................................................................240
9.3.1.3.4 Synchronization frame status ..............................................................................241
9.3.1.3.5 Startup frame status ............................................................................................241
9.3.1.3.6 Symbol window status .........................................................................................241
9.3.1.3.7 NIT status ............................................................................................................242
9.3.1.3.8 Aggregated channel status..................................................................................242
9.3.1.3.9 Dynamic segment status .....................................................................................243
9.3.2 Message data interface ...................................................................................................... 243
9.3.2.1 Communication slot assignment................................................................................. 244
9.3.2.2 Communication slot assignment for transmission ...................................................... 244
9.3.2.2.1 Cycle-independent and cycle-dependent slot assignment ..................................244
9.3.2.2.2 Transmission slot assignment list........................................................................245
9.3.2.2.3 Key slot assignment ............................................................................................245
9.3.2.3 Communication slot assignment for reception............................................................ 246
9.3.2.4 Conflicting communication slot assignment for reception and transmission .............. 246
9.3.2.5 Non-queued message buffers .................................................................................... 246
9.3.2.5.1 Message buffer configuration data ......................................................................246
9.3.2.5.2 Message buffer status data .................................................................................247
9.3.2.5.3 Message buffer payload data and payload data valid flag ..................................248
9.3.2.5.4 Buffer Enabling and Buffer Locking .....................................................................249
9.3.2.6 Non-queued message buffer identification ................................................................. 249
9.3.2.6.1 Candidate transmit message buffer identification................................................249
9.3.2.6.2 Candidate receive message buffer identification.................................................250
9.3.2.6.3 Selected transmit buffer identification..................................................................251
9.3.2.6.4 Selected receive buffer identification...................................................................251
9.3.2.6.5 Active message buffer identification ....................................................................251
9.3.2.7 Message transmission................................................................................................ 251
9.3.2.7.1 Transmit buffer configuration...............................................................................251
9.3.2.7.2 Transmit buffer identification for message retrieval.............................................252
9.3.2.7.3 Transmit buffer status..........................................................................................253
9.3.2.8 Message reception ..................................................................................................... 254
9.3.2.8.1 Non-queued receive buffer configuration ............................................................254
9.3.2.8.2 Non-queued receive buffer contents ...................................................................256
9.3.2.8.2.1 Slot status data............................................................................................256
9.3.2.8.2.2 Frame contents data....................................................................................257
Version 3.0.1
October 2010
Page 8 of 341
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