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EDA 六十进制计数器.docx
计时系统电路设计
姓名：张泽主
年级：电信 08104
学号：200811020403
设计元器件有：3 万分频器 CLKGEN，十进制计数器 CNT10，六进制计
时器 CNT6，24 分频器 CNT24 和 24 小时译码器 LED7S24
设计 VHDL 程序如下：
3 万分频器 CLKGEN：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clkgen is
port(clk:in std_logic;
newclk:out std_logic);
end clkgen;
architecture one of clkgen is
signal cnter:integer range 0 to 29999;
begin
process(clk)
begin
if clk'event and clk='1'then
if cnter=29999 then cnter<=0;
else cnter<=cnter+1;
end if;
end if;
end process;
process(cnter)
begin
if cnter=29999 then newclk<='1';
else newclk<='0';
end if;
end process;
end one;
十进制计数器 cnt10
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk,rst,ena:in std_logic;
outy:out std_logic_vector(3 downto 0);
cout:out std_logic);
end cnt10;
architecture one of cnt10 is
signal cqi:std_logic_vector(3 downto 0):="0000";
begin
process(clk,rst,ena)
begin
if rst='1'then cqi<="0000";
elsif clk'event and clk='1' then
if ena='1'then
if cqi<9 then cqi<=cqi+1;
else cqi<="0000";
end if;
end if;
end if;
outy<=cqi;
end process ;
cout<=not(cqi(0) and cqi(3));
end one;
24 分频器 cnt24：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt24 is
Port ( clk ,rst,ena:in std_logic;
outy :out std_logic_vector(4 downto 0);
cout:out std_logic);
end cnt24;
architecture one of cnt24 is
signal cqi :std_logic_vector(4 downto 0);
begin
process(clk,rst,ena)
begin
if rst='1' then cqi<="00000";
elsif clk'event and clk='1'then
if ena='1'then
if cqi<23 then cqi<=cqi+1;
else cqi<="00000";
end if;
end if;
end if;
outy<=cqi;
end process;
cout<=not(cqi(0) and cqi(1) and cqi(2) and cqi(4));
end one;
六进制计数器 cnt6：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt6 is
port(clk,rst,ena:in std_logic;
outy:out std_logic_vector(3 downto 0);
cout:out std_logic);
end cnt6;
architecture one of cnt6 is
signal cqi:std_logic_vector(3 downto 0):="0000";
begin
process(clk,rst,ena)
begin
if rst='1'then cqi<="0000";
elsif clk'event and clk='1'then
if ena='1'then
if cqi<5 then cqi<=cqi+1;
else cqi<="0000";
end if;
end if;
end if;
outy<=cqi;
end process;
cout<=not(cqi(0) and cqi(2));
end one;
24 小时译码器 led7s24：
library ieee;
use ieee.std_logic_1164.all;
entity led7s24 is
port(clr:in std_logic;
a:in bit_vector(4 downto 0);
led7s1:out bit_vector(3 downto 0);
led7s2:out bit_vector(7 downto 4));
end;
architecture one of led7s24 is
signal led7s:bit_vector(7 downto 0);
begin
process(clr,a)
begin
if clr='0' then led7s<="00000000";
else
case a(4 downto 0) is
when "00000"=>led7s<="00000000";
when "00001"=>led7s<="00000001";
when "00010"=>led7s<="00000010";
when "00011"=>led7s<="00000011";
when "00100"=>led7s<="00000100";
when "00101"=>led7s<="00000101";
when "00110"=>led7s<="00000110";
when "00111"=>led7s<="00000111";
when "01000"=>led7s<="00001000";
when "01001"=>led7s<="00001001";
when "01010"=>led7s<="00010000";
when "01011"=>led7s<="00010001";
when "01100"=>led7s<="00010010";
when "01101"=>led7s<="00010011";
when "01110"=>led7s<="00010100";
when "01111"=>led7s<="00010101";
when "10000"=>led7s<="00010110";
when "10001"=>led7s<="00010111";
when "10010"=>led7s<="00011000";
when "10011"=>led7s<="00011001";
when "10100"=>led7s<="00100000";
when "10101"=>led7s<="00100001";
when "10110"=>led7s<="00100010";
when "10111"=>led7s<="00100011";
when others=>null;
end case;
end if;
led7s2<=led7s(7 downto 4);
led7s1<=led7s(3 downto 0);
end process;
end one;
计时电路原理图如下：
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