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I2C总线英文原版协议.pdf
1. Introduction
2. I2C-bus features
2.1 Designer benefits
2.2 Manufacturer benefits
2.3 IC designer benefits
3. The I2C-bus protocol
3.1 Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols
3.1.1 SDA and SCL signals
3.1.2 SDA and SCL logic levels
3.1.3 Data validity
3.1.4 START and STOP conditions
3.1.5 Byte format
3.1.6 Acknowledge (ACK) and Not Acknowledge (NACK)
3.1.7 Clock synchronization
3.1.8 Arbitration
3.1.9 Clock stretching
3.1.10 The slave address and R/W bit
3.1.11 10-bit addressing
3.1.12 Reserved addresses
3.1.13 General call address
3.1.14 Software reset
3.1.15 START byte
3.1.16 Bus clear
3.1.17 Device ID
3.2 Ultra Fast-mode I2C-bus protocol
3.2.1 USDA and USCL signals
3.2.2 USDA and USCL logic levels
3.2.3 Data validity
3.2.4 START and STOP conditions
3.2.5 Byte format
3.2.6 Acknowledge (ACK) and Not Acknowledge (NACK)
3.2.7 The slave address and R/W bit
3.2.8 10-bit addressing
3.2.9 Reserved addresses in UFm
3.2.10 General call address
3.2.11 Software reset
3.2.12 START byte
3.2.13 Unresponsive slave reset
3.2.14 Device ID
4. Other uses of the I2C-bus communications protocol
4.1 CBUS compatibility
4.2 SMBus - System Management Bus
4.2.1 I2C/SMBus compliancy
4.2.2 Time-out feature
4.2.3 Differences between SMBus 1.0 and SMBus 2.0
4.3 PMBus - Power Management Bus
4.4 Intelligent Platform Management Interface (IPMI)
4.5 Advanced Telecom Computing Architecture (ATCA)
4.6 Display Data Channel (DDC)
5. Bus speeds
5.1 Fast-mode
5.2 Fast-mode Plus
5.3 Hs-mode
5.3.1 High speed transfer
5.3.2 Serial data format in Hs-mode
5.3.3 Switching from F/S-mode to Hs-mode and back
5.3.4 Hs-mode devices at lower speed modes
5.3.5 Mixed speed modes on one serial bus system
5.3.6 Standard, Fast-mode and Fast-mode Plus transfer in a mixed-speed bus system
5.3.7 Hs-mode transfer in a mixed-speed bus system
5.3.8 Timing requirements for the bridge in a mixed-speed bus system
5.4 Ultra Fast-mode
6. Electrical specifications and timing for I/O stages and bus lines
6.1 Standard-, Fast-, and Fast-mode Plus devices
6.2 Hs-mode devices
6.3 Ultra Fast-mode devices
7. Electrical connections of I2C-bus devices to the bus lines
7.1 Pull-up resistor sizing
7.2 Operating above the maximum allowable bus capacitance
7.2.1 Reduced fSCL
7.2.2 Higher drive outputs
7.2.3 Bus buffers, multiplexers and switches
7.2.4 Switched pull-up circuit
7.3 Series protection resistors
7.4 Input leakage
7.5 Wiring pattern of the bus lines
8. Abbreviations
9. Legal information
9.1 Definitions
9.2 Disclaimers
9.3 Trademarks
10. Contents
UM10204
I2C-bus specification and user manual
Rev. 6 — 4 April 2014
User manual
Document information
Info
Keywords
Abstract
Content
I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL
Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I2C-bus. Only two bus lines are required: a serial data line
(SDA) and a serial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100 kbit/s in the Standard-mode, up to
400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus (Fm+), or
up to 3.4 Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5 Mbit/s.
NXP Semiconductors
UM10204
I2C-bus specification and user manual
Revision history
Rev
v.6
Modifications:
Description
Date
20140404 User manual; sixth release
• Figure 41 “Rp(max) as a function of bus capacitance” updated (recalculated)
• Figure 42 “Rp(min) as a function of VDD” updated (recalculated)
v.5
v.4
v.3
20121009 User manual; fifth release
20120213 User manual Rev. 4
20070619 Many of today’s applications require longer buses and/or faster speeds. Fast-mode Plus was
introduced to meet this need by increasing drive strength by as much as 10× and increasing the
data rate to 1 Mbit/s while maintaining downward compatibility to Fast-mode and Standard-mode
speeds and software commands.
Version 2.1 of the I2C-bus specification
The I2C-bus has become a de facto world standard that is now implemented in over 1000 different
ICs and licensed to more than 50 companies. Many of today’s applications, however, require higher
bus speeds and lower supply voltages. This updated version of the I2C-bus specification meets those
requirements.
Version 1.0 of the I2C-bus specification
first release
v2.1
v2.0
2000
1998
1992
v1.0
Original 1982
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 4 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
1.
Introduction
UM10204
I2C-bus specification and user manual
The I2C-bus is a de facto world standard that is now implemented in over 1000 different
ICs manufactured by more than 50 companies. Additionally, the versatile I2C-bus is used
in various control architectures such as System Management Bus (SMBus), Power
Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display
Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA).
This document assists device and system designers to understand how the I2C-bus works
and implement a working application. Various operating modes are described. It contains
a comprehensive introduction to the I2C-bus data transfer, handshaking and bus
arbitration schemes. Detailed sections cover the timing and electrical specifications for the
I2C-bus in each of its operating modes.
Designers of I2C-compatible chips should use this document as a reference and ensure
that new devices meet all limits specified in this document. Designers of systems that
include I2C devices should review this document and also refer to individual component
data sheets.
2.
I2C-bus features
In consumer electronics, telecommunications and industrial electronics, there are often
many similarities between seemingly unrelated designs. For example, nearly every
system includes:
• Some intelligent control, usually a single-chip microcontroller
• General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM,
EEPROM, real-time clocks or A/D and D/A converters
• Application-oriented circuits such as digital tuning and signal processing circuits for
radio and video systems, temperature sensors, and smart cards
To exploit these similarities to the benefit of both systems designers and equipment
manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips
Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus
for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. All I2C-bus
compatible devices incorporate an on-chip interface which allows them to communicate
directly with each other via the I2C-bus. This design concept solves the many interfacing
problems encountered when designing digital control circuits.
Here are some of the features of the I2C-bus:
• Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
• Each device connected to the bus is software addressable by a unique address and
simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
• It is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in
the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode
Plus, or up to 3.4 Mbit/s in the High-speed mode.
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 4 April 2014
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3 of 64
NXP Semiconductors
UM10204
I2C-bus specification and user manual
• Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode
• On-chip filtering rejects spikes on the bus data line to preserve data integrity.
• The number of ICs that can be connected to the same bus is limited only by a
maximum bus capacitance. More capacitance may be allowed under some
conditions. Refer to Section 7.2.
Figure 1 shows an example of I2C-bus applications.
I2C
A/D or D/A
Converters
I2C
General Purpose
I/O Expanders
I2C
LED Controllers
I2C
DIP Switches
I2C
Slave
VDD4
VDD5
VDD2
I2C
Multiplexers
and Switches
PCA9541
I2C
Master Selector/
Demux
I2C
Repeaters/
Hubs/Extenders
VDD0
VDD1
I2C Port
via HW or
Bit Banging
MCUs
I2C
Bus Controllers
8
MCUs
I2C
Serial EEPROMs
LCD Drivers
(with I2C)
VDD3
Fig 1.
Example of I2C-bus applications
2.1 Designer benefits
I2C
Real Time Clock/
Calendars
I2C
Temperature
Sensors
Bridges
(with I2C)
SPI
UART
USB
002aac858
I2C-bus compatible ICs allow a system design to progress rapidly directly from a
functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be
modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
Here are some of the features of I2C-bus compatible ICs that are particularly attractive to
designers:
• Functional blocks on the block diagram correspond with the actual ICs; designs
proceed rapidly from block diagram to final schematic.
• No need to design bus interfaces because the I2C-bus interface is already integrated
on-chip.
UM10204
User manual
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Rev. 6 — 4 April 2014
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NXP Semiconductors
UM10204
I2C-bus specification and user manual
• Integrated addressing and data-transfer protocol allow systems to be completely
software-defined.
• The same IC types can often be used in many different applications.
• Design-time reduces as designers quickly become familiar with the frequently used
functional blocks represented by I2C-bus compatible ICs.
• ICs can be added to or removed from a system without affecting any other circuits on
the bus.
• Fault diagnosis and debugging are simple; malfunctions can be immediately traced.
• Software development time can be reduced by assembling a library of reusable
software modules.
In addition to these advantages, the CMOS ICs in the I2C-bus compatible range offer
designers special features which are particularly attractive for portable equipment and
battery-backed systems.
They all have:
• Extremely low current consumption
• High noise immunity
• Wide supply voltage range
• Wide operating temperature range.
2.2 Manufacturer benefits
I2C-bus compatible ICs not only assist designers, they also give a wide range of benefits
to equipment manufacturers because:
• The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins
and there are not so many PCB tracks; result — smaller and less expensive PCBs.
• The completely integrated I2C-bus protocol eliminates the need for address decoders
and other ‘glue logic’.
• The multi-master capability of the I2C-bus allows rapid testing and alignment of
end-user equipment via external connections to an assembly line.
• The availability of I2C-bus compatible ICs in various leadless packages reduces
space requirements even more.
These are just some of the benefits. In addition, I2C-bus compatible ICs increase system
design flexibility by allowing simple construction of equipment variants and easy
upgrading to keep designs up-to-date. In this way, an entire family of equipment can be
developed around a basic model. Upgrades for new equipment, or enhanced-feature
models (that is, extended memory, remote control, etc.) can then be produced simply by
clipping the appropriate ICs onto the bus. If a larger ROM is needed, it is simply a matter
of selecting a microcontroller with a larger ROM from our comprehensive range. As new
ICs supersede older ones, it is easy to add new features to equipment or to increase its
performance by simply unclipping the outdated IC from the bus and clipping on its
successor.
UM10204
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 4 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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UM10204
I2C-bus specification and user manual
2.3
IC designer benefits
Designers of microcontrollers are frequently under pressure to conserve output pins. The
I2C protocol allows connection of a wide variety of peripherals without the need for
separate addressing or chip enable signals. Additionally, a microcontroller that includes an
I2C interface is more successful in the marketplace due to the wide variety of existing
peripheral devices available.
3. The I2C-bus protocol
3.1 Standard-mode, Fast-mode and Fast-mode Plus I2C-bus protocols
Two wires, serial data (SDA) and serial clock (SCL), carry information between the
devices connected to the bus. Each device is recognized by a unique address (whether
it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as
either a transmitter or receiver, depending on the function of the device. An LCD driver
may be only a receiver, whereas a memory can both receive and transmit data. In addition
to transmitters and receivers, devices can also be considered as masters or slaves when
performing data transfers (see Table 1). A master is the device which initiates a data
transfer on the bus and generates the clock signals to permit that transfer. At that time,
any device addressed is considered a slave.
Definition of I2C-bus terminology
Table 1.
Term
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Description
the device which sends data to the bus
the device which receives data from the bus
the device which initiates a transfer, generates clock signals and
terminates a transfer
the device addressed by a master
more than one master can attempt to control the bus at the same time
without corrupting the message
procedure to ensure that, if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the winning message is
not corrupted
procedure to synchronize the clock signals of two or more devices
Synchronization
The I2C-bus is a multi-master bus. This means that more than one device capable of
controlling the bus can be connected to it. As masters are usually microcontrollers, let us
consider the case of a data transfer between two microcontrollers connected to the
I2C-bus (see Figure 2).
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I2C-bus specification and user manual
MICRO -
CONTROLLER
A
LCD
DRIVER
STATIC
RAM OR
EEPROM
SDA
SCL
GATE
ARRAY
ADC
MICRO -
CONTROLLER
B
mbc645
Fig 2.
Example of an I2C-bus configuration using two microcontrollers
This example highlights the master-slave and receiver-transmitter relationships found on
the I2C-bus. Note that these relationships are not permanent, but only depend on the
direction of data transfer at that time. The transfer of data would proceed as follows:
1. Suppose microcontroller A wants to send information to microcontroller B:
– microcontroller A (master), addresses microcontroller B (slave)
– microcontroller A (master-transmitter), sends data to microcontroller B
(slave-receiver)
– microcontroller A terminates the transfer.
2. If microcontroller A wants to receive information from microcontroller B:
– microcontroller A (master) addresses microcontroller B (slave)
– microcontroller A (master-receiver) receives data from microcontroller B
(slave-transmitter)
– microcontroller A terminates the transfer.
Even in this case, the master (microcontroller A) generates the timing and terminates the
transfer.
The possibility of connecting more than one microcontroller to the I2C-bus means that
more than one master could try to initiate a data transfer at the same time. To avoid the
chaos that might ensue from such an event, an arbitration procedure has been developed.
This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus.
If two or more masters try to put information onto the bus, the first to produce a ‘one’ when
the other produces a ‘zero’ loses the arbitration. The clock signals during arbitration are a
synchronized combination of the clocks generated by the masters using the wired-AND
connection to the SCL line (for more detailed information concerning arbitration see
Section 3.1.8).
Generation of clock signals on the I2C-bus is always the responsibility of master devices;
each master generates its own clock signals when transferring data on the bus. Bus clock
signals from a master can only be altered when they are stretched by a slow slave device
holding down the clock line or by another master when arbitration occurs.
Table 2 summarizes the use of mandatory and optional portions of the I2C-bus
specification and which system configurations use them.
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Rev. 6 — 4 April 2014
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UM10204
I2C-bus specification and user manual
Applicability of I2C-bus protocol features
Table 2.
M = mandatory; O = optional; n/a = not applicable.
Feature
START condition
STOP condition
Acknowledge
Synchronization
Arbitration
Clock stretching
7-bit slave address
10-bit slave address
General Call address
Software Reset
START byte
Device ID
Configuration
Single master
M
M
M
n/a
n/a
O[2]
M
O
O
O
n/a
n/a
Multi-master
M
M
M
M
M
O[2]
M
O
O
O
O[3]
n/a
Slave[1]
M
M
M
n/a
n/a
O
M
O
O
O
n/a
O
[1] Also refers to a master acting as a slave.
[2] Clock stretching is a feature of some slaves. If no slaves in a system can stretch the clock (hold SCL LOW),
[3]
the master need not be designed to handle this procedure.
‘Bit banging’ (software emulation) multi-master systems should consider a START byte. See
Section 3.1.15.
3.1.1 SDA and SCL signals
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
current-source or pull-up resistor (see Figure 3). When the bus is free, both lines are
HIGH. The output stages of devices connected to the bus must have an open-drain or
open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred
at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to
1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The bus
capacitance limits the number of interfaces connected to the bus.
For a single master application, the master’s SCL output can be a push-pull driver design
if there are no devices on the bus which would stretch the clock.
VDD1 =
5 V ± 10 %
VDD2
VDD3
CMOS
CMOS
NMOS
BIPOLAR
Rp
Rp
SDA
SCL
VDD2, VDD3 are device-dependent (for example, 12 V).
Fig 3. Devices with various supply voltages sharing the same bus
002aac860
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