GaN驱动电路得详细设计方案和注意事项.pdf

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GN001 Application Brief How to drive GaN Enhancement mode HEMT Updated on Mar-24-2016 GaN Systems Inc. GaN Systems – 1

Basics  Basics  Design considerations  Driver selection  Design examples  PCB Layout  Switching Testing results Latest update Mar. 24, 2016 Please visit http://www.gansystems.com/whitepapers.php for latest version of this document GaN Systems – 2

Fundamentals of GaN Systems E-HEMT GaN Enhancement mode High Electron Mobility Transistor (E-HEMT): • • • Lateral 2DEG (2-dimensional electron gas) channel formed between AlGaN and GaN layers Positive gate bias opens up 2DEG channel 0V or negative gate voltage shuts off 2DEG and block forward conduction • Voltage driven: Gate driver charges/discharges (CGD + CGS) • No DC gate driving current needed: gate leakage current only (IGSS) GaN E-HEMT simplified structure E-HEMT circuit model GaN Systems – 3 Si substrateGaNAl GaNSDG2DEGVGSVDSIGSSIDS2DEGDRAINGATECGDCGSCDSSOURCE

Gate Characteristics GaN E-HEMT vs. other technologies • Similar gate drive requirement to Silicon MOSFET/IGBT • Much Smaller gate charge – Lower drive loss, faster rise & fall time • • • Lower gate voltage – Select right gate driver UVLO Easy 5 to 6.5V gate drive with maximum rating +7V and +10V transient 0V to turn off, typical VGTH=1.5V. • Negative voltage improves gate drive robustness but optional • Easy slew rate control using gate resistor Gate drive voltage level GaN Systems GaN E-HEMT Si MOSFET Maximum rating -10/+7V +/-20V Transient maximum -20/+10V* IGBT +/-20V +/-30V SIC MOSFET -8/+18V Typical operational values 0 or -3/+5-6.5V 0/+10-12V 0 or -9/+15V -4/+15V [*] pulse width < 1uS GaN Systems – 4

GaN E-HEMT Reverse Conduction • No parasitic body diode: Zero QRR Loss & very high dv/dt ruggedness • GaN E-HEMT is naturally capable of reverse conduction, without external diode • Unlike MOSFETs/IGBT, reverse current flow through same 2DEG channel as forward conduction • “Diode” like reverse behavior is VGS dependent Drain-source forward bias: Reverse bias VGS=0V: Reverse bias with -VGS: When VGS ≤ 0V: no channel conduction • One can consider D/S swapped in reverse bias mode 2DEG channel starts to conduct when VSD = VGS’ (VGD) > VGTH = ~1.5V Reverse current flows in 2DEG • • • • 2DEG starts to conduct when VSD = VGTH + VGS_OFF -VGS increases reverse voltage drop VSD GaN Systems – 5 Si substrateGaNAl GaNSDG2DEGV+VSD(S’)(D’)VGS’Si substrateGaNAl GaNSDG2DEGV+VDSDSV+S (D’)D(S’)GV+VGS’S (D’)D(S’)GV+VGS’VGS_OFF

Reverse Conduction Loss model GS66508T reverse I/V characteristics 2-quadrant bidirectional current flow in 2DEG channel VGS = 6V (on-state): • • Reverse Rds(on) same as forward conduction • Ploss_rev= ISD 2x RDS(ON), Tj VGS=-2V VGS ≤ 0V (off-state): • Modeled as “diode” with VF + channel resistance Rrev_on that is higher than RDS(ON) in forward conduction 2 X RREV(ON) + ISD x (VGTH + VGS_OFF) • VSD increases with the negative gate voltage applied • Ploss_rev = ISD How does it affect the design: • No external anti-parallel diode required • No QRR Loss (QOSS loss only), perfect fit for half bridge where hard commutation is required – Higher efficiency and more robust without body diode VGTH VGTH + 2V Reverse bias model • Higher reverse conduction loss, for optimal efficiency: • Minimize dead time and utilize synchronous drive • Prefer 0V for turn-off GaN Systems – 6 VGSTH + VGS_OFFRREV_ON

Reduce Losses using Dead time & Synchronous driving • Synchronous driving with minimum dead time is recommended for optimum efficiency • Dead time can be selected by considering the worst case gate driver propagation delay skewing + switching rise/fall time • • For 650V GS66508T/P: typical 50-100ns For 100V GS61008P: typical 15-20ns 25ns Delay difference for Si8261 Isolated gate driver Total switching time 26ns for GS66508T (RG=10Ω, TJ=125°C) GaN Systems – 7 ParametersSymbolValueUnitConditionsTurn-on delay timetd(on)4.5nsRise timetr6.3nsTurn-off delay timetd(off)9.3nsFall timetf5.4nsGS66508T TJ=125°CVDD=400V, VGS=6V, ID=16A, RG=10Ω

Design Considerations  Basics  Design considerations  Driver selection  Design examples  PCB Layout  Switching Testing results GaN Systems – 8

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