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fir_block design.pdf

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instances
axi_smc design_1_axi_smc_0
filter filter_imp
processing_system7_0 design_1_processing_system7_0_0
ps7_0_axi_periph ps7_0_axi_periph_imp
rst_ps7_0_100M design_1_rst_ps7_0_100M_0
ports
DDR output
FIXED_IO output
portBuses
nets
axi_dma_0_M_AXI_MM2S
axi_dma_0_M_AXI_S2MM
axi_smc_M00_AXI
processing_system7_0_DDR
processing_system7_0_FCLK_CLK0
processing_system7_0_FCLK_RESET0_N
processing_system7_0_FIXED_IO
processing_system7_0_M_AXI_GP0
ps7_0_axi_periph_M00_AXI
rst_ps7_0_100M_interconnect_aresetn
rst_ps7_0_100M_peripheral_aresetn
netBundles
rst_ps7_0_100M slowest_sync_clk ext_reset_in aux_reset_in mb_reset bus_struct_reset[0:0] peripheral_reset[0:0] mb_debug_sys_rst interconnect_aresetn[0:0] dcm_locked peripheral_aresetn[0:0] Processor System Reset ps7_0_axi_periph S00_AXI ACLK ARESETN S00_ACLK S00_ARESETN M00_ACLK M00_ARESETN filter axi_smc processing_system7_0 M00_AXI S_AXI_LITE m_axi_mm2s_aclk axi_resetn M_AXI_MM2S M_AXI_S2MM S00_AXI S01_AXI aclk aresetn M00_AXI S_AXI_HP0 S_AXI_HP0_FIFO_CTRL M_AXI_GP0_ACLK S_AXI_HP0_ACLK AXI Interconnect AXI SmartConnect DDR FIXED_IO DDR FIXED_IO USBIND_0 M_AXI_GP0 FCLK_CLK0 FCLK_RESET0_N ZYNQ7 Processing System
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