Contents
Preface
Related Documents
Typographic and Syntax Conventions
SKILL Syntax Examples
Form Examples
Features of the Virtuoso® Analog Design Environment
Consistent User Interface
Analog Design Entry
Design Hierarchy
Simulators Supported
Annotation
Interactive Simulation
Simulation Output and Analysis
Advanced Analysis
Environment Setup
About the Simulation Window
Displaying the Simulation Window
Choosing the Design
Choosing a Simulator
Setting the Simulation Temperature
Setting the Model Path
Choosing a User Interface Path
Using the Simulation Window
Using the Schematic Window
Simulator Interfaces
Spectre Simulator
Virtuoso UltraSim Simulator Interface
Virtuoso AMS Simulator Interface
Mixed-Signal Simulators
Hspice Direct Interface
HSPICE Socket Interface
Cadence SPICE Simulator
Setting Up Simulation Files
Setting Simulation Environment Options
Setting Simulation Environment Options for Direct Simulation
Setting Environment Options for AMS
Setting Simulation Environment Options for Socket Simulation
Setting Up a Remote Simulation
Using a Third-Party Simulator for Remote Simulations
Scripts for Using Third-Party Simulators in Remote Simulations
About the Simulation Environment
Saving and Restoring the Simulation Setup
Saving a Script
Resetting the Default Environment
Setting Basic Session Defaults
Netlisting Control Variables
Customizing Your .cdsinit File
Customizing Your .cdsenv File
Customizing Your Menus File
Setting UNIX Environment Variables
Reserved Words
Reserved Words in Direct Simulation
Reserved Words in Socket Simulations
What Are Bindkeys?
Checking Bindkey Assignments
Assigning Bindkeys
Using the Key or Mouse Binding Form
Using the CIW
Using Your .cdsinit File
Form Field Descriptions
Choosing Simulator/Directory/Host
Create New File
Setting Model Path
Model Library Setup
Environment Options
Saving State
Loading State
Editing Session Options
Design Variables and Simulation Files for Direct Simulation
About Direct Simulation
Important Benefits of Direct Simulation
Using Direct Simulation
Important Use-Model Differences between spectreS and spectre
Migration from spectreS to spectre
Design Variables and Simulation
Setting Values
Adding a New Variable
Changing Values
Deleting Values
Saving Variable Values
Restoring Variable Values
Copying Values between the Schematic and the Simulation Environment
Displaying Values on the Schematic
Adding Setup Files for Direct Simulation
Using a Definitions File
Syntax
Definition File Example
Stimuli Setup
Using the Setup Analog Stimuli Form
Specifying a Stimulus File
Example of a spectre Stimulus File
Model Files in the Virtuoso® Analog Design Environment
Model File Libraries
Referencing Textual Subcircuits or Models
Updating the Component CDF
Creating a Stopping Cellview
Using the Component
Including the Subcircuit File in the Netlist
Scope of Parameters
Inheriting from the Same Instance: iPar()
Passed Parameter Value of One Level Higher: pPar()
Passed Parameters from Any Higher Level: atPar()
Inheriting from the Instance Being Netlisted: dotPar()
Table of Functions
Nesting Functions
Using Inheritance Functions in Input Files
How the Netlister Expands Hierarchy
Netlisting Sample for Spectre
Modifying View Lists and Stop Lists
About Netlists
The .simrc File
Incremental Netlisting
Creating and Displaying a Netlist
Form Field Descriptions
Setup Analog Stimuli Form
Editing Design Variables
Design Variables and Simulation Files for Socket Simulation
Schematic Variables and Simulation
Setting Values
Adding a New Variable
Changing Values
Deleting Values
Saving Variable Values
Restoring Variable Values
Copying Values between the Schematic and the Simulation Environment
Displaying Values on the Schematic
Adding Analysis Commands to Netlist
Using an Init File
Syntax
Example Functions
Init Example
Using an Update File
Update Examples
Setting Spectre Options
Options Examples
Making Init or Update Files Compatible with Other Simulators
Stimuli Setup
The Analog Stimuli Form
Creating a Stimulus File Using a Text Editor
Managing Edited Files
Path Specification
Setup Considerations
Examples of Edited Files
Model Files in Socket Simulations
Editing Model Files in the Models Directory
Using Model Files in Native Syntax In Socket Simulations
About Subcircuits and Macros
How Subcircuits Are Named
Creating the Component CDF and a Stopping Cellview
Including the Subcircuit File in the Netlist
HSPICE CDF Examples
Scope of Parameters
Inheriting from the Same Instance: iPar()
Passed Parameter Value from the Parent Instance: pPar()
Inheriting from the Current or Any Higher Level: atPar()
Inheriting from the Instance being Netlisted: dotPar()
Table of Functions
Determining the Current Instance in Expression Evaluation
Nesting Functions
How the Netlister Expands Hierarchy
Netlisting Sample for SpectreS
Modifying View Lists and Stop View Lists
Using Instance-Based View Switching
Setting Up View List and Stop List Tables
Assigning Properties to Instances in the Schematic
About Netlists
Incremental Netlisting
Creating and Displaying a Raw Netlist for Socket Simulations
Creating and Displaying a Final Netlist for Socket Simulations
Form Field Descriptions
Setup Analog Stimuli
Editing Design Variables
Setting Up for an Analysis
Required Symbol
Setting Up with Different Simulators
Deleting an Analysis
Enabling or Disabling an Analysis
Saving the Analysis Setup
Restoring a Saved Analysis Setup
Packing a Design in AMS
Setting Up a Spectre Analysis
Transient Analysis
DC Analysis
AC Small-Signal Analysis
Noise Analysis
S-Parameter Analysis
Transfer Function Analysis
Sensitivity Analysis
DC Mismatch Analysis
Stability Analysis
Pole Zero Analysis
Other Spectre Analyses
Setting Up an UltraSim Analysis
Fast Envelope Analysis for RF Circuit Simulation
Running Advanced Analysis UltraSim Simulations
Setting Up an AMS Analysis
Setting Up a SpectreS Analysis
Transient Analysis
AC Small-Signal or S-Parameter Analysis
DC Analysis
Transfer Function Analysis
Noise Analysis
Current Probing For SpectreS Macro Models
Setting Up a Cadence SPICE Analysis
AC Analysis
Transient Analysis
DC Analysis
Noise Analysis
Selecting Data to Save, Plot, or March
About the Saved, Plotted, and Marched Sets of Outputs
Opening the Setting Outputs Form
Deciding which Outputs to Save
Saving All Voltages or Currents
Saving Outputs for UltraSim Simulations
Saving Selected Voltages or Currents
Saving or Plotting Selected Voltages or Currents for AMS Simulation
Adding a Node or Terminal to a Set
Adding a Saved Node to the Plot or March Set
Removing Nodes and Terminals from a Set
Saving a List of Outputs
Restoring a Saved List of Outputs
Conditional Search for Results
Form Field Descriptions
Circuit Conditions
Setting Outputs
Save Options and Keep Options
Running a Simulation
Prerequisites to Simulation
Setting Simulator Options
Spectre Options
UltraSim Options
AMS Options
SpectreS Options
HSPICE Socket Options
Cadence SPICE Options
OSS-based AMS Netlister
Important Benefits of OSS-based AMS Netlister
Choosing the AMS Netlister
Selecting the AMS Netlister
Starting a Simulation
Starting a Socket Simulation
Interrupting or Stopping a Simulation
Continuing a Cadence SPICE Transient Simulation
Updating Variables and Resimulating
Saving Simulator Option Settings
Restoring Saved Settings
Viewing the Simulation Output
Viewing the Output Log for AMS
Viewing the Error Explanation for AMS
Using the SimVision Debugger with AMS
Display Partition
Default Digital Discipline Selection
Entering Simulator Commands in the TypeIn Window
Running a Parametric Analysis
Setting Up and Running Statistical Analyses
Device Checking
Editing Asserts
Setting Options
Violations Display
Helping a Simulation to Converge
Commands for Forcing Convergence
Node Set
Initial Conditions
Force Node
Selecting Nodes and Setting Their Values
Releasing Voltages
Changing Voltages
Saving and Restoring Node Voltages
Highlighting Set Nodes
Storing a Solution
Restoring a Solution for Spectre
Restoring a Solution for cdsSpice
Form Field Descriptions
Store/Restore File
Analysis Tools
About Parametric Analysis
Sweeps on Multiple Variables
Overview of Analysis Specification
Getting Started with Parametric Analysis
Specifying Sweep Variables
Specifying Ranges
Storing Specifications
Viewing Specifications
Specifying Step Values and Types
Parametric Set Sweep
Running a Parametric Analysis
Run-Time Modifications
Starting the Run
Interrupt and Restart
Closing the Window
Statistical Analysis
Using the Optimizer
Corners Analysis
UltraSim Power Network Solver
UltraSim Interactive Simulation Debugging
Form Field Descriptions
Parametric Analysis
Plotting and Printing
Selecting the Waveform Tool
Overview of Plotting
Plot Selector
Setting Plotting and Display Options
Saving and Restoring the Window Setup
Using the Plot Outputs Commands
Plotting the Current or Restored Results
Removing Nodes and Terminals from the Plot List
Plotting Parasitic Simulation Results
Using the Direct Plot Commands
For Noise Figures
For Transfer Functions
For S-Parameters
Using the Direct Plot Main Form
For DC
For Transient Results
For Stability Results
For Pole Zero Results
Overview of Printing
Printing Results
Saving State
Loading State
Updating Results
Making a Window Active
Editing Expressions
Setting Display Options
Displaying Output Information
Specifying Results to Print
Printing DC Operating Points
Printing Transient Operating Points
Printing Model Parameters of Components
Printing Noise Parameters of Nodes or Components
Printing DC Mismatch Summary
Printing Stability Summary
Printing DC Node Voltages
Printing Transient Voltages
Printing Sensitivities
Precision Control for Printing
Printing Capacitance Data
Printing Statistical Reports or Calculator Results
Using SKILL to Display Tabular Data
Overview of Plotting Calculator Expressions
Defining Expressions
Plotting Expressions
Suppressing Plotting of an Expression
Annotating Simulation Results
Saving Simulation Results
Deleting Simulation Results
Browsing Results Directories
Restoring Saved Results
Annotating Transient Voltages
Annotating Transient Operating Points
Specifying the Data Directory for Labels
Saving and Removing Annotated Labels
Highlighting Logic Levels with Wire Colors
Plotting Results of a Parametric Analysis
Form Field Descriptions
Setting Plotting Options
XF Results
S-Parameter Results
Annotate Voltage Levels
Setting Outputs
Noise Summary
Save Results
Select Results
Delete Results
UNIX Browser
Hspice Direct Support
Introduction
Libraries
Features
Model Libraries
Distributed Processing Support
Running Analyses
Analog Options
Output Log
Convergence Aids
Results
Advanced Analysis Tools Support
Converting Libraries
UltraSimVerilog
Interface Element Macro Models
Inline Subcircuit
Interface Element Selection Rules
Simulation Accuracy and Performance
Analog-to-Digital (A2D) Models
Digital-to-Analog (D2A) Models
Analog-to-Analog-In (A2AI) Models
Analog-to-Analog-Out (A2AO) Models
Model Description
Netlisting Options
Verilog Netlisting Options
Hierarchical Netlisting
Running a Mixed Signal Simulation
Setting Simulator Options
Input Stimulus for HNL
Setting Design Variables
Choosing Analyses
Running the Simulation
Control and Debugging
Viewing and Analyzing Simulation Output
Environment Variables
ADE Simulation Environment
filteredSimList
saveDir
designEditMode
schematicBased
windowBased
saveAsCellview
saveQuery
loadCorners
x
y
simulator
projectDir
hostMode
host
digitalHostMode
digitalHost
remoteDir
autoPlot
artistPlottingMode
directPlotPlottingMode
designName
simulationDate
temperature
variables
scalarOutputs
icons
width
height
x
y
immediatePlot
immediatePrint
preSaveOceanScript
postSaveOceanScript
numberOfSavedRuns
browserCenterMode
createCDFtermOrder
updateCDFtermOrder
printNotation
displayMode
stripModeType
saveDefaultsToOCEAN
showWhatsNew
digits
obsoleteWarnings
netlistAccess
printCommentChar
loadCorners
toolList
ignoreSchModified
defaultTools
oceanScriptFile
printInlines
awvResizeWindow
paraplotUpdateSimulatorLog
labelDigits
termFontSize
Calculator
mode
uimode
eval
dstack
Distributed Processing
clockSync
autoJobSubmit
showMessages
queueName
hostName
startTime
startDay
expTime
externalServer
expDay
timeLimit
emailNotify
mailTo
logsInEmail
stateFile
daysBeforeExpire
block
copyMode
copyModeDir
loginShell
numOfTasks
jobArgsInOceanScript
puttogetherqueue
copyNetlist
mailAllLogs
Spectre
save
outputParamInfo
modelParamInfo
pwr
useprobes
subcktprobelvl
nestlvl
elementinfo
saveahdlvars
currents
switchViewList
stopViewList
autoDisplay
spp
stimulusFile
includePath
modelFiles
analysisOrder
paramRangeCheckFile
printComments
definitionFiles
enableArclength
useAltergroup
netlistBBox
autoDisplayBBox
includeStyle
simExecName
savestate
recover
firstRun
simOutputFormat
controlMode
licQueueTimeOut
licQueueSleep
ignorePortOrderMismatch
SpectreVerilog and SpectreSVerilog
simOutputFormat
logicOutputFormat
HspiceD
setTopLevelAsSubckt
AMS and UltraSim
connectRulesList
rulesNames
rulesAndModuleFiles
useEffectiveCDF
useOtherOutputFormat
Waveform Tools in ADE
Post Processing Tools
Differences in Behavior
Graphs
Object Oriented Editing
Moving Traces
Tracking Cursors
Adding Markers and Labels
Zooming
Reset Option
Modifying Objects
Saving and Loading of Graphs
Creating a Digital Representation of an Analog Signal
Bindkeys
Calculator
Function Organization
Specifying Arguments for a Function
Manipulating the Buffer
Selecting Data in Building Expressions
Operating on a Zoomed-In Part of a Trace
Plotting
Printing
Results Browser
Data Selection
Location History
Data Display
Plot Selection
Plotting Sweeps
Complex Data
YvsY and Diff
Scalar Data
SST2 Data Support
Multiple Signal Selection
SKILL functions: Differences in Behavior
Migration Information
auCdl Netlisting
What Is auCdl and Why Do You Need It?
Licensing Requirements
Running auCdl
Running auCdl from within DFII
Running auCdl from the Command Line
Creating a config View for auCdl
Customization Using the .simrc File
auCdl-Specific Parameters
View List, Stop List, Netlist Type, and Comments
Preserving Devices in the Netlist
Printing CDL Commands
Defining Power Node and Ground Node
Evaluating Expressions
Mapping Global Pins
Renaming Cell Names
Renaming Pcell Subcircuits
Custom Netlisting Procedures
ansCdlCompPrim
ansCdlSubcktCall
ansCdlHnlPrintInst
Black Box Netlisting
Additional Customizations
Automatically Including a Partial Netlist File within the .SUBCKT Definition for the Top or Mid-L...
Including a ROM-Insert Netlist Automatically Into the auCdl Netlist
PININFO for Power and Ground Pins
Changing the Pin Order
.PARAM Statement
Specifying the Terminal Order for Terminals
Notification about Net Collision
Getting the Netlister to Stop at the Subcircuit Level
Parameter Passing
Netlisting the Area of an npn
CDF Simulation Information for auCdl
Device CDF Values
Netlist Examples
What Is Different in the 4.3 Release
Complete Example
Spectre in ADE
New Release Stream
Enhancements
Improved Parsing and Spice Compatibility
Softshare FLEXlm v10.1 Licensing
Save/Restart
64-Bit Support
License Suspend and Resume
Enhanced Pole Zero Analysis
Fractional Impedance/Admittance Pole
New Device Models and Components
Transient Noise Analysis
auLvs Netlisting
Using auLvs
How to Run auLvs from within DFII
Customization Using the .simrc File
Related Documentation on auLvs
Index