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Low Power Methodology Manual for Soc Design.pdf
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Table of Contents
APPENDIX A Sleep Transistor Design 249
APPENDIX B UPF Command Syntax 267
Preface
CHAPTER 1 Introduction
1.1 Overview
1.2 Scope of the Problem
1.3 Power vs. Energy
Figure 1-1 Power vs. Energy
1.4 Dynamic Power
Figure 1-2 Dynamic Power
Figure 1-3 Crowbar Current
1.5 The Conflict Between Dynamic and Static Power
1.6 Static Power
Figure 1-4 Leakage Currents
1.7 Purpose of This Book
CHAPTER 2 Standard Low Power Methods
2.1 Clock Gating
Figure 2-1 Clock Gating
2.2 Gate Level Power Optimization
Figure 2-2 Examples of Gate Level Optimizations
2.3 Multi VDD
Figure 2-3 Multi-Voltage Architecture
2.4 Multi-Threshold Logic
Figure 2-4 Delay vs. Leakage for 90nm
Figure 2-5 Leakage vs. Delay for a 90nm Library
2.5 Summary of the Impact of Standard Low Power Techniques
CHAPTER 3 Multi-Voltage Design
3.1 Challenges in Multi-Voltage Designs
3.2 Voltage Scaling Interfaces - Level Shifters
3.2.1 Unidirectional Level Shifters
3.2.2 Level Shifters - high to low voltage translation
Figure 3-1 High to Low Level Shifters
3.2.3 Level Shifters - low-to-high voltage
Figure 3-2 Low to High Level Shifters
3.2.4 Level Shifter Placement
Figure 3-3 Level Shifter in the Destination Domain
Figure 3-4 Buffering and Level Shifters
Figure 3-5 Placement of Low to High Level Shifter
3.2.5 Automation and Level Shifters
3.2.6 Level Shifter Recommendations and Pitfalls
3.3 Timing Issues in Multi-Voltage Designs
3.3.1 Clocks
Figure 3-6 Clock Distribution and Multi-Voltage
3.3.2 Static Timing Analysis
3.4 Power Planning for Multi-Voltage Design
3.5 System Design Issues with Multi-Voltage Designs
CHAPTER 4 Power Gating Overview
4.1 Dynamic and Leakage power profiles
Figure 4-1 Activity Profile with No Power Gating
Figure 4-2 Activity Profile with Power Gating
Figure 4-3 Realistic Profile with Power Gating
4.2 Impact of Power Gating on classes of sub-systems
4.3 Principles of Power Gating Design
Figure 4-4 Block Diagram of an SoC with Power Gating
4.3.1 Power Switching - Fine Grain vs. Coarse Grain
Figure 4-5 Fine Grain AND Gate with Pull-Up
4.3.2 The Challenges of Power Gating
CHAPTER 5 Designing Power Gating
Figure 5-1 SoC with Power Gating
5.1 Switching Fabric Design
5.1.1 Controlling the Switching Fabric
5.1.2 Recommendations and Pitfalls for power gating control
5.2 Signal isolation
5.2.1 Signal Isolation techniques
Figure 5-2 Basic Isolation Cells
Figure 5-3 Pull-Down and Pull-Up Isolation Transistors
5.2.2 Output or Input Isolation
5.2.3 Interface Protocols and Isolation
Figure 5-4 Output Isolation
5.2.4 Recommendations and Pitfalls for Isolation
5.3 State retention and restoration methods
5.3.1 State Retention Using Scan Chains
Figure 5-5 Scan Based Retention
5.3.2 Retention Registers
Figure 5-6 Retention Registers
5.3.3 Power Controller Design for Retention
5.3.4 Partial vs. Full State Retention
5.3.5 System Level Issues and Retention
5.3.6 Recommendations and Pitfalls for state retention
5.4 Power gating control
5.4.1 Power control sequencing
Figure 5-7 Power Control Sequencing Without Retention
Figure 5-8 Power Control Sequencing With Retention
5.4.2 Handshake Protocols
Figure 5-9 Power Switching With Acknowledge
5.4.3 Recommendations and Pitfalls for power gating controllers
5.5 Power gating design verification - RTL simulation
5.5.1 Inferring Power Gating Behavior in RTL
Figure 5-10
5.5.2 Inferring Power Gating and Retention Behavior in RTL
5.6 Design For Test considerations
5.6.1 Power Gating Controls
5.6.2 Power Limitations during Scan Test
5.6.3 Testing the Switching Network
5.6.4 Testing Isolation and Retention
5.6.5 Testing the Power Gating Controller
CHAPTER 6 Architectural Issues for Power Gating
6.1 Hierarchy and Power Gating
Figure 6-1 Power Gating Example
Figure 6-2 Flattened Switching Network
6.2 Power networks and their control
Figure 6-3 Power Network Control
6.2.1 External power rail switching
6.2.2 On-chip power gating
6.3 Power State Tables and Always On Regions
Figure 6-4 Buffering Inter-Domain Signals
CHAPTER 7 A Power Gating Example
7.1 Leakage modes supported
Figure 7-1 SALT Block Diagram
Figure 7-2 Power States for SALT
7.2 Design partitioning
Figure 7-3 Partitioning of the SALT Chip
Figure 7-4 Re-Partitioned CPU Subsystem
7.3 Isolation
7.4 Retention
7.5 Inferring Power Gating and Retention
7.6 Measurements and Analysis
Figure 7-5 Power Measurements for SALT
Figure 7-6 Leakage Power on SALT
Figure 7-7 Leakage vs. Temperature
Figure 7-8 Leakage Savings vs. Temperature
CHAPTER 8 IP Design for Low Power
8.1 Architecture and Partitioning for Power Gating
8.1.1 How and When to Shut Down
8.1.2 What to shut down and what to keep alive
Figure 8-1 USB OTG Block Diagram
8.2 Power Controller Design for the USB OTG
Figure 8-2 Power Gating Sequence for the USB OTG
8.3 Issues in Designing Portable Power Controllers
8.4 Clocks and Resets
8.5 Verification
8.6 Packaging IP for Reuse with Power Intent
8.7 UPF for the USB OTG Core
Figure 8-3 Power Gating for the USB OTG
8.8 USB OTG Power Gating Controller State Machine
Figure 8-4 Top Level State Machine
CHAPTER 9 Frequency and Voltage Scaling Design
9.1 Dynamic Power and Energy
Figure 9-1 Voltage and Frequency Scaling Opportunity
Figure 9-2 Increased Savings with Frequency Scaling
Figure 9-3 Energy Savings From Voltage Scaling
9.2 Voltage Scaling Approaches
9.3 Dynamic Voltage and Frequency Scaling (DVFS)
Figure 9-4 DVFS Block Diagram
9.4 CPU Subsystem Design Issues
Figure 9-5 CPU Subsystem
Figure 9-6 CPU Subsystem with Fixed Cache Supply
9.5 Adaptive Voltage Scaling (AVS)
Figure 9-7 Adaptive Voltage Scaling
9.6 Level Shifters and Isolation
9.7 Voltage Scaling Interfaces - Effect on Synchronous Timing
Figure 9-8 Latch-based Re-timing
Figure 9-9 Read Timing for Latch Based Re-timing
Figure 9-10 Write Timing for Latch-based Re-timing
Figure 9-11 Register-based Re-timing
Figure 9-12 Write Timing for Register-based Re-timing
9.8 Control of voltage scaling
Figure 9-13 Example Utilization Trace
Figure 9-14 Trace With with Periodic Tasks Identified
CHAPTER 10 Examples of Voltage and Frequency Scaling Design
10.1 Voltage Scaling - A Worked Example for UMC 130nm
10.1.1 ULTRA926 System Design Block Diagram
Figure 10-1 ULTRA926
10.1.2 Voltage/Frequency range exploration
Figure 10-2 ULTRA926 Scaling Analysis
10.1.3 Synchronous Design Constraints
Figure 10-3 ULTRA926 Clock Tree Latency
10.1.4 Simulated (predicted) Energy Savings Analysis
10.1.5 Silicon-measured Power and Performance Analysis
Figure 10-4 Current, Voltage and Frequency for ULTRA926
Figure 10-5 Power, Voltage and Frequency for ULTRA926
10.1.6 Silicon-measured ULTRA926 DVFS energy savings Analysis
Figure 10-6 Energy, Voltage and Frequency for ULTRA926
10.2 Voltage Scaling - A worked example for TSMC 65nm
10.2.1 ATLAS926 case study
10.2.2 Voltage/Frequency range exploration
10.2.3 Silicon-measured Power and Performance Analysis
Figure 10-7 Power, Voltage and Frequency for ATLAS926
Figure 10-8 Total Energy (Relative to 1.20V FMAX)
Figure 10-9 Power Savings in the Different Modes
CHAPTER 11 Implementing Multi- Voltage, Power Gated Designs
Figure 11-1 ARM1176JZF-S Synthesizable Applications Processor
Figure 11-2 ARM1176JZF-S Multi-voltage, power gated design
11.1 Design Partitioning
11.1.1 Logical and Physical Hierarchy
Figure 11-3 Alignment of power domain to logical hierarchy
11.1.2 Critical Path Timing
11.2 Design Flow Overview
Figure 11-4 Design Flow Overview
11.3 Synthesis
11.3.1 Power Intent
11.3.2 Defining Power Domains and Power Connectivity
11.3.3 Isolation Cell Insertion
11.3.4 Retention Register Insertion
11.3.5 Level Shifter Insertion
Figure 11-5 Input Nets on Level Shifters are Protected
11.3.6 Scan Synthesis
Figure 11-6 Power Domain Mixing of Scan Chains
Figure 11-7 Additional Isolation Needed For Scan Chain Creation
11.3.7 Always-On Network Synthesis
Figure 11-8 Always-on Networks Required in Power Gated Designs
11.4 Multi Corner Multi Mode Optimization with Voltage Scaling Designs
11.5 Design Planning
11.5.1 Creating Voltage Areas
Figure 11-9 Mapping of Power Domain to Voltage Area
11.5.2 Power Gating Topologies
11.5.3 In-rush Current Management
11.5.4 Recommendations:
11.6 Power Planning
11.6.1 Decoupling Capacitor Insertion
11.7 Clock Tree Synthesis
Figure 11-10 Clock Tree Synthesis Challenge in a Multi-Voltage Design
Figure 11-11 Bottom Up Clock Tree Clustering
Figure 11-12 Detour Routing Around a Power Domain
11.8 Power Analysis
11.9 Timing Analysis
11.10 Low Power Validation
11.11 Manufacturing Test
CHAPTER 12 Physical Libraries
12.1 Standard Cell Libraries
12.1.1 Modeling of Standard Cell Libraries
12.1.2 Characterization of Standard Cell Libraries
12.2 Special Cells - Isolation Cells
12.2.1 Signal Isolation
Figure 12-1 AND-style Isolation Cell
Figure 12-2 OR-style Isolation Cell
Figure 12-3 State Retention Isolation
12.2.2 Output Isolation vs. Input Isolation
12.2.3 Sneak DC leakage paths
Figure 12-4 Sneak DC path through leaky XOR gate
12.2.4 Recommendations
12.3 Special Cells - Level Shifters
Figure 12-5 High to Low Level Shifter
Figure 12-6 Low to High Level Shifter
Figure 12-7 Example Layout of a Low to High Level Shifter
Figure 12-8 Level Shifter Plus Isolation Cell
12.4 Memories
12.4.1 RAMs for Multi-Voltage Power Gated Designs
Figure 12-9 Multi-Voltage RAM Interface
12.4.2 Memories and Retention
12.5 Power Gating Strategies and Structures
12.5.1 Power Gating Structures
Figure 12-10 Fine Grain Cells
Figure 12-11 Fine Grain AND with Pull-Up
Figure 12-12 Coarse Grain Power Gating
12.5.2 Recommendations - Coarse Grain vs. Fine Grain
12.6 Power Gating Cells
Figure 12-13 Footer and Header Switches
Figure 12-14 Parallel Transistors Make Up the Switch
Figure 12-15 Layout of a Footer Cell
12.7 Power Gated Standard Cell Libraries
Figure 12-16 Header-based Power Gating
CHAPTER 13 Retention Register Design
13.1 Retention Registers
13.1.1 Single Pin “Live Slave” Retention Registers
Figure 13-1 Retention Register: “Live Slave”
Figure 13-2 Generic Switch Cell
Figure 13-3 Control Waveform for Single Control Retention Register
13.1.2 Dual control signal “Balloon” Retention Register
Figure 13-4 Dual Control Balloon Register
Figure 13-5 Dual Control Retention Register
Figure 13-6 Control Waveform for Dual Control Retention Register
13.1.3 Single control signal “Balloon” Retention Register
Figure 13-7 Single Control Balloon Register
Figure 13-8 Single Control Retention Register
Figure 13-9 Control Waveform for Single Control Balloon Register
13.1.4 Retention Register: Relative layout
Figure 13-10 Standard Scan D-type Register
Figure 13-11 Balloon Register
13.2 Memory retention methods
13.2.1 VDD retention method
13.2.2 Source-diode biasing method
Figure 13-12 Source-diode biasing SRAM retention
13.2.3 Source biasing method
Figure 13-13 Source biasing SRAM retention
13.2.4 Retention latency reduction methods
CHAPTER 14 Design of the Power Switching Network
14.1 Ring vs. Grid Style
14.1.1 Ring style implementation
Figure 14-1 Ring style sleep transistor implementation
14.1.2 Grid style implementation
Figure 14-2 Grid style sleep transistor implementations
14.1.3 Row and Column Grids
Figure 14-3 Column Based Switching
Figure 14-4 Row Based Switching
14.1.4 Hybrid style implementation
14.1.5 Recommendations - Ring vs. Grid Style
14.2 Header vs. Footer Switch
14.2.1 Switch efficiency considerations
Figure 14-5 90nm high VT pMOS switch efficiency at normal body bias
Figure 14-6 90nm high VT nMOS switch efficiency at normal body bias
14.2.2 Area efficiency consideration and L/W choice
Figure 14-7 90nm pMOS Ion/Ioff and Ion vs. W
14.2.3 Body bias considerations
14.2.4 System level design consideration
14.2.5 Recommendations - Header vs. Footer
14.3 Rail vs. Strap VDD supply
14.3.1 Parallel rail VDD distribution
Figure 14-8 Parallel Vdd rail distribution
14.3.2 Power strap VDD distribution
Figure 14-9 Power strap Vdd distribution
14.3.3 Recommendations for Supply Distribution
14.4 A Sleep Transistor Example
Figure 14-10 A double-row sleep transistor implementation
14.5 Wakeup Current and Latency Control Methods
14.5.1 Single daisy chain sleep transistor distribution
Figure 14-11 Single-daisy chain sleep transistor distribution
14.5.2 Dual daisy chain sleep transistor distribution
Figure 14-12 Dual daisy chain sleep transistor distribution
14.5.3 Parallel short chain distribution of the main sleep transistor
14.5.4 Main chain turn-on control
14.5.5 Buffer delay based main chain turn-on control
14.5.6 Programmable main chain turn-on control
14.5.7 Power-off latency reduction
Figure 14-13 Parallel switching off sleep transistors
14.5.8 Recommendations for Power Switching Control
14.6 An Example of a Dual Daisy Chain Sleep Transistor Implementation
Figure 14-14 Dual daisy chain sleep transistor implementation in SALT
A.1 Sleep transistor design metrics
A.1.1 Switch efficiency
Figure A-1 An example of Ion/Ioff SPICE analysis circuit
Figure A-2 65nm High VT pMOS Ion/Ioff curve (normal back bias)
Figure A-3 65nm pMOS Ion/Ioff curve at reverse back bias (Vbb=1.4V)
A.1.2 Area efficiency
A.1.3 IR drop
Figure A-4 90nm High VT pMOS Ron and Ioff curves
A.1.4 Normal vs. reverse body bias
Figure A-5
Figure A-6 90nm Ioff/Vbb curve of high-VT pMOS (L=100nm, W=3um,Vds=1V, Vgs=0V, tt-corner)
Figure A-7 90nm pMOS Ion/Ioff and Ioff curves
Figure A-8 65nm pMOS Ion/Ioff and Ioff curves
Figure A-9 65nm nMOS Ion/Ioff and Ioff curves
A.1.5 Recommendations
A.2 Layout design for area efficiency
Figure A-10 Spacing rule overhead of sleep transistor with well-taped standard cells
A.2.1 Recommendations
A.3 Single row vs. double row
A.3.1 Recommendations
A.4 In-rush current and latency analysis
Figure A-11 Charge current and time SPICE transient simulation circuit
Figure A-12 Wakeup power-on voltage curve
Figure A-13 Wakeup power-on current curve
APPENDIX A Sleep Transistor Design
APPENDIX B UPF Command Syntax
B.1 add_pst_state
B.2 connect_supply_net
B.3 create_power_domain
B.4 create_power_switch
B.5 create_pst
B.6 create_supply_net
B.7 create_supply_port
B.8 set_domain_supply_net
B.9 set_isolation
B.10 set_isolation_control
B.11 set_level_shifter
B.12 set_retention
B.13 set_retention_control
B.14 set_scope
Glossary
Bibliography
Index
Michael Keating • David Flynn •
Robert Aitken Alan Gibbons • Kaijian Shi
•
Low Power Methodology
Manual
For System-on-Chip Design
David Flynn
ARM Limited
Cambridge
United Kingdom
Alan Gibbons
Synopsys, Inc.
Northampton
United Kingdom
Michael Keating
Synopsys, Inc.
Palo Alto, CA
USA
Robert Aitken
ARM, Inc.
Almaden, CA
USA
Kaijian Shi
Synopsys, Inc.
Dallas, TX
USA
e-ISBN 978-0-387-71819-4
Library of Congress Control Number: 2007928355
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Table of Contents
Preface...........................................................................................xv
1 Introduction....................................................................................1
1.1 Overview ....................................................................................................... 1
1.2 Scope of the Problem..................................................................................... 2
1.3 Power vs. Energy........................................................................................... 3
1.4 Dynamic Power ............................................................................................. 4
1.5 The Conflict Between Dynamic and Static Power........................................ 7
1.6 Static Power................................................................................................... 8
1.7 Purpose of This Book .................................................................................. 10
2 Standard Low Power Methods ...................................................13
2.1 Clock Gating................................................................................................ 13
2.2 Gate Level Power Optimization .................................................................. 15
2.3 Multi VDD................................................................................................... 16
2.4 Multi-Threshold Logic ................................................................................ 17
2.5 Summary of the Impact of Standard Low Power Techniques..................... 19
3 Multi-Voltage Design ...................................................................21
3.1 Challenges in Multi-Voltage Designs.......................................................... 22
3.2 Voltage Scaling Interfaces – Level Shifters................................................. 22
3.2.1 Unidirectional Level Shifters ......................................................... 23
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