第1页 / 共226页
第2页 / 共226页
第3页 / 共226页
第4页 / 共226页
第5页 / 共226页
第6页 / 共226页
第7页 / 共226页
第8页 / 共226页
完整版JESD79-3F DDR3协议规范 官网最新原版.pdf
JEDEC
STANDARD
DDR3 SDRAM Standard
JESD79-3F
(Revision of JESD79-3E, July 2010)
JULY 2012
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
publication may be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
www.jedec.org
Published by
©JEDEC Solid State Technology Association 2012
3103 North 10th Street, Suite 240 South
Arlington, VA 22201
This document may be downloaded free of charge; however JEDEC retains the copyright on this
material. By downloading this file the individual agrees not to charge for or resell the resulting
material.
PRICE: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications online at
http://www.jedec.org/Catalog/catalog.cfm
Printed in the U.S.A.
All rights reserved
PLEASE!
DON'T VIOLATE THE LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
3103 North 10th Street, Suite 240 South
Arlington, Virginia 22201
or call (703) 907-7559
This page left blank.
JEDEC Standard No. 79-3F
Contents
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
2.11.1 512Mb ....................................................................................................................15
2.11.2 1Gb..........................................................................................................................15
2.11.3 2Gb .........................................................................................................................15
2.11.4 4Gb .........................................................................................................................15
2.11.5 8Gb .........................................................................................................................16
3 Functional Description.............................................................................................................17
3.1 Simplified State Diagram.................................................................................................17
3.3.1 Power-up Initialization Sequence .............................................................................19
3.3.2 Reset Initialization with Stable Power......................................................................21
3.4.1 Programming the Mode Registers ............................................................................22
3.4.2 Mode Register MR0..................................................................................................23
3.4.3 Mode Register MR1..................................................................................................27
3.4.4 Mode Register MR2..................................................................................................30
3.4.5 Mode Register MR3..................................................................................................32
4 DDR3 SDRAM Command Description and Operation...........................................................33
4.1 Command Truth Table.....................................................................................................33
4.3 No OPeration (NOP) Command ......................................................................................36
4.4 Deselect Command ..........................................................................................................36
4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
4.8.2 Procedure Description...............................................................................................43
4.8.3 Write Leveling Mode Exit ........................................................................................45
4.9.1 Self-Refresh Temperature Range - SRT...................................................................46
4.10.1 MPR Functional Description ..................................................................................49
4.10.2 MPR Register Address Definition ..........................................................................50
4.10.3 Relevant Timing Parameters...................................................................................50
4.10.4 Protocol Example....................................................................................................50
4.12 PRECHARGE Command ..............................................................................................55
4.13.1 READ Burst Operation...........................................................................................56
4.13.3 Burst Read Operation followed by a Precharge......................................................66
4.14.1 DDR3 Burst Operation ...........................................................................................68
4.14.2 WRITE Timing Violations .....................................................................................68
4.14.3 Write Data Mask.....................................................................................................69
4.14.4 tWPRE Calculation.................................................................................................70
4.14.5 tWPST Calculation .................................................................................................70
4.17.1 Power-Down Entry and Exit...................................................................................81
4.17.2 Power-Down clarifications - Case 1 .......................................................................86
4.17.3 Power-Down clarifications - Case 2 .......................................................................87
5 On-Die Termination (ODT).....................................................................................................89
5.1 ODT Mode Register and ODT Truth Table.....................................................................89
i
JEDEC Standard No. 79-3F
Contents
5.2 Synchronous ODT Mode .................................................................................................90
5.2.1 ODT Latency and Posted ODT.................................................................................90
5.2.2 Timing Parameters....................................................................................................90
5.2.3 ODT during Reads ....................................................................................................92
5.3.1 Functional Description:.............................................................................................94
5.3.2 ODT Timing Diagrams.............................................................................................95
5.4.1 Synchronous to Asynchronous ODT Mode Transitions.........................................101
5.4.2 Synchronous to Asynchronous ODT Mode Transition during
Power-Down Entry .................................................................................................101
5.4.3 Asynchronous to Synchronous ODT Mode Transition during
Power-Down Exit ...................................................................................................104
5.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short
CKE low periods.....................................................................................................105
5.5.1 ZQ Calibration Description.....................................................................................107
5.5.2 ZQ Calibration Timing ...........................................................................................108
5.5.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ...........................108
6 Absolute Maximum Ratings ..................................................................................................109
6.1 Absolute Maximum DC Ratings....................................................................................109
6.2 DRAM Component Operating Temperature Range ......................................................109
7 AC & DC Operating Conditions............................................................................................111
7.1 Recommended DC Operating Conditions......................................................................111
8 AC and DC Input Measurement Levels.................................................................................113
8.1 AC and DC Logic Input Levels for Single-Ended Signals ............................................113
8.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals.........113
8.3 AC and DC Logic Input Levels for Differential Signals ...............................................116
8.3.1 Differential signal definition...................................................................................116
8.3.2 Differential swing requirements for clock (CK - CK#) and strobe
(DQS - DQS#) ........................................................................................................116
8.3.3 Single-ended requirements for differential signals.................................................117
8.4 Differential Input Cross Point Voltage ..........................................................................118
8.6 Slew Rate Definitions for Differential Input Signals.....................................................120
9 AC and DC Output Measurement Levels ..............................................................................121
9.1 Single Ended AC and DC Output Levels.......................................................................121
9.2 Differential AC and DC Output Levels .........................................................................121
9.6.1 Address and Control Overshoot and Undershoot Specifications............................125
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications.............126
9.7.1 Output Driver Temperature and Voltage sensitivity...............................................128
9.8.1 On-Die Termination (ODT) Levels and I-V Characteristics ..................................130
9.8.2 ODT DC Electrical Characteristics.........................................................................131
9.8.3 ODT Temperature and Voltage sensitivity.............................................................134
9.9 ODT Timing Definitions................................................................................................134
9.9.1 Test Load for ODT Timings ...................................................................................134
9.9.2 ODT Timing Definitions.........................................................................................135
10 IDD and IDDQ Specification Parameters and Test Conditions...........................................139
ii
JEDEC Standard No. 79-3F
Contents
10.1 IDD and IDDQ Measurement Conditions ...................................................................139
11 Input/Output Capacitance ....................................................................................................153
11.1 Input/Output Capacitance ............................................................................................153
12 .............................................................................................................................................155
12.1 Clock Specification......................................................................................................155
12.1.1 Definition for tCK(avg) ........................................................................................155
12.1.2 Definition for tCK(abs).........................................................................................155
12.1.3 Definition for tCH(avg) and tCL(avg)..................................................................155
12.1.4 Definition for tJIT(per) and tJIT(per,lck) .............................................................156
12.1.5 Definition for tJIT(cc) and tJIT(cc,lck) ................................................................156
12.1.6 Definition for tERR(nper).....................................................................................156
12.2 Refresh parameters by device density..........................................................................156
13 Electrical Characteristics and AC Timing ...........................................................................167
13.1 Timing Parameters for DDR3-800, DDR3-1067, DDR3-1333, and DDR3-1600.......167
13.6.1 Data Setup, Hold and Slew Rate Derating of DDR3-1866/2133..........................190
iii
JEDEC Standard No. 79-3F
List of Figures
Figure 1 —Qual-stacked / Quad-die DDR3 SDRAM x4 rank association . . . . . . . . . . . . . . . . . 12
Figure 2 —Qual-stacked / Quad-die DDR3 SDRAM x8 rank association . . . . . . . . . . . . . . . . . 12
Figure 3 —Qual-stacked / Quad-die DDR3 SDRAM x16 rank association . . . . . . . . . . . . . . . . 12
Figure 4 —Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 —Reset and Initialization Sequence at Power-on Ramping . . . . . . . . . . . . . . . . . . . . . 20
Figure 6 —Reset Procedure at Power Stable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7 —tMRD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8 —tMOD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9 —MR0 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10 —MR1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11 —MR2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12 —MR3 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13 —DLL-off mode READ Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 14 — DLL Switch Sequence from DLL-on to DLL-off . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15 —DLL Switch Sequence from DLL Off to DLL On . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16 —Change Frequency during Precharge Power-down . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17 —Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18 —Timing details of Write leveling sequence [DQS - DQS# is capturing
CK - CK# low at T1 and CK - CK# high at T2 . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19 —Timing details of Write leveling exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 20 —MPR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21 —MPR Readout of predefined pattern, BL8 fixed burst order, single readout . . . . . 51
Figure 22 —MPR Readout of predefined pattern, BL8 fixed burst order,
back-to-back readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 23 —MPR Readout predefined pattern, BC4, lower nibble then upper nibble . . . . . . . . 53
Figure 24 —MPR Readout of predefined pattern, BC4, upper nibble then lower nibble . . . . . . 54
Figure 25 —READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8) . . . . . . . . . . . . . . . . . . . . . 56
Figure 26 —READ Burst Operation RL = 9 (AL = 4, CL = 5, BL8) . . . . . . . . . . . . . . . . . . . . . 56
Figure 27 —READ Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 28 —Clock to Data Strobe Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 29 —Data Strobe to Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 30 —tLZ and tHZ method for calculating transitions and endpoints . . . . . . . . . . . . . . . . 60
Figure 31 —Method for calculating tRPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . . 61
Figure 32 —Method for calculating tRPST transitions and endpoints . . . . . . . . . . . . . . . . . . . . 61
Figure 33 —READ (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 34 —Nonconsecutive READ (BL8) to READ (BL8), tCCD=5 . . . . . . . . . . . . . . . . . . . 62
Figure 35 —READ (BC4) to READ (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 36 —READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 37 —READ (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 38 —READ (BL8) to READ (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 39 —READ (BC4) to READ (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 40 —READ (BC4) to WRITE (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 41 —READ (BL8) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 42 —READ to PRECHARGE, RL = 5, AL = 0, CL = 5, tRTP = 4, tRP = 5 . . . . . . . . . 67
Figure 43 —READ to PRECHARGE, RL = 8, AL = CL-2, CL = 5, tRTP = 6, tRP = 5 . . . . . . 67
Figure 44 —Write Timing Definition and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 45 —Method for calculating tWPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . 70
iv
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
