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88e6097数据手册.pdf
Section 1. Signal Description
1.1 Pin Description
Section 2. Application Examples
2.1 Examples using the 88E6097 Device
2.2 Device Physical Interfaces
2.2.1 10/100 PHY Interface
2.2.2 SERDES or (G)MII Interface
2.2.3 Digital Interface Options
2.2.4 PHY Polling Unit (PPU)
2.2.5 24 Port Switch Configuration
Section 3. Switch Core Functional Description
Section 4. Basic Switch Functions
4.1 Physical Switch Data Flow
4.2 Physical Interface
4.3 Media Access Controllers (MAC)
4.3.1 Backoff
4.3.2 Half-duplex Flow Control
4.3.3 Full-duplex Flow Control
4.3.4 Forcing Flow Control in the MAC
4.3.5 Jamming Control - Egress Limit
4.3.6 Jamming Control - Ingress Limit
4.3.7 Forcing Link, Speed, and Duplex in the MAC
4.3.8 MAC Based RMON/Statistics Counters
4.3.9 Policy Based RMON/Statistics Counters
4.4 Basic Switch Operation
4.4.1 Lookup Engine
4.4.2 Address Searching or Translation
4.4.3 Automatic Address Learning
4.4.4 Hardware Address Learn Limiting
4.4.5 Automatic Address Aging
4.4.6 CPU Directed Address Learning and Purging
4.4.7 802.1X Source MAC Address Checking
4.4.8 Multiple Address Database Support (FID)
Section 5. Normal Network Ports
5.1 Ingress Policy
5.1.1 Port States Filtering for 802.1D Spanning Tree
5.1.2 Source Address Filtering
5.1.3 Layer 2 Policy Control Lists (88E6097 Only)
5.2 VLANS
5.2.1 Port Based VLANs
5.2.2 802.1Q VLANs
5.2.3 802.1s Per VLAN Spanning Tree
5.3 Special Frame Handling
5.3.1 Switching Frames Back to their Source Port
5.3.2 Tunneling Frames through VLANs
5.3.3 ARP Mirroring
5.3.4 IGMP/MLD Trapping or Snooping
5.4 Quality of Service (QoS) Classification
5.4.1 IEEE Tagged Frame Priority Extraction
5.4.2 IPv4 and IPv6 Frame Priority Extraction
5.4.3 Default Priority
5.4.4 Initial Priority Selection
5.4.5 Frame Type Priority Override
5.4.6 Layer 2 Priority Override
5.5 Port Based Ingress Rate Limiting (PIRL)
5.6 Queue Controller
5.6.1 Frame Latencies
5.6.2 No Head-of-Line Blocking
5.6.3 QoS with and without Flow Control
5.6.4 Guaranteed Frame Delivery without Flow Control
5.6.5 The Queues
5.6.6 Per Port Fixed or Weighted Priority
5.6.7 Programmable Weighting Table (88E6097 Only)
5.7 Embedded Memory
5.8 Egress Policy
5.8.1 Forward Unknown/Secure Port
5.8.2 Forward Unknown for Multicasts
5.8.3 Secure 802.1Q VLANs
5.8.4 Tagging and Untagging Frames
5.8.5 Egress Rate Shaping
Section 6. Provider Mode Ports
6.1 Customer to Provider
6.2 Provider to Customer
6.2.1 Provider VID Processing
6.2.2 Provider QoS Processing
6.3 Customer to Customer
6.4 Provider to Provider
6.5 Recursive Provider Tag Stripping
6.6 Restrictions on Provider Ports
6.7 Restrictions on Customer Ports
Section 7. Distributed Switch Architecture (DSA) Ports
7.1 Forward DSA Tag
7.2 To_CPU DSA Tag
7.3 From_CPU DSA Tags
7.4 To_Sniffer DSA Tag
7.5 Cross-chip Features Using DSA Links
7.5.1 Cross-chip Flow Control
7.5.2 Cross-chip 802.1Q VLANs
7.5.3 Cross-chip Port Based VLANs
7.6 Switch Handling of DSA MGMT Frames
7.7 Proper Usage of DSA Tag Ports
7.8 Secure Control Technology (SCT)
7.9 Ether Type DSA Tag
Section 8. Advanced Switch Functions
8.1 Management Frames to and from the CPU
8.2 Spanning Tree Support
8.3 Ingress MGMT/BPDU Frame Detection
8.3.1 Reserved Multicast Address Support
8.3.2 New and Proprietary Protocol Support
8.4 Other Ingress MGMT Frame Detection
8.5 MGMT Frames to Normal or Provider Egress
8.6 Proper Connection to a Management CPU
8.7 Proper Connection to a Router
8.7.1 Switch Ingress Header for CPU Routers
8.7.2 Switch Egress Header for CPU Routers
8.8 MUX’ing or Ignoring Address Translation
8.8.1 Passing Frames to a Router
8.8.2 Operational, Administration, and Maintenance (OAM) Loopback
8.9 Port Mirroring Support
8.10 Port Trunking Support
8.10.1 Trunk Address Learning
8.10.2 Trunk Address Searching
8.10.3 Trunk Mapping
8.10.4 Load Balancing
8.11 Interrupt Controller
8.11.1 Device Interrupts
Section 9. Accessing Data Structures
9.1 Address Translation Unit Operations
9.1.1 Format of the ATU Database
9.1.2 Reading the Address Database
9.1.3 Loading & Purging an Entry in the Address Database
9.1.4 Flushing Entries
9.1.5 Moving or Removing Single Port Mappings
9.1.6 Servicing ATU Violations
9.1.7 ATU Statistics
9.2 VLAN Translation Unit Operations
9.2.1 Format of the VTU Database
9.2.2 Reading the VLAN Database
9.2.3 Loading and Purging an Entry in the VLAN Database
9.2.4 Flushing Entries
9.2.5 Servicing VTU Violations
9.2.6 Format of the STU Database
9.2.7 Reading the SID Database
9.2.8 Loading and Purging an Entry in the STU Database
9.2.9 Flushing Entries
Section 10. Remote Management
10.1 Request for Frame Format - Layer 2 and DSA Portion
10.1.1 RMU and Ether type DSA
10.1.2 RMU and Marvell® Header
10.2 Response Frame Format - Layer 2 and DSA Portion
10.2.1 Restrictions of Remote Management
10.3 Request Frame Format - Layer 3
10.3.1 The Initial Request Frame - GetID
10.4 Response Frame Format - Layer 3
10.4.1 The Initial Response Frame - GotID
10.4.2 Error Handling
10.5 Supported Requests and Responses
10.5.1 GetID (non-destructive)
10.5.2 Dump ATU (non-destructive)
10.5.3 Dump MIBs (non-destructive)
10.5.4 Dump MIBs and Clear (destructive)
10.5.5 Read/Write Register (may be destructive)
10.5.6 Error Response Frame (non-destructive)
Section 11. Physical Interface (PHY) Functional Description (P0 to P7)
11.1 Transmit PCS and PMA
11.1.1 100BASE-TX Transmitter
11.1.2 4B/5B Encoding
11.1.3 Scrambler
11.1.4 NRZ to NRZI Conversion
11.1.5 Pre-Driver and Transmit Clock
11.1.6 Multimode Transmit DAC
11.2 Receive PCS and PMA
11.2.1 10-BASE-T/100BASE-TX Receiver
11.2.2 AGC and Baseline Wander
11.2.3 ADC and Digital Adaptive Equalizer
11.2.4 Digital Phased Locked Loop (DPLL)
11.2.5 NRZI to NRZ Conversion
11.2.6 Descrambler
11.2.7 Serial to Parallel Conversion and 5B/4B Code-Group Alignment
11.2.8 5B/4B Decoder
11.2.8.1 FIFO
11.2.8.2 100BASE-FX Receiver
11.2.8.3 Far End Fault Indication (FEFI)
11.2.8.4 10BASE-T Receiver
11.2.9 Setting Cable Characteristics
11.2.10 Scrambler/Descrambler
11.2.11 Link Monitor
11.2.12 Auto-Negotiation
11.2.13 Register Update
11.2.14 Next Page Support
11.2.15 Status Registers
11.3 Power Management
11.3.1 Low Power Modes
11.3.2 MAC Interface and PHY Configuration for Low Power Modes
11.3.3 IEEE Power Down Mode
11.3.3.1 Energy Detect +TM
11.4 Far End Fault Indication (FEFI)
11.5 Virtual Cable Tester® Feature
11.6 Data Terminal Equipment (DTE) Detect
11.7 Auto MDI/MDIX Crossover
11.8 Copper Line Loopback
11.9 LED Interface
11.9.1 Parallel LED Interface
11.9.2 Using Two Color LEDs
11.9.3 Serial LED Interface (88E6097F Device Only)
11.9.4 Single and Dual LED Modes
11.9.4.1 Single LED Display Mode
11.9.4.2 Dual LED Display Mode
Section 12. Serial Management Interface (SMI)
12.1 MDC/MDIO Read and Write Operations
Section 13. Switch Register Description
13.1 Register Types
13.2 Multi-chip Addressing Mode
13.3 Single-chip Addressing Mode
13.4 Switch Port Registers
13.5 Switch Global Registers
13.6 Switch Global 2 Registers
13.6.1 PIRL Registers
Section 14. EEPROM Programming Format
Section 15. PHY Register Description
Section 16. Electrical Specifications
16.1 Absolute Maximum Ratings
16.2 Recommended Operating Conditions
16.3 Thermal Conditions for 88E6096/88E6097 devices 176-pin TQFP Package
16.4 Thermal Conditions for 88E6097F device 216-pin LQFP Package
16.5 Current Consumption
16.6 DC Electrical Characteristics
16.6.1 Digital Operating Conditions
16.6.2 SERDES Electrical Specifications
16.6.3 IEEE DC Transceiver Parameters
16.7 AC Electrical Specifications
16.7.1 Receiver AC Characteristics
16.7.2 Clock Timing
16.8 GMII Timing
16.8.1 GMII Transmit Timing
16.8.2 GMII Receive Timing
16.9 RGMII Timing
16.9.1 RGMII Timing for Different RGMII Modes
16.10 MII Timing
16.10.1 MII MAC Mode Clock Timing
16.10.2 MII Receive Timing - MAC Mode
16.10.3 MII Transmit Timing - MAC Mode
16.11 Serial Management Interface (SMI) Timing
16.11.1 SMI Clock Timing (CPU Set)
16.11.2 SMI Data Timing (CPU Set)
16.11.3 SMI Timing (PHY Set)
16.12 EEPROM Timing
16.12.1 2-Wire EEPROM Timing
16.12.2 4-Wire EEPROM Timing
16.13 SERDES (Serial Interface) Timing
16.14 IEEE AC Parameters (Ports 0-7)
Section 17. Package Mechanical Dimensions
Section 18. Ordering Information
18.1 Ordering Part Numbers and Package Markings
18.1.1 RoHS 6/6 Compliant Marking Examples
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Link Street® 88E6096/88E6097/
88E6097F Datasheet
8 FE + 3 GE Stackable Ethernet Switch with QoS
and 802.1Q
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
Doc. No. MV-S103922-00 Rev. B
July 2, 2007
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Document Status
Advance
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Information
Preliminary
Information
Final
Information
Revision Code: Rev. B
Advance
This document contains design specifications for initial product development. Specifications may change
without notice. Contact Marvell Field Application Engineers for more information.
This document contains preliminary data, and a revision of this document will be published at a later date.
Specifications may change without notice. Contact Marvell Field Application Engineers for more information.
This document contains specifications on a product that is in final release. Specifications may change without
notice. Contact Marvell Field Application Engineers for more information.
Technical Publication: 1.40
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Link Street® 88E6096/88E6097/88E6097F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express
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With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
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Copyright © 2007. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX,
PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP
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Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S103922-00 Rev. B
Copyright © 2007 Marvell
July 2, 2007, Advance
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Link Street® 88E6096/88E6097/88E6097F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
88E6097F, Port 9 supports an additional GMII mode.
These interfaces, along with BPDU handling for IEEE
802.1D Spanning Tree Protocol, 802.1w Rapid Span-
ning Tree, 802.1s Multiple VLAN Spanning Tree, pro-
grammable per-port VLAN configurations, 802.1Q and
Port States, support fully managed switches and truly
isolated WAN vs. LAN firewall applications. The
devices support 4,096 802.1Q VLAN IDs which can be
enabled on a per port basis. Three levels of 802.1Q
security is supported with error frame trapping and log-
ging.
The devices support multiple address databases (up
to 4096), which allows packet routing without modifica-
tion of the MAC address. This allows the same MAC
address to exist multiple times in the MAC Address
database with multiple port mappings, to completely
isolate the WAN from the LAN database.
The PHY and SERDES units in the devices are
designed with the Marvell® cutting-edge mixed-signal
processing technology for digital implementation of
adaptive equalization and clock data recovery. Special
power management techniques are used to facilitate
low power dissipation and high port count integration.
Both the PHY and MAC units in the devices comply
fully with the applicable sections of IEEE 802.3, IEEE
802.3u, and IEEE 802.3x standards.
The devices’ many operating modes can be config-
ured using SMI (serial management interface - MDC/
MDIO) and/or a low cost serial EEPROM, and/or by
special Remote Management ethernet frames. A stan-
dalone QoS mode is also supported.
Up to 32 88E6096/88E6097 devices can be cascaded.
One or more devices can be used to create larger
switches, e.g 24 FE + 2 GE or 48 FE + 4 GE. The
devices are designed for cost-sensitive low to high
port count switch systems that require Quality of Ser-
vice, Trunking, Stacking, and/or Spanning Tree.
OVERVIEW
The Marvell® 88E6096, 88E6097, and 88E6097F
v
5
devices are each single-chip 8-port 10/100 plus 3 port
Gigabit Ethernet switches. These devices support
‘Best-in-Class’ Quality of Service (QoS) and the high-
est ‘real-world’ performance. They are uniquely suited
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for Small-to-Medium Business (SMB) and Access
o
Switch applications.
These devices contain eight 10BASE-T/100BASE-TX
transceivers (PHYs), and three gigabit SERDES inter-
faces that can be used to connect to external Marvell
10/100/1000 triple speed Ethernet transceivers
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(PHYs). The 88E6096/88E6097 devices are designed
1
to work in all environments. True Plug-and-Play is sup-
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ported with Auto-Crossover, Auto-Negotiation, and
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Auto-Polarity in the PHYs, along with bridge loop pre-
4
vention (using Port States).
The 88E6096 is designed for SOHO and SMB switch
applications, while the 88E6097 is for Access/Demar-
cation switch applications. The 88E6097F device is
available for Access applications as well, and includes
fiber enable and controls on all ports.
The devices offer enhanced stacking capabilities that
enable multiple devices and/or systems to act as a sin-
gle unit. These features include the ability to Link
Aggregate ports between boxes in a stack, monitor
any port from any other port in the stack, and create
port-based VLANs using any port(s) within the stack.
The devices contain eleven independent 802.3 media
access controllers (MACs), a high-speed, non-block-
ing four traffic class QoS switch fabric that uses the
unique, patented Marvell Dynamic Queue Limit archi-
tecture. The QoS architecture switches packets into
one of four traffic class queues based upon Port, IEEE
802.1p, IPv4 Type of Service (TOS) or Differentiated
Services (Diff-Serv), IPv6 Traffic Class, 802.1Q VLAN
ID, DA MAC address or SA MAC address. The
devices also contain a high-performance address
lookup engine with support for up to 8K active nodes,
and a 1 Mbit frame buffer memory. Back-pressure and
Pause frame-based flow control schemes are included
to support zero packet loss under temporary traffic
congestion. The MAC units in the devices comply fully
with the applicable sections of IEEE 802.3.
The ninth and tenth ports’ optional (G)MII (or MII) inter-
face supports a direct connection to Management or
Router CPUs with integrated MACs. The tenth port
also supports an RGMII interface that operates as a
1000 Mbps, full-duplex port. For the 88E6096/
88E6097 devices, Port 9 is only MII-PHY or MII-MAC
mode capable, while Port 10 can be configured in
either GMII, MII-PHY or MII-MAC mode. In the
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
8 FE + 2 1000BASE-X using a single 88E6096 or
88E6097 device
24 FE + 2 GE SMB or Access switch using three
88E6096 or three 88E6097 devices
48 FE + 4 GE SMB or Access switch using six
88E6096 or six 88E6097 devices with a single
88E6185, 98DX106, or 98DX107
SOHO/SMB router with eight FE and two GE
ports
Fiber to the Curb cascade applications
APPLICATIONS
•
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S103922-00 Rev. B
Copyright © 2007 Marvell
July 2, 2007, Advance
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‘Best-in-Class’ per port TCP/IP Ingress Rate Lim-
5
iting along with independent Storm Prevention
5 Ingress Rate Limiting buckets per port, support-
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ing Rate-based and Priority-based rate limiting
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(88E6097 only)
Non-Rate Limited frames based on SA or DA
Layer 2 Policy Control List (PCL) enables drop,
trap, or mirroring based on SA, DA, VID, Ether-
type, VBAS, PPPoE, UDP, and DHCP Option 82
(88E6097 only)
9
Remote Management capabilities allow device
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configuration and readback via Ethernet frames
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Per port, programmable MAC address limiting
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Quality of Service support with four traffic classes
QoS determined by Port, IEEE 802.1p tagged
frames, IPv4’s Type of Service (TOS) & Differenti-
ated Services (DS), IPv6’s Traffic Class 802.1Q
VID, Destination MAC address, or Source MAC
address
Frame priority overrides based on SA, DA, or VID
Queue priority overrides based on SA, DA, VID,
ARP, or Snoop
Strict, Weighted, or mixed mode QoS selectable
per port
Globally Programmable QoS weighting via a 128-
entry table (88E6097 only)
802.1Q VLAN support for the full 4,096 VLAN IDs
Supports multiple provider ports within a single
chip via a programmable Ethertype per port
Enhanced 802.1s Per VLAN Spanning Tree sup-
porting up to 64 spanning tree instances
Support for protected port across multiple devices
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• MAC SA based 802.1X authentication
•
HIGHLIGHTED FEATURES
•
FEATURES
• Marvell® Header for increased Routing perfor-
Link Street® 88E6096/88E6097/88E6097F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
mance
Shared 1 Mbit on-chip memory-based switch fab-
ric with true non-blocking switching performance
High performance lookup engine with support for
up to 8K MAC address entries with automatic
learning and aging
Supports the Marvell Distributed Switching Archi-
tecture (DSA) for STP, up to 32 cascaded
devices, and CPU-directed packet processing
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
Port Trunking and Port Monitoring/Mirroring
across chips
Egress tagging/untagging selectable per port or
by 802.1Q VLAN ID
Port based VLANs supported in any combination
across multiple chips
Port States & BPDU handling for Spanning Tree
28 32-bit and 2 64-bit RMON Counters per port
Ports 8, 9 & 10 are independent triple speed
SERDES transceivers to interface with Marvell
Alaska® gigabit copper PHYs and can optionally
be configured as fiber ports (1000BASE-X) with
direct connection to lasers
Ports 9 and 10 can support GMII Mode (full-
duplex), MII-MAC Mode (Forward) or MII-PHY
Mode (Reverse—full-duplex) interface options for
management and firewall applications (Port 9 is
MII only in the 88E6096/88E6097 devices)
Port 10 supports an additional RGMII interface
that operates at 1000 Mbps, full-duplex only
Integrated with eight independent Auto-Crossover
Fast Ethernet transceivers fully compliant with the
applicable sections of IEEE802.3 and
IEEE802.3u
Flexible LED support for Link, Speed, Duplex
Mode, Collision, and Tx/Rx Activities
Supports a low-cost 25 MHz XTAL clock source
Supports 4-Wire 93C56/93C66 or 2-Wire 24C01/
24C02/24C04 EEPROMs
Single chip integration of an 11 port 8-FE + 3-GE
QoS switch and memory in a 20 x 20 mm 176-pin
TQFP package (88E6096/88E6097 device), or 24
x 24 mm 216 LQFP (88E6097F device)
Pin compatible to the previous generation
88E6092 and 88E6095 devices
88E6097 and 88E6097F devices available in
Commercial and Industrial grade
Low power dissipation PAVE = 1.5W
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S103922-00 Rev. B
Copyright © 2007 Marvell
July 2, 2007, Advance
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88E6096
Yes (16/8)
y
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b
g
s
e
r
u
t
a
e
F
S
o
Q
N
A
L
V
d
wjx
o
1 Mbit
1 Mbit
8 + 3
0
1/2
1
8 + 3
0
1/2
1
1632 bytes
1 Mbit
fi-io
g
5
1632 bytes
1632 bytes
8
cjw
v
u
5
v
Table 1:
5
n
w
SOHO/SMB
Switches
88E6097
Access
Switches
88E6097F
Access
Switches
88E6096/88E6097/88E6097F Device Differences
8K
4
Yes
Yes
Yes
No
Yes
4096
4096
Yes
Yes
Yes
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
Description
FE PHY and GE SERDES
FE Fiber Support
1
# GMII/MII (Shared w/SERDES)
k
RGMII
9
Max Frame Size
qts
1
Packet Buffer Memory
q
# MAC Addresses
Queues per Port
802.1p, Port, TOS/DS, IPv6, TC, MAC
Priority Overrides (DA/SA/VID/ARP/Snoop)
Mixed Mode QoS per port
Programmable Weighting
Port -based and 802.1Q VLANs
Maximum number of Shared 802.1Q VLANs
Maximum number of Independent 802.1Q VLANs
Double Tagging (Q in Q)
Supports Multiple Provider Ports
Stacking Support
Cross -chip Trunking (#Trunks/#Ports)
Cross-chip Port Based VLANs
Cross-chip Flow Control
Cross-chip Protected Port
Distributed Switching Architecture (DSA) Tag Support
Remote Management
Ethertype DSA
Layer 2 Policy Control Lists (PCL)
802.1D/w/s Spanning Tree
Port Mirroring
IPv4 IGMP & IPv6 MLD Snooping
Ingress Rate Limiting Resources
Priority-based Ingress Rate Limiting
Egress Rate Shaping
802.1X Port and MAC-based Authentication
Hardware MAC Address Limiting per port
Industrial Grade
Package
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
2/port
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
5/port
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
5/port
Yes
Yes
Yes
Yes
Yes
8K
4
Yes
Yes
Yes
Yes
Yes
4096
4096
Yes
Yes
Yes
8K
4
Yes
Yes
Yes
Yes
Yes
4096
4096
Yes
Yes
Yes
Document Classification: Proprietary Information
CONFIDENTIAL
176-pin LQFP 216-pin LQFP
Doc. No. MV-S103922-00 Rev. B
Copyright © 2007 Marvell
p
i
h
c
-
s
s
o
r
C
t
n
e
m
e
g
a
n
a
M
Yes (16/8)
Yes (16/8)
July 2, 2007, Advance
r
e
h
t
O
176-pin LQFP
Page 5
atio
g Intern
n
RESETn
Look-up Engine
s
r
e
i
t
s
g
e
R
h
c
t
i
w
S
Table
w/Auto Crossover
w
n
P0_RX
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
w/Auto Crossover
Register
Loader
CPU/
Reg
Interface
MAC
MAC
MAC
MAC
P5_TX
P5_RX
P6_TX
P6_RX
P7_TX
P7_RX
P1_TX
P1_RX
P2_TX
P2_RX
P3_TX
P3_RX
P4_TX
P4_RX
q
c
MAC
2
c
MAC
k
y
2
5
v
5
XTAL_IN
XTAL_OUT
1
b
g
e
eik
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
fi-io
P0_TX
g
5
10BASE-T
100BASE-TX
Transceiver
10BASE-T
100BASE-TX
Transceiver
10BASE-T
100BASE-TX
Transceiver
10BASE-T
100BASE-TX
Transceiver
10BASE-T
100BASE-TX
Transceiver
10BASE-T
100BASE-TX
Transceiver
1 Mbit Embedded Switch Fabric Memory
MDC_CPU
MDIO_CPU
INTn
Queue Controller with
Four Traffic Classes
4 * W
Ingress/
Egress
p
Processing
9
& Limiting
4
EE_CS
EE_CLK
EE_DIN
EE_DOUT
9
qts
1
d
wjx
o
w/Auto Crossover
8
10BASE-T
cjw
100BASE-TX
v
Transceiver
u
w/Auto Crossover
1
Link Street® 88E6096/88E6097/88E6097F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
88E6096/88E6097 176 TQFP Top Level Block Diagram
Document Classification: Proprietary Information
CONFIDENTIAL
Doc. No. MV-S103922-00 Rev. B
MAC or PHY Mode
GMII/RGMII/MII Interface
Copyright © 2007 Marvell
MAC or PHY Mode
MII Interface
July 2, 2007, Advance
28 32-bit and 2 64-bit
RMON Counters per Port
10BASE-T
100BASE-TX
Transceiver
Triple Speed &
1000BASE-X
SERDES
Triple Speed &
1000BASE-X
SERDES
Triple Speed &
1000BASE-X
SERDES
Fiber Enable
and Controls
Fiber Enable
and Controls
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Fiber Enable
and Controls
External
PHY
Reg
Interface
MDC_PHY
MDIO_PHY
64 Entry 802.1s per VLAN
4,096 Entry 802.1Q VLAN
Remote Management Unit
P10_TX
P10_RX
P8_TX
P8_RX
P9_TX
P9_RX
8K Entry MAC Address
Table
MAC
MAC
GMAC
GMAC
FE PHY
LEDs
3 x 8 LEDs
r
e
l
l
o
r
t
n
o
C
t
r
o
P
t
l
o
S
e
m
T
i
SW_MODE[1:0]
RMU
Frame
Buffer
Port State Table
PHY
Polling
Unit
GMAC
Plus Policy MIBs
Page 6
atio
g Intern
n
2
c
q
MAC
c
Register
Loader
10BASE-T
10BASE-T
10BASE-T
10BASE-T
10BASE-T
10BASE-T
10BASE-T
w
n
MAC
MAC
MAC
MAC
MAC
MAC
CPU/
Reg
Interface
P5_TX
P5_RX
P6_TX
P6_RX
P7_TX
P7_RX
P1_TX
P1_RX
P2_TX
P2_RX
P3_TX
P3_RX
P4_TX
P4_RX
5
v
5
fi-io
XTAL_IN
XTAL_OUT
p
9
4
P0_TX
g
5
P0_RX
e
eik
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Fiber Enable
and Controls
Fiber Enable
and Controls
100BASE-TX/FX
Transceiver
w/Auto Crossover
100BASE-TX/FX
Transceiver
w/Auto Crossover
100BASE-TX/FX
Transceiver
w/Auto Crossover
Fiber Enable
and Controls
Fiber Enable
and Controls
100BASE-TX/FX
Transceiver
w/Auto Crossover
Fiber Enable
and Controls
100BASE-TX/FX
Transceiver
w/Auto Crossover
Fiber Enable
and Controls
Fiber Enable
and Controls
1 Mbit Embedded Switch Fabric Memory
MDC_CPU
MDIO_CPU
INTn
4 * W
Queue Controller with
Four Traffic Classes
Transceiver
u
k
10BASE-T
1
EE_CS
EE_CLK
EE_DIN
EE_DOUT
1
Ingress/
b
Egress
g
Processing
& Limiting
9
qts
1
d
wjx
o
y
100BASE-TX/FX
2
Transceiver
w/Auto Crossover
100BASE-TX/FX
8
cjw
v
w/Auto Crossover
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
88E6097F 216 LQFP Top Level Block Diagram
Document Classification: Proprietary Information
CONFIDENTIAL
P8_TX
Fiber Enable
and Controls P8_RX
Doc. No. MV-S103922-00 Rev. B
MAC or PHY Mode
GMII/RGMII/MII Interface
Copyright © 2007 Marvell
MAC or PHY Mode
GMII/MII Interface
July 2, 2007, Advance
28 32-bit and 2 64-bit
RMON Counters per Port
100BASE-TX/FX
Transceiver
w/Auto Crossover
Fiber Enable
and Controls
Fiber Enable
and Controls
Triple Speed &
1000BASE-X
SERDES
Triple Speed &
1000BASE-X
SERDES
Triple Speed &
1000BASE-X
SERDES
Fiber Enable
and Controls
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
Ingress/
Egress
Processing
& Limiting
External
PHY
Reg
Interface
MDC_PHY
MDIO_PHY
64 Entry 802.1s per VLAN
4,096 Entry 802.1Q VLAN
P10_TX
P10_RX
Remote Management Unit
8K Entry MAC Address
Table
P9_TX
P9_RX
r
e
l
l
o
r
t
n
o
C
t
r
o
P
t
l
o
S
e
m
T
i
3 x 8 LEDs
Serial LEDs
SW_MODE[1:0]
MAC
GMAC
GMAC
PHY
Polling
Unit
RMU
Frame
Buffer
Plus Policy MIBs
FE PHY
LEDs
Table
Port State Table
Look-up Engine
s
r
e
i
t
s
g
e
R
h
c
t
i
w
S
RESETn
Page 7
GMAC
atio
g Intern
n
g
2
c
5
v
5
q
c
p
k
y
2
w
n
9
4
g
5
u
1
1
b
fi-io
e
eik
4 * W
9
qts
1
8
cjw
v
d
wjx
o
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
gb149pcq1qts9c22yk1uvcjw8owjxd5gfi-ionw5v54 * Weikeng International Co., Ltd.
MARVELL CONFIDENTIAL, UNDER NDA# 12154502
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