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dw_apb_rtc_db.pdf
SolvNet
DesignWare
Documentation Overview
Release Notes
Installation Guide
Contents
Preface
Organization
Related Documentation
Document Revision History
Web Resources
Customer Support
1 Product Overview
1.1 DesignWare System Overview
1.2 General Product Description
1.2.1 DW_apb_rtc Block Diagram
1.3 Features
1.4 Standards Compliance
1.5 Verification Environment Overview
1.6 Licenses
1.7 Where To Go From Here
2 Building and Verifying a Component or Subsystem
2.1 Setting up Your Environment
2.2 Overview of the coreConsultant Configuration and Integration Process
2.2.1 coreConsultant Usage
2.2.2 Configuring the DW_apb_rtc within coreConsultant
2.2.3 Creating Gate-Level Netlists within coreConsultant
2.2.4 Verifying the DW_apb_rtc within coreConsultant
2.2.5 Running Leda on Generated Code with coreConsultant
2.3 Overview of the coreAssembler Configuration and Integration Process
2.3.1 coreAssembler Usage
2.3.2 Configuring the DW_apb_rtc within a Subsystem
2.3.3 Creating Gate-Level Netlists within coreAssembler
2.3.4 Verifying the DW_apb_rtc within coreAssembler
2.3.5 Running Leda on Generated Code with coreAssembler
2.4 Database Files
2.4.1 Design/HDL Files
2.4.1.1 RTL-Level Files
2.4.1.2 Simulation Model Files
2.4.2 Synthesis Files
2.4.3 Verification Reference Files
3 Functional Description
3.1 Up Counter
3.2 Clock Relationship
3.3 Match Register and Interrupt Generation
3.4 Reset Condition
3.5 Design for Test
4 Parameters
4.1 Parameter Descriptions
5 Signals
5.1 DW_apb_rtc Interface Diagram
5.2 DW_apb_rtc Signal Descriptions
6 Registers
6.1 Bus Interface
6.2 Register Memory Map
6.3 Register and Field Descriptions
6.3.0.1 RTC_CCVR
6.3.0.2 RTC_CMR
6.3.0.3 RTC_CLR
6.3.0.4 RTC_CCR
6.3.0.5 RTC_STAT
6.3.0.6 RTC_RSTAT
6.3.0.7 RTC_EOI
6.3.0.8 RTC_COMP_VERSION
7 Programming the DW_apb_rtc
7.1 Programming Considerations
8 Verification
8.1 Overview of Vera Tests
8.1.1 Reset
8.1.2 Registers
8.1.3 Interrupts
8.1.4 Counter Enable Mode
8.1.5 Wrap Mode
8.2 Overview of DW_apb_rtc Testbench
8.3 Running Simulations from the Command Line
8.4 Command Line Output Files
9 Integration Considerations
9.1 Reading and Writing from an APB Slave
9.1.1 Reading From Unused Locations
9.1.2 32-bit Bus System
9.1.3 16-bit Bus System
9.1.4 8-bit Bus System
9.2 Write Timing Operation
9.3 Read Timing Operation
9.4 Accessing Top-level Constraints
9.5 Coherency
9.5.1 Writing Coherently
9.5.1.1 Identical Clocks
9.5.1.2 Synchronous Clocks
9.5.1.3 Asynchronous Clocks
9.5.2 Reading Coherently
9.5.2.1 Synchronous Clocks
9.5.2.2 Asynchronous Clocks
A Glossary
Index
A
B
C
D
E
F
G
H
I
L
M
N
O
P
R
S
T
U
V
W
Z
DesignWare DW_apb_rtc Databook
DW_apb_rtc
Version 2.03a
September 2010
DesignWare DW_apb_rtc Databook
Copyright Notice and Proprietary Information
Copyright © 2010 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information
that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or
copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced,
transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written
permission of Synopsys, Inc., or as expressly provided by the license agreement.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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Synopsys, Inc.
700 E. Middlefield Road
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www.synopsys.com
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DesignWare DW_apb_rtc Databook
Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.1 DesignWare System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.2.1 DW_apb_rtc Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.4 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5 Verification Environment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.6 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.7 Where To Go From Here . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Chapter 2
Building and Verifying a Component or Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1 Setting up Your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2 Overview of the coreConsultant Configuration and Integration Process . . . . . . . . . . . . . . . . . . . . . . .14
2.2.1 coreConsultant Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2.2 Configuring the DW_apb_rtc within coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2.3 Creating Gate-Level Netlists within coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2.4 Verifying the DW_apb_rtc within coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.2.5 Running Leda on Generated Code with coreConsultant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.3 Overview of the coreAssembler Configuration and Integration Process . . . . . . . . . . . . . . . . . . . . . . .17
2.3.1 coreAssembler Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.3.2 Configuring the DW_apb_rtc within a Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.3.3 Creating Gate-Level Netlists within coreAssembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.3.4 Verifying the DW_apb_rtc within coreAssembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.3.5 Running Leda on Generated Code with coreAssembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.4 Database Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.4.1 Design/HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.4.2 Synthesis Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4.3 Verification Reference Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Chapter 3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1 Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.2 Clock Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.3 Match Register and Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.4 Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
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DesignWare DW_apb_rtc Databook
3.5 Design for Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 4
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.1 Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Chapter 5
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.1 DW_apb_rtc Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.2 DW_apb_rtc Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Chapter 6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.1 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
6.2 Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
6.3 Register and Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Chapter 7
Programming the DW_apb_rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.1 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Chapter 8
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.1 Overview of Vera Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.1.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.1.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
8.1.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.1.4 Counter Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.1.5 Wrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.2 Overview of DW_apb_rtc Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
8.3 Running Simulations from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
8.4 Command Line Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Chapter 9
Integration Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.1 Reading and Writing from an APB Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.1.1 Reading From Unused Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
9.1.2 32-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.1.3 16-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9.1.4 8-bit Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
9.2 Write Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
9.3 Read Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
9.4 Accessing Top-level Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
9.5 Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
9.5.1 Writing Coherently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
9.5.2 Reading Coherently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Appendix A
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
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DesignWare DW_apb_rtc Databook
Preface
Preface
This databook provides information that you need to interface the DW_apb_rtc component to the Advanced
Peripheral Bus (APB). This component conforms to the AMBA Specification, Revision 2.0 from ARM.
The information in this databook includes a functional description, signal and parameter descriptions, and a
memory map. Also provided are an overview of the component testbench, a description of the tests that are
run to verify the coreKit, and synthesis information for the coreKit.
Organization
The chapters of this databook are organized as follows:
❖ Chapter 1, “Product Overview,” provides a system overview, a component block diagram, basic
features, and an overview of the verification environment.
❖ Chapter 2, “Building and Verifying a Component or Subsystem,” introduces you to using the
DW_apb_rtc within the coreAssembler and coreConsultant tools.
❖ Chapter 3, “Functional Description,” describes the functional operation of the DW_apb_rtc.
❖ Chapter 4, “Parameters,” identifies the configurable parameters supported by the DW_apb_rtc.
❖ Chapter 5, “Signals,” provides a list and description of the DW_apb_rtc signals.
❖ Chapter 6, “Registers,” describes the programmable registers of the DW_apb_rtc.
❖ Chapter 7, “Programming the DW_apb_rtc,” provides information needed to program the
configured DW_apb_rtc.
❖ Chapter 8, “Verification,” provides information on verifying the configured DW_apb_rtc.
❖ Chapter 9, “Integration Considerations,” includes information you need to integrate the configured
DW_apb_rtc into your design.
❖ Appendix A, “Glossary,” provides a glossary of general terms.
Related Documentation
To see a complete listing of documentation within the DesignWare Synthesizable Components for AMBA 2,
refer to the Guide to Documentation for DesignWare Synthesizable Components for AMBA 2 and AMBA 3 AXI.
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Preface
DesignWare DW_apb_rtc Databook
Document Revision History
This section tracks the significant documentation changes that occur from release-to-release and during a
release from version 2.01d onward.
Databook Revision History
Table 1-1
Version Databook Date Description
2.03a
September 2010 Corrected names of include files and vcs command used for simulation
2.02a
Dec 2009
Updated databook to new template for consistency with other IIP/VIP/PHY databooks.
2.02a
May 2008
Removed references to QuickStarts, as they are no longer supported.
2.02a
October 2008
Version change for 2008.10a release.
2.01e
June 2008
Version change for 2008.06a release.
2.01d
Jan 2008
Updated for revised installation guide and consolidated release notes titles; changed
references of “Designware AMBA” to simply “DesignWare.”
2.01d
June 2007
Version change for 2007.06a release.
Web Resources
❖ DesignWare IP product information: http://www.designware.com
❖ Your custom DesignWare IP page: http://www.mydesignware.com
❖ Documentation through SolvNet: http://solvnet.synopsys.com (Synopsys password required)
❖ Synopsys Common Licensing (SCL): http://www.synopsys.com/keys
Customer Support
To obtain support for your product:
❖ First, prepare the following debug information, if applicable:
✦ For environment setup problems or failures with configuration, simulation, or synthesis that
occur within coreConsultant or coreAssembler, use the following menu entry:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This menu entry gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the file
/debug.tar.gz.
✦ For simulation issues outside of coreConsultant or coreAssembler:
✧ Create a waveforms file (such as VPD or VCD)
✧ Identify the hierarchy path to the DesignWare instance
✧ Identify the timestamp of any signals or locations in the waveforms that are not understood
❖ Then, contact Support Center, with a description of your question and supplying the above
information, using one of the following methods:
✦ For fastest response, use the SolvNet website. If you fill in your information as explained below,
your issue is automatically routed to a support engineer who is experienced with your product.
The Sub Product entry is critical for correct routing.
6
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DesignWare DW_apb_rtc Databook
Preface
Go to http://solvnet.synopsys.com/EnterACall and click on the link to enter a call.
Provide the requested information, including:
✧ Product: DesignWare Library IP
✧ Sub Product: AMBA
✧ Tool Version:
✧ Problem Type:
✧ Priority:
✧ Title: DW_apb_rtc
✧ Description: For simulation issues, include the timestamp of any signals or locations in
waveforms that are not understood
After creating the case, attach any debug files you created in the previous step.
✦ Or, send an e-mail message to support_center@synopsys.com (your email will be queued and
then, on a first-come, first-served basis, manually routed to the correct support engineer):
✧ Include the Product name, Sub Product name, and Tool Version number in your e-mail (as
identified above) so it can be routed correctly.
✧ For simulation issues, include the timestamp of any signals or locations in waveforms that
are not understood
✧ Attach any debug files you created in the previous step.
✦ Or, telephone your local support center:
✧ North America:
Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.
✧ All other countries:
http://www.synopsys.com/Support/GlobalSupportCenters
September 2010
Synopsys, Inc.
SolvNet
DesignWare.com
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Preface
DesignWare DW_apb_rtc Databook
8
SolvNet
DesignWare.com
Synopsys, Inc.
September 2010
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