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eDP v1.4b d3.pdf
Contents
Tables
Figures
DPCD Registers that Differ from DP v1.3
Preface
1 Overview
1.1 Background
1.2 Acronyms
1.3 Glossary
1.4 References
2 eDP System Architecture
2.1 eDP System Application
2.2 eDP Support by Source and Sink Devices
2.3 Multi-SST Architecture
3 eDP v1.4b Deviations from DP v1.3
3.1 Background
3.2 eDP Implementation
3.3 eDP v1.4b-specific Register Summary
3.4 eDP AUX Link Services
3.5 Display Authentication and Content Protection Support
3.6 Panel Input Power (LCDVCC)
3.7 Main Stream Attribute Data
3.8 Multi-SST Operation
3.8.1 Multi-SST Architecture Overview
3.8.2 Multi-SST Operation Source Configuration
3.8.3 Multi-SST Operation with Two SST Links, One Lane Each (2x1)
3.8.4 Multi-SST Operation with Two SST Links, Two Lanes Each (2x2)
3.8.5 Multi-SST Operation with Four SST Links, One Lane Each (4x1)
3.8.6 Multi-SST Operation with Pixels Overlapping Adjacent Panel Segments
3.8.7 Multi-SST Operation DPCD Capabilities Register
3.8.8 Multi-SST Operation Timing Requirements (Dependent Multi-SST Operation Links Only)
3.8.9 Sink CRC Registers for Multi-SST Operation
4 eDP Electrical Specification Extension
4.1 Introduction
4.2 Interconnect Reference Points
4.3 Main-Link TX TP1 Differential Signal Voltage
4.3.1 Link Training
4.3.2 Vdiff Training Table
4.3.2.1 Special Training Tables
4.3.2.1.1 Rules for Custom Training Tables
4.3.2.1.2 Special Training Table Examples
4.4 Main-Link Electrical Specification Table
4.5 Link Transfer Rates and Jitter Budget
4.5.1 Recommended Link Transfer Rates
4.5.2 Differential Noise Budget
4.5.3 Differential Noise Budget Application
4.5.3.1 Custom Link Transfer Rates
4.5.3.1.1 Custom Transfer Rate Example 1 – 1920x1080 CVT Reduced Blanking, 24bpp Using a Single eDP Lane
4.5.3.1.2 Custom Transfer Rate Example 2 – 1920x1080 CVT Reduced Blanking, 24bpp Using Two eDP Lanes
4.5.3.1.3 Custom Transfer Rate Example 3 – Handheld with 19.2MHz Reference Clock
4.5.3.1.4 Custom Transfer Rate Example 4 – Handheld with 26MHz Reference Clock
4.6 Main-Link Source Device Eye Diagrams
4.6.1 TP3_EQ EYE Requirements
4.6.2 TP3_EQ Reference Equalizers
4.7 AUX CH
4.7.1 AUX CH Electrical Sub-block
4.7.1.1 Differential Voltage/Timing (EYE) Diagram for Manchester-II Transactions
4.8 Link Rate Discovery and Selection
5 Advanced Link Power Management
5.1 Power Management States of DPRX in a Downstream Device
5.2 Power Management Signaling
5.2.1 PHY Layer Power-Down
5.2.2 PHY Layer Wake
5.3 Configuration
5.3.1 Discovery, Enabling, and Disabling
5.4 Advanced Link Power Management DPCD Fields
6 Panel Self Refresh
6.1 PSR Overview
6.1.1 Architecture Overview
6.1.1.1 Source Device Responsibilities
6.1.1.2 Sink Device Responsibilities
6.1.2 Configuration
6.1.3 PSR Entry/Exit Protocols
6.1.3.1 PSR States
6.1.3.1.1 Source Device PSR States
6.1.3.1.2 Sink Device PSR States
6.1.3.2 PSR Entry
6.1.3.2.1 PSR Entry Link Management
6.1.3.2.1.1 Source Device Transmitter OFF
6.1.3.2.1.2 Source Device Transmitter Active
6.1.3.3 PSR Exit
6.1.3.3.1 PSR Exit Link Management
6.1.3.3.1.1 Source Device Main-Link Transmitter Is Turned OFF
6.1.3.3.1.2 Source Device Main-Link Transmitter Is Active
6.1.3.4 PSR Entry Abort
6.1.3.5 Single-frame Updates
6.1.3.5.1 Source Device Transmitter OFF
6.1.3.5.2 Source Device Transmitter Active
6.1.3.5.3 PSR Exit after Single-frame Update
6.1.3.5.4 Single-frame Update Immediately after PSR Entry
6.1.3.6 Burst Single-frame Updates
6.1.4 Error Management/Recovery
6.1.4.1 CRC Verification Performed in Source Device
6.1.4.2 CRC Verification Performed in Sink Device
6.2 Self Refresh with Selective Update (PSR2) Overview
6.2.1 Selective Update
6.2.2 Configuration
6.2.3 PSR2 States
6.2.4 PSR2 Command and Data Transport
6.2.5 Data Integrity Check and Corrective Action
6.3 PSR DPCD Fields
6.4 PSR SDP Support
7 AUX-based Source-to-Sink Device Active Video Timing Synchronization
7.1 Introduction
7.2 AUX Frame Sync DPCD Fields
8 Compressed Display Stream Transport Services
8.1 Introduction
8.2 Architecture Overview
8.3 Configuration – Discovery, Enabling, and Disabling
8.4 Framing and Compressed Stream Mapping
8.5 Picture Parameter Set Packet
8.5.1 PPS Packet Header
8.5.2 PPS Packet Payload
8.6 PSR in DSC Configuration
8.6.1 PSR SDP in DSC Configuration
8.6.2 PSR2 Selective Update in DSC Configuration
8.7 DSC DPCD Fields
9 Multi-Touch over AUX
9.1 Requirements and Scope
9.2 Device Discovery
9.3 Capability Discovery
9.4 Boot Mode
9.5 Sink Device Configuration
9.6 Register Layout and Access Rules
9.6.1 HID Class Descriptors
9.6.2 HID Report Descriptors
9.6.3 HID Reports Layout
9.6.3.1 Touch Sink Device Generated Reports
9.6.3.2 Touch Source Device Generated Reports
9.6.3.3 Report IDs
9.7 Data Transfer
9.7.1 Source Device Interrupt-based Data Access to Input or Feature Report
9.7.2 Source Device Polled Data Access to Input or Feature Report
9.7.3 Combination of Source Device Interrupt-based and Polled Data Access
9.7.4 Sink Device Data Access to Output Report
9.7.5 Sink Device Data Access to Feature Report
9.8 Report Freshness
9.9 Concurrency Definition
9.9.1 Concurrency of Touch with Keyboard
9.9.2 Concurrency of Touch with Mouse
9.9.3 Concurrency of Touch with Keyboard and Mouse
9.9.4 Sink Device Limitation Regarding Multiple Keyboard or Mouse Functions
9.10 DP Touch Example
9.10.1 HID Descriptor
9.10.2 Report Descriptor
9.10.3 REPORT_DATA Layout
9.11 Multi-Touch DPCD Fields
10 eDP Display Control
10.1 Display Backlight Control Using DPCD Registers
10.2 LCD Panel Self-Test (Informative)
10.3 Display Control DPCD Fields
11 Power Sequencing
12 eDP Connector Pin Assignments
A Lane Rate/Count vs. Supported Pixel Bandwidth (Informative)
A.1 Number of Main-Link Lanes vs. Video Mode Support (Informative)
B Electrical Specification Development
B.1 End-to-End Description
B.2 TX I/O Assumptions
B.3 End-to-End Channel EYE Mask, RX_EQ
B.4 RX Reference Equalizer
C Usage Guide for Multi-SST Operation with Segmented Panel Display
C.1 Introduction
C.2 Multi-SST Architecture Theory of Operation
C.3 Panel Self Refresh (PSR2) with Multi-SST Operation
D Features Required for the VESA eDP Notebook Profile (Policy Requirement)
E Main Contributor History (Previous Versions)
VESA LOGO HERE
39899 Balentine Drive, Suite 125
Newark, CA 94560
Phone: 510 651 5122
Fax: 510 651 5127
URL: www.vesa.org
VESA Proposed Embedded DisplayPort
(eDP) Standard
v1.4b d3
29 June, 2015
Purpose
This Standard defines requirements and options of a standardized display panel interface for embedded
display applications. It is based on VESA DisplayPort Standard Version 1.3 (DP v1.3) and includes
implementation-specific options recommended for consideration by the system integrator.
Summary
DP v1.3 is a scalable and extendable video data interface developed for use in both embedded (internal) and
external (box-to-box) applications. While DisplayPort does reference embedded applications, it is primarily
oriented toward external applications with emphasis on interoperability between system vendors and
interconnect cables. This Standard defines a feature set of an embedded version of DisplayPort for
applications including, but not limited to, notebook PCs and all-in-one PCs.
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
Copyright © 2008 – 2015 Video Electronics Standards Association. All rights reserved.
v1.4b d3
Page 1 of 269
DRAFT
Contents
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Intellectual Property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Support for this Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Section 1
Section 2
Section 3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1
1.2
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.3
1.4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
eDP System Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
eDP System Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.1
2.2
eDP Support by Source and Sink Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3 Multi-SST Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
eDP v1.4b Deviations from DP v1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.1
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
eDP Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2
eDP v1.4b-specific Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3
3.4
eDP AUX Link Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Display Authentication and Content Protection Support . . . . . . . . . . . . . . . . . 51
3.5
3.6
Panel Input Power (LCDVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.7 Main Stream Attribute Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
Copyright © 2008 – 2015 Video Electronics Standards Association. All rights reserved.
v1.4b d3
Page 2 of 269
DRAFT
3.8 Multi-SST Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.8.1 Multi-SST Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.8.2 Multi-SST Operation Source Configuration . . . . . . . . . . . . . . . . . . . . . 58
3.8.3 Multi-SST Operation with Two SST Links, One Lane Each (2x1) . . . 61
3.8.4 Multi-SST Operation with Two SST Links, Two Lanes Each (2x2) . . 62
3.8.5 Multi-SST Operation with Four SST Links, One Lane Each (4x1) . . . 63
3.8.6 Multi-SST Operation with Pixels Overlapping
Adjacent Panel Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.8.7 Multi-SST Operation DPCD Capabilities Register. . . . . . . . . . . . . . . . 66
3.8.8 Multi-SST Operation Timing Requirements
(Dependent Multi-SST Operation Links Only). . . . . . . . . . . . . . . . . . . 67
3.8.9 Sink CRC Registers for Multi-SST Operation . . . . . . . . . . . . . . . . . . . 68
eDP Electrical Specification Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2
Interconnect Reference Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 Main-Link TX TP1 Differential Signal Voltage . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.1 Link Training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.2 Vdiff Training Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Main-Link Electrical Specification Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Link Transfer Rates and Jitter Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.5
4.5.1 Recommended Link Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.5.2 Differential Noise Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5.3 Differential Noise Budget Application . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.6 Main-Link Source Device Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.6.1 TP3_EQ EYE Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.6.2 TP3_EQ Reference Equalizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AUX CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.7.1 AUX CH Electrical Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Link Rate Discovery and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.7
4.8
Advanced Link Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Power Management States of DPRX in a Downstream Device . . . . . . . . . . . . 99
5.1
Power Management Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2
5.2.1 PHY Layer Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.2.2 PHY Layer Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.3.1 Discovery, Enabling, and Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Advanced Link Power Management DPCD Fields. . . . . . . . . . . . . . . . . . . . . 110
5.3
5.4
Section 4
Section 5
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
Copyright © 2008 – 2015 Video Electronics Standards Association. All rights reserved.
v1.4b d3
Page 3 of 269
DRAFT
Section 6
Section 7
Section 8
6.2
Panel Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
PSR Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.1
6.1.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.1.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.1.3 PSR Entry/Exit Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.1.4 Error Management/Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Self Refresh with Selective Update (PSR2) Overview . . . . . . . . . . . . . . . . . . 139
6.2.1 Selective Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.2.2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.2.3 PSR2 States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.2.4 PSR2 Command and Data Transport . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.2.5 Data Integrity Check and Corrective Action. . . . . . . . . . . . . . . . . . . . 145
PSR DPCD Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
PSR SDP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3
6.4
AUX-based Source-to-Sink Device Active
Video Timing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.1
7.2
AUX Frame Sync DPCD Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Compressed Display Stream Transport Services . . . . . . . . . . . . . . . . . . .167
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.2
Configuration – Discovery, Enabling, and Disabling . . . . . . . . . . . . . . . . . . . 169
8.3
Framing and Compressed Stream Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4
8.5
Picture Parameter Set Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
8.5.1 PPS Packet Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
8.5.2 PPS Packet Payload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
PSR in DSC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
8.6.1 PSR SDP in DSC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
8.6.2 PSR2 Selective Update in DSC Configuration . . . . . . . . . . . . . . . . . . 177
DSC DPCD Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
8.6
8.7
Section 9
Multi-Touch over AUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
9.1
Requirements and Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Device Discovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
9.2
Capability Discovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
9.3
9.4
Boot Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Sink Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
9.5
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
Copyright © 2008 – 2015 Video Electronics Standards Association. All rights reserved.
v1.4b d3
Page 4 of 269
DRAFT
Register Layout and Access Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
9.6.1 HID Class Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
9.6.2 HID Report Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
9.6.3 HID Reports Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
9.7.1 Source Device Interrupt-based Data Access to Input
or Feature Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
9.7.2 Source Device Polled Data Access to Input or Feature Report. . . . . . 195
9.7.3 Combination of Source Device Interrupt-based
and Polled Data Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
9.7.4 Sink Device Data Access to Output Report . . . . . . . . . . . . . . . . . . . . 197
9.7.5 Sink Device Data Access to Feature Report . . . . . . . . . . . . . . . . . . . . 199
Report Freshness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Concurrency Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.9.1 Concurrency of Touch with Keyboard . . . . . . . . . . . . . . . . . . . . . . . . 201
9.9.2 Concurrency of Touch with Mouse. . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.9.3 Concurrency of Touch with Keyboard and Mouse . . . . . . . . . . . . . . . 202
9.9.4 Sink Device Limitation Regarding Multiple Keyboard
9.6
9.7
9.8
9.9
or Mouse Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
9.10 DP Touch Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.10.1 HID Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.10.2 Report Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
9.10.3 REPORT_DATA Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.11 Multi-Touch DPCD Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Section 10
eDP Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
10.1 Display Backlight Control Using DPCD Registers. . . . . . . . . . . . . . . . . . . . . 215
10.2
LCD Panel Self-Test (Informative). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.3 Display Control DPCD Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Section 11
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Section 12
eDP Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
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Appendix A Lane Rate/Count vs. Supported Pixel Bandwidth (Informative). . . . . . . .253
Number of Main-Link Lanes vs. Video Mode Support (Informative) . . . . . . 253
A.1
Appendix B Electrical Specification Development. . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
End-to-End Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
TX I/O Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
End-to-End Channel EYE Mask, RX_EQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
RX Reference Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
B.1
B.2
B.3
B.4
Appendix C Usage Guide for Multi-SST Operation with Segmented Panel Display . .261
C.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
C.2 Multi-SST Architecture Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 261
C.3
Panel Self Refresh (PSR2) with Multi-SST Operation . . . . . . . . . . . . . . . . . . 264
Appendix D Features Required for the VESA eDP Notebook Profile
(Policy Requirement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Appendix E Main Contributor History (Previous Versions). . . . . . . . . . . . . . . . . . . . . .266
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
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Tables
Table 1:
Table 2:
Table 3:
Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Main Contributors to eDP v1.4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-1:
Table 1-2:
Table 1-3:
Acronyms and Initialisms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
eDP Features and Requirements that Differ from DP v1.3 . . . . . . . . . . . . . . . . . . 40
Table 3-1:
eDP v1.4b DPCD Address Mapping Deviation from DP v1.3 . . . . . . . . . . . . . . . 46
Table 3-2:
Assignment of DPCD Address 0000Dh Register Bits. . . . . . . . . . . . . . . . . . . . . . 50
Table 3-3:
Optional eDP Display Authentication and Content Protection Methods. . . . . . . . 51
Table 3-4:
Assignment of DPCD Address 0010Ah Register Bits. . . . . . . . . . . . . . . . . . . . . . 52
Table 3-5:
Expanded Description of Figure 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 3-6:
Set of MSA Timing Parameters that Can Be Ignored . . . . . . . . . . . . . . . . . . . . . . 57
Table 3-7:
DPCD Register Bits that Determine Use of Parameters Listed in Table 3-7. . . . . 57
Table 3-8:
Multi-SST Operation Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 3-9:
Table 3-10: Additional DPCD CRC Registers for Multi-SST Operation . . . . . . . . . . . . . . . . . 68
Table 4-1:
Table 4-2:
Table 4-3:
Table 4-4:
Table 4-5:
Table 4-6:
Table 4-7:
Table 4-8:
Table 4-9:
Table 4-10:
Recommended TP1 Differential Signal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . 74
Generic Training Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Low Vdiff Training Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
High Vdiff Training Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Single Vdiff Training Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Single Non-transition VdiffP-P with Variable Transition VdiffP-P Example. . . . . . 77
Stretched eDP Training Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
eDP v1.3-Compatible Training Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Recommended eDP Source Device Main-Link Transmitter (Main TX)
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Recommended eDP Sink Device Main-Link Receiver (Main RX)
System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
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Table 4-11:
Recommended Link Transfer Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 4-12: Differential Noise Budget in UI, Transfer Rate ≤ 5.4Gbps/Lane . . . . . . . . . . . . . 82
Jitter Budget Application of Recommended Link Transfer Rates . . . . . . . . . . . . . 83
Table 4-13:
4.155Gbps/Lane Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 4-14:
Table 4-15:
2.0775Gbps/Lane Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.496Gbps/Lane Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 4-16:
Table 4-17:
1.456Gbps/Lane Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
eDP TP3_EQ EYE Mask Vertices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 4-18:
TP3_EQ Reference Equalizer Poles and Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 4-19:
Table 4-20:
Recommended eDP AUX Channel Electrical Specifications,
Manchester-II Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 4-21: Mask Vertices for AUX CH for Manchester-II Transactions
at Transmitting Device’s Package Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 4-22: Mask Vertices for AUX CH for Manchester-II Transactions at TP3 . . . . . . . . . . 91
Table 4-23:
Link Rate Discovery/Selection Method Interoperability Summary. . . . . . . . . . . . 93
Table 4-24: DPCD – Receiver Extended Link Rate Capabilities Registers . . . . . . . . . . . . . . . 94
Table 4-25:
Receiver Extended Link Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 5-1:
Table 5-2:
Table 5-3:
Table 5-4:
Table 5-5:
Table 5-6:
Table 6-1:
Table 6-2:
Table 6-3:
Table 6-4:
Table 6-5:
Table 6-6:
Table 6-7:
Table 6-8:
Table 6-9:
Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Main-Link Power-Down Signal K-Code Definition . . . . . . . . . . . . . . . . . . . . . . 104
Fast Wake Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DPCD – Receiver ALPM Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . 110
DPCD – Receiver ALPM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 110
Receiver ALPM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Source Device PSR States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Sink Device PSR States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Sink Device Action for Single-frame Update . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Valid Control Bit Setting Combinations in PSR2 SDP . . . . . . . . . . . . . . . . . . . . 144
DPCD – Sink Device PSR Capability Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
DPCD – Sink Device PSR Configuration Field. . . . . . . . . . . . . . . . . . . . . . . . . . 149
DPCD – Sink Device PSR Status Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
VSC SDP Byte Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
VSC SDP Header Extension for PSR Operation – HB0 through HB3 . . . . . . . . 156
VESA Proposed Embedded DisplayPort (eDP) Standard DISTRIBUTION TO NON-MEMBERS IS PROHIBITED
Copyright © 2008 – 2015 Video Electronics Standards Association. All rights reserved.
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