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PCI spec 2.3.pdf
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"/:732
-83,/6
Revision 2.3
REVISION
REVISION HISTORY
Original issue
DATE
6/22/92
1.0
2.0
2.1
2.2
2.3
Incorporated connector and expansion board specification
4/30/93
Incorporated clarifications and added 66 MHz chapter
6/1/95
Incorporated ECNs and improved readability
Incorporated ECNs, errata, and deleted 5 volt only keyed
add-in cards
12/18/98
10/31/01
The PCI Special Interest Group disclaims all warranties and liability for the use of this document
and the information contained herein and assumes no responsibility for any errors that may appear
in this document, nor does the PCI Special Interest Group make a commitment to update the
information contained herein.
Contact the PCI Special Interest Group office to obtain the latest revision of the specification.
Questions regarding the PCI specification or membership in the PCI Special Interest Group may
be forwarded to:
PCI Special Interest Group
5440 SW Westgate Drive
Suite 217
Portland, Oregon 97221
Phone: 800-433-5177 (Inside the U.S.)
503-291-2569 (Outside the U.S.)
503-297-1090
administration@pcisig.com
Fax:
e-mail
http://www.pcisig.com
DISCLAIMER
This PCI Local Bus Specification is provided "as is" with no warranties whatsoever, including any
warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability
for infringement of proprietary rights, relating to use of information in this specification. No
license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted
herein.
ALPHA is a registered trademark of Digital Equipment Corporation.
FireWire is a trademark of Apple Computer, Inc.
Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT are
registered trademarks of IBM Corporation.
Windows, MS-DOS, and Microsoft are registered trademarks of Microsoft Corporation.
Tristate is a registered trademark of National Semiconductor.
NuBus is a trademark of Texas Instruments.
Ethernet is a registered trademark of Xerox Corporation.
All other product names are trademarks, registered trademarks, or service marks of their respective
owners.
Copyright © 1992, 1993, 1995, 1998, 2001 PCI Special Interest Group
Revision 2.3
Contents
Preface
Specification Supersedes Earlier Documents...................................................................xiii
Incorporation of Engineering Change Notices (ECNs)....................................................xiii
Document Conventions.................................................................................................... xiv
Chapter 1 Introduction
1.1. Specification Contents................................................................................................ 1
1.2. Motivation .................................................................................................................. 1
1.3. PCI Local Bus Applications....................................................................................... 2
1.4. PCI Local Bus Overview............................................................................................ 3
1.5. PCI Local Bus Features and Benefits......................................................................... 4
1.6. Administration............................................................................................................ 6
Chapter 2 Signal Definition
2.1. Signal Type Definition............................................................................................... 8
2.2. Pin Functional Groups................................................................................................ 8
2.2.1. System Pins...................................................................................................................... 8
2.2.2. Address and Data Pins..................................................................................................... 9
2.2.3. Interface Control Pins.................................................................................................... 10
2.2.4. Arbitration Pins (Bus Masters Only) ............................................................................. 11
2.2.5. Error Reporting Pins...................................................................................................... 12
2.2.6. Interrupt Pins (Optional)................................................................................................ 13
2.2.7. Additional Signals ......................................................................................................... 15
2.2.8. 64-Bit Bus Extension Pins (Optional) ........................................................................... 17
2.2.9. JTAG/Boundary Scan Pins (Optional) .......................................................................... 18
2.2.10. System Management Bus Interface Pins (Optional)................................................... 19
2.3. Sideband Signals ...................................................................................................... 19
2.4. Central Resource Functions ..................................................................................... 19
Revision 2.3
Chapter 3 Bus Operation
3.1. Bus Commands ........................................................................................................ 21
3.1.1. Command Definition ..................................................................................................... 21
3.1.2. Command Usage Rules.................................................................................................. 23
3.2. PCI Protocol Fundamentals...................................................................................... 26
3.2.1. Basic Transfer Control................................................................................................... 26
3.2.2. Addressing ..................................................................................................................... 27
3.2.2.1. I/O Space Decoding................................................................................................ 28
3.2.2.2. Memory Space Decoding ....................................................................................... 28
3.2.2.3. Configuration Space Decoding............................................................................... 30
3.2.3. Byte Lane and Byte Enable Usage ................................................................................ 38
3.2.4. Bus Driving and Turnaround ......................................................................................... 39
3.2.5. Transaction Ordering and Posting ................................................................................. 40
3.2.5.1. Transaction Ordering and Posting for Simple Devices........................................... 41
3.2.5.2. Transaction Ordering and Posting for Bridges ....................................................... 42
3.2.6. Combining, Merging, and Collapsing............................................................................ 44
3.3. Bus Transactions ...................................................................................................... 46
3.3.1. Read Transaction ........................................................................................................... 47
3.3.2. Write Transaction .......................................................................................................... 48
3.3.3. Transaction Termination................................................................................................ 49
3.3.3.1. Master Initiated Termination .................................................................................. 49
3.3.3.2. Target Initiated Termination................................................................................... 51
3.3.3.3. Delayed Transactions.............................................................................................. 61
3.4. Arbitration ................................................................................................................ 68
3.4.1. Arbitration Signaling Protocol....................................................................................... 70
3.4.2. Fast Back-to-Back Transactions .................................................................................... 72
3.4.3. Arbitration Parking ........................................................................................................ 74
3.5. Latency..................................................................................................................... 75
3.5.1. Target Latency............................................................................................................... 75
3.5.1.1. Target Initial Latency ............................................................................................. 75
3.5.1.2. Target Subsequent Latency..................................................................................... 77
3.5.2. Master Data Latency...................................................................................................... 78
3.5.3. Memory Write Maximum Completion Time Limit....................................................... 78
3.5.4. Arbitration Latency........................................................................................................ 79
3.5.4.1. Bandwidth and Latency Considerations ................................................................. 80
3.5.4.2. Determining Arbitration Latency............................................................................ 82
3.5.4.3. Determining Buffer Requirements.......................................................................... 87
3.6. Other Bus Operations............................................................................................... 88
3.6.1. Device Selection ............................................................................................................ 88
3.6.2. Special Cycle ................................................................................................................. 90
3.6.3. IDSEL Stepping............................................................................................................. 91
3.6.4. Interrupt Acknowledge .................................................................................................. 93
3.7. Error Functions......................................................................................................... 93
:
Revision 2.3
3.7.1. Parity Generation........................................................................................................... 94
3.7.2. Parity Checking ............................................................................................................. 95
3.7.3. Address Parity Errors..................................................................................................... 95
3.7.4. Error Reporting.............................................................................................................. 95
3.7.4.1. Data Parity Error Signaling on PERR# .................................................................. 96
3.7.4.2. Other Error Signaling on SERR# ........................................................................... 97
3.7.4.3. Master Data Parity Error Status Bit ........................................................................ 98
3.7.4.4. Detected Parity Error Status Bit ............................................................................. 98
3.7.5. Delayed Transactions and Data Parity Errors................................................................ 98
3.7.6. Error Recovery............................................................................................................. 100
3.8. 64-Bit Bus Extension ............................................................................................. 101
3.8.1. Determining Bus Width During System Initialization ................................................ 104
3.9. 64-bit Addressing ................................................................................................... 105
3.10. Special Design Considerations............................................................................. 108
Chapter 4 Electical Specification
4.1. Overview ................................................................................................................ 113
4.1.1. Transition Road Map ................................................................................................... 113
4.1.2. Dynamic vs. Static Drive Specification....................................................................... 115
4.2. Component Specification ....................................................................................... 115
4.2.1. 5V Signaling Environment .......................................................................................... 117
4.2.1.1. DC Specifications ................................................................................................. 117
4.2.1.2. AC Specifications ................................................................................................. 118
4.2.1.3. Maximum AC Ratings and Device Protection ..................................................... 120
4.2.2. 3.3V Signaling Environment ....................................................................................... 122
4.2.2.1. DC Specifications ................................................................................................. 122
4.2.2.2. AC Specifications ................................................................................................. 123
4.2.2.3. Maximum AC Ratings and Device Protection ..................................................... 125
4.2.3. Timing Specification ................................................................................................... 126
4.2.3.1. Clock Specification............................................................................................... 126
4.2.3.2. Timing Parameters................................................................................................ 128
4.2.3.3. Measurement and Test Conditions ....................................................................... 129
4.2.4. Indeterminate Inputs and Metastability ....................................................................... 130
4.2.5. Vendor Provided Specification.................................................................................... 131
4.2.6. Pinout Recommendation.............................................................................................. 131
4.3. System Board Specification ................................................................................... 132
4.3.1. Clock Skew.................................................................................................................. 132
4.3.2. Reset ............................................................................................................................ 133
4.3.3. Pull-ups........................................................................................................................ 136
4.3.4. Power ........................................................................................................................... 137
4.3.4.1. Power Requirements............................................................................................. 137
4.3.4.2. Sequencing............................................................................................................ 137
4.3.4.3. Decoupling............................................................................................................ 138
4.3.5. System Timing Budget ................................................................................................ 138
:
Revision 2.3
4.3.6. Physical Requirements................................................................................................. 142
4.3.6.1. Routing and Layout Recommendations for Four-Layer System Boards.............. 142
4.3.6.2. System Board Impedance ..................................................................................... 142
4.3.7. Connector Pin Assignments......................................................................................... 143
4.4. Add-in Card Specification...................................................................................... 147
4.4.1. Add-in Card Pin Assignment....................................................................................... 147
4.4.2. Power Requirements.................................................................................................... 151
4.4.2.1. Decoupling............................................................................................................ 151
4.4.2.2. Power Consumption.............................................................................................. 151
4.4.3. Physical Requirements................................................................................................. 152
4.4.3.1. Trace Length Limits ............................................................................................. 152
4.4.3.2. Routing Recommendations for Four-Layer Add-in Cards ................................... 153
4.4.3.3. Impedance............................................................................................................. 153
4.4.3.4. Signal Loading...................................................................................................... 153
Chapter 5 Mechanical Specification
5.1. Overview ................................................................................................................ 155
5.2. Add-in Card Physical Dimensions and Tolerances................................................ 156
5.3. Connector Physical Description............................................................................. 169
5.4. Connector Physical Requirements ......................................................................... 182
5.5. Connector Performance Specification.................................................................... 183
5.6. System Board Implementation............................................................................... 184
Chapter 6 Configuration Space
6.1. Configuration Space Organization......................................................................... 194
6.2. Configuration Space Functions .............................................................................. 196
6.2.1. Device Identification ................................................................................................... 196
6.2.2. Device Control............................................................................................................. 197
6.2.3. Device Status ............................................................................................................... 200
6.2.4. Miscellaneous Registers .............................................................................................. 202
6.2.5. Base Addresses ............................................................................................................ 205
6.2.5.1. Address Maps ....................................................................................................... 205
6.2.5.2. Expansion ROM Base Address Register .............................................................. 208
6.3. PCI Expansion ROMs ............................................................................................ 209
6.3.1. PCI Expansion ROM Contents .................................................................................... 210
6.3.1.1. PCI Expansion ROM Header Format ................................................................... 211
6.3.1.2. PCI Data Structure Format ................................................................................... 212
6.3.2. Power-on Self Test (POST) Code................................................................................ 213
6.3.3. PC-compatible Expansion ROMs................................................................................ 214
6.3.3.1. ROM Header Extensions ...................................................................................... 214
6.4. Vital Product Data................................................................................................... 216
:
Revision 2.3
6.5. Device Drivers........................................................................................................ 217
6.6. System Reset .......................................................................................................... 217
6.7. Capabilities List...................................................................................................... 218
6.8. Message Signaled Interrupts .................................................................................. 218
6.8.1. Message Capability Structure ....................................................................................... 219
6.8.1.1. Capability ID ........................................................................................................ 220
6.8.1.2. Next Pointer.......................................................................................................... 220
6.8.1.3. Message Control ................................................................................................... 220
6.8.1.4. Message Address .................................................................................................. 222
6.8.1.5. Message Upper Address (Optional)...................................................................... 222
6.8.1.6. Message Data........................................................................................................ 223
6.8.2. MSI Operation .............................................................................................................. 223
6.8.2.1. MSI Transaction Termination............................................................................... 225
6.8.2.2. MSI Transaction Reception and Ordering Requirements..................................... 225
Chapter 7 66 MHz PCI Specification
7.1. Introduction ............................................................................................................ 227
7.2. Scope ...................................................................................................................... 227
7.3. Device Implementation Considerations ................................................................. 228
7.3.1. Configuration Space .................................................................................................... 228
7.4. Agent Architecture ................................................................................................. 228
7.5. Protocol .................................................................................................................. 228
7.5.1. 66MHZ_ENABLE (M66EN) Pin Definition .............................................................. 228
7.5.2. Latency ........................................................................................................................ 229
7.6. Electrical Specification .......................................................................................... 229
7.6.1. Overview ..................................................................................................................... 229
7.6.2. Transition Roadmap to 66 MHz PCI ........................................................................... 230
7.6.3. Signaling Environment ................................................................................................ 230
7.6.3.1. DC Specifications ................................................................................................. 231
7.6.3.2. AC Specifications ................................................................................................. 231
7.6.3.3. Maximum AC Ratings and Device Protection ..................................................... 232
7.6.4. Timing Specification ................................................................................................... 232
7.6.4.1. Clock Specification............................................................................................... 232
7.6.4.2. Timing Parameters................................................................................................ 234
7.6.4.3. Measurement and Test Conditions ....................................................................... 235
7.6.5. Vendor Provided Specification.................................................................................... 237
7.6.6. Recommendations........................................................................................................ 237
7.6.6.1. Pinout Recommendations ..................................................................................... 237
7.6.6.2. Clocking Recommendations................................................................................. 237
7.7. System Board Specification ................................................................................... 238
7.7.1. Clock Uncertainty........................................................................................................ 238
7.7.2. Reset ............................................................................................................................ 239
7.7.3. Pullups ......................................................................................................................... 239
:
Revision 2.3
7.7.4. Power ........................................................................................................................... 239
7.7.4.1. Power Requirements............................................................................................. 239
7.7.4.2. Sequencing............................................................................................................ 239
7.7.4.3. Decoupling............................................................................................................ 239
7.7.5. System Timing Budget ................................................................................................ 239
7.7.6. Physical Requirements................................................................................................. 240
7.7.6.1. Routing and Layout Recommendations for Four-Layer System Boards.............. 240
7.7.6.2. System Board Impedance ..................................................................................... 240
7.7.7. Connector Pin Assignments......................................................................................... 240
7.8. Add-in Card Specifications .................................................................................... 241
Chapter 8 System Support for SMBus
8.1. SMBus System Requirements................................................................................ 243
8.1.1. Power ........................................................................................................................... 243
8.1.2. Physical and Logical SMBus....................................................................................... 244
8.1.3. Bus Connectivity ......................................................................................................... 244
8.1.4 Master and Slave Support............................................................................................. 245
8.1.5 Addressing and Configuration...................................................................................... 245
8.1.6 Electrical ....................................................................................................................... 246
8.1.7 SMBus Behavior on PCI Reset..................................................................................... 246
8.2 Add-in Card SMBus Requirements......................................................................... 246
8.2.1 Connection.................................................................................................................... 246
8.2.2 Master and Slave Support............................................................................................. 247
8.2.3 Addressing and Configuration...................................................................................... 247
8.2.4 Power ............................................................................................................................ 247
8.2.5 Electrical ....................................................................................................................... 247
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