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千兆网芯片RTL8211EG.pdf
1. General Description
2. Features
3. System Applications
3.1. Application Diagram (RTL8211E-VB)
3.2. Application Diagram (RTL8211EG-VB)
3.3. Application Diagram (RTL8211E-VL)
4. Block Diagram
5. Pin Assignments
5.1. RTL8211E-VB/RTL8211E-VL Pin Assignments (48-Pin QFN)
5.2. Package Identification
5.3. RTL8211EG-VB Pin Assignments (64-Pin QFN)
5.4. Package Identification
6. Pin Descriptions
6.1. Transceiver Interface
6.2. Clock
6.3. RGMII
6.4. GMII (RTL8211EG-VB Only)
6.5. Management Interface
6.6. Reset
6.7. Mode Selection
6.8. LED Default Settings
6.9. Regulator and Reference
6.10. Power and Ground
6.11. Not Connected
7. Function Description
7.1. Transmitter
7.1.1. RGMII/GMII (1000Mbps) Mode
7.1.2. MII (100Mbps) Mode
7.1.3. MII (10Mbps) Mode
7.2. Receiver
7.2.1. RGMII/GMII (1000Mbps) Mode
7.2.2. MII (100Mbps) Mode
7.2.3. MII (10Mbps) Mode
7.3. Energy Efficient Ethernet (EEE)
7.4. Wake-On-LAN (WOL)
7.5. Interrupt
7.6. MDI Interface
7.7. Hardware Configuration
7.8. LED and PHY Address Configuration
7.9. Green Ethernet (1000/100Mbps Mode Only)
7.9.1. Cable Length Power Saving
7.9.2. Register Setting
7.10. MAC/PHY Interface
7.10.1. MII
7.10.2. GMII
7.10.3. RGMII
7.10.4. Management Interface
7.10.5. Access to Extension Page (ExtPage)
7.10.6. Access to MDIO Manageable Device (MMD)
7.11. Auto-Negotiation
7.11.1. Auto-Negotiation Priority Resolution
7.11.2. Auto-Negotiation Master/Slave Resolution
7.11.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution
7.12. Crossover Detection and Auto-Correction
7.13. LED Configuration
7.14. Polarity Correction
7.15. Power
7.16. PHY Reset (Hardware Reset)
8. Register Descriptions
8.1. Register Mapping and Definitions
8.2. MMD Register Mapping and Definition
8.3. ExtPage Register Mapping and Definition
8.4. Register Table
8.4.1. BMCR (Basic Mode Control Register, Address 0x00)
8.4.2. BMSR (Basic Mode Status Register, Address 0x01)
8.4.3. PHYID1 (PHY Identifier Register 1, Address 0x02)
8.4.4. PHYID2 (PHY Identifier Register 2, Address 0x03)
8.4.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04)
8.4.6. ANLPAR (Auto-Negotiation Link Partner Ability Register,Address 0x05)
8.4.7. ANER (Auto-Negotiation Expansion Register, Address 0x06)
8.4.8. ANNPTR (Auto-Negotiation Next Page Transmit Register,Address 0x07)
8.4.9. ANNPRR (Auto-Negotiation Next Page Receive Register,Address 0x08)
8.4.10. GBCR (1000Base-T Control Register, Address 0x09)
8.4.11. GBSR (1000Base-T Status Register, Address 0x0A)
8.4.12. MACR (MMD Access Control Register, Address 0x0D)
8.4.13. MAADR (MMD Access Address Data Register, Address 0x0E)
8.4.14. GBESR (1000Base-T Extended Status Register, Address 0x0F)
8.4.15. PHYCR (PHY Specific Control Register, Address 0x10)
8.4.16. PHYSR (PHY Specific Status Register, Address 0x11)
8.4.17. INER (Interrupt Enable Register, Address 0x12)
8.4.18. INSR (Interrupt Status Register, Address 0x13)
8.4.19. RXERC (Receive Error Counter, Address 0x18)
8.4.20. LDPSR (Link Down Power Saving Register, Address 0x1B)
8.4.21. EPAGSR (Extension Page Select Register, Address 0x1E)
8.4.22. PAGSEL (Page Select Register, Address 0x1F)
8.4.23. PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00)
8.4.24. PS1R (PCS Status1 Register, MMD Device 3, Address 0x01)
8.4.25. EEECR (EEE Capability Register, MMD Device 3, Address 0x14)
8.4.26. EEEWER (EEE Wake Error Register, MMD Device 3,Address 0x16)
8.4.27. EEEAR (EEE Advertisement Register, MMD Device 7,Address 0x3c)
8.4.28. EEELPAR (EEE Link Partner Ability Register, MMD Device 7,Address 0x3d)
8.4.29. LACR (LED Action Control Register, ExtPage 0x2c, Address 0x1a)
8.4.30. LCR (LED Control Register, ExtPage 0x2c, Address 0x1c)
8.4.31. ACCR (Auto-Crossover Control Register, ExtPage 0x2d,Address 0x18)
9. Switching Regulator
9.1. PCB Layout
9.2. Inductor and Capacitor Parts List
9.3. Measurement Criteria
9.4. Efficiency Measurement
9.5. Power Sequence
10. Characteristics
10.1. Absolute Maximum Ratings
10.2. Recommended Operating Conditions
10.3. Crystal Requirements
10.4. Oscillator/External Clock Requirements
10.5. DC Characteristics
10.6. AC Characteristics
10.6.1. MDC/MDIO Timing
10.6.2. MII Transmission Cycle Timing (RTL8211EG-VB Only)
10.6.3. MII Reception Cycle Timing (RTL8211EG-VB Only)
10.6.4. GMII Timing Modes (RTL8211EG-VB Only)
10.6.5. RGMII Timing Modes
11. Mechanical Dimensions
11.1. RTL8211E-VB/RTL8211E-VL Mechanical Dimensions (48-Pin QFN)
11.2. Mechanical Dimensions Notes (RTL8211E-VB/RTL8211E-VL)
11.3. RTL8211EG-VB Mechanical Dimensions (64-Pin QFN)
11.4. Mechanical Dimensions Notes (RTL8211EG-VB)
12. Ordering Information
RTL8211E-VB-CG
RTL8211E-VL-CG
RTL8211EG-VB-CG
INTEGRATED 10/100/1000M ETHERNET
TRANSCEIVER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.6
03 April 2012
Track ID: JATR-3375-16
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8211E/RTL8211EG
Datasheet
COPYRIGHT
©2012 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094,
US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
1.1
1.2
1.3
Release Date
2009/08/31
2010/08/13
2010/08/16
2010/12/17
Summary
First release.
Added RTL8211EG-CG product data.
Corrected minor typing errors.
Added RTL8211E-VL-CG model number.
Revised Table 23 BMCR (Basic Mode Control Register, Address 0x00), page 31.
Revised Table 32 GBCR (1000Base-T Control Register, Address 0x09), page 37.
Revised Table 40 INSR (Interrupt Status Register, Address 0x13), page 42.
Revised Table 55 Power Sequence parameter, page 55.
Revised Table 61 MDC/MDIO Management Timing Parameters, page 59.
Added section 10.6.2 MII Transmission Cycle Timing, page 60.
Added section 10.6.3 MII Reception Cycle Timing (RTL8211EG-VB Only), page 60.
Revised Table 64 GMII Timing Parameters, page 62.
Revised ordering numbers (see Table 66 Ordering Information, page 70).
Integrated 10/100/1000M Ethernet Transceiver
ii
Track ID: JATR-3375-16 Rev. 1.6
RTL8211E/RTL8211EG
Datasheet
Summary
Revised section 2 Features, page 2.
Revised section 3 System Applications, page 3.
Added section 4 Block Diagram, page 5.
Revised Table 6 Reset, page 11.
Revised Table 10 Power and Ground, page 12.
Added section 7.5 Interrupt, page 15.
Revised section 7.7 Hardware Configuration, page 16.
Revised Figure 7 LED and PHY Address Configuration, page 17.
Revised section 7.9.2 Register Setting, page 18.
Revised section 7.10.4 Management Interface, page 19.
Revised section 7.10.5 Access to Extension Page (ExtPage), page 21.
Added section 7.16 PHY Reset (Hardware Reset), page 29.
Revised Table 23 BMCR (Basic Mode Control Register, Address 0x00), page 31.
Revised Table 37 PHYCR (PHY Specific Control Register, Address 0x10), page 39.
Revised Table 56 Absolute Maximum Ratings, page 56.
Revised Table 57 Recommended Operating Conditions, page 56.
Revised Table 60 DC Characteristics, page 58.
Revised section 10.6.1 MDC/MDIO Timing, page 59.
Revised section 10.6.2 MII Transmission Cycle Timing (RTL8211EG-VB Only), page 60.
Revised Table 66 Ordering Information, page 70.
Revised section 4 Block Diagram, page 5.
Revised Table 35 MAADR (MMD Access Address Data Register, Address 0x0E), page
39.
Revised Table 39 INER (Interrupt Enable Register, Address 0x12), page 41.
Revised Table 55 Power Sequence parameter, page 55.
Revised Table 60 DC Characteristics, page 58.
Revised Table 62 MII Transmission Cycle Timing, page 60.
Revised Table 63 MII Reception Cycle Timing, page 61.
Revised section 10.6.5 RGMII Timing Modes, page 63.
Revised Table 20 Register Mapping and Definitions, page 30.
Added Table 22 ExtPage Register Mapping and Definition, page 31.
Added Table 42 LDPSR (Link Down Power Saving Register, Address 0x1B), page 42.
Added Table 43 EPAGSR (Extension Page Select Register, Address 0x1E), page 42.
Added Table 51 LACR (LED Action Control Register, ExtPage 0x2c, Address 0x1a),
page 45.
Added Table 52 LCR (LED Control Register, ExtPage 0x2c, Address 0x1c), page 45.
Added Table 53 ACCR (Auto-Crossover Control Register, ExtPage 0x2d, Address
0x18)45, page 45.
Revised section 11.4 Mechanical Dimensions Notes (RTL8211EG-VB), page 69.
Revision
1.4
Release Date
2011/05/17
1.5
2011/10/28
1.6
2012/04/03
Integrated 10/100/1000M Ethernet Transceiver
iii
Track ID: JATR-3375-16 Rev. 1.6
RTL8211E/RTL8211EG
Datasheet
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
2.
3.
4.
5.
6.
7.
FEATURES.........................................................................................................................................................................2
3.1.
3.2.
3.3.
SYSTEM APPLICATIONS...............................................................................................................................................3
APPLICATION DIAGRAM (RTL8211E-VB)...................................................................................................................3
APPLICATION DIAGRAM (RTL8211EG-VB)................................................................................................................4
APPLICATION DIAGRAM (RTL8211E-VL)...................................................................................................................4
BLOCK DIAGRAM...........................................................................................................................................................5
5.1.
5.2.
5.3.
5.4.
PIN ASSIGNMENTS .........................................................................................................................................................6
RTL8211E-VB/RTL8211E-VL PIN ASSIGNMENTS (48-PIN QFN).............................................................................6
PACKAGE IDENTIFICATION...........................................................................................................................................6
RTL8211EG-VB PIN ASSIGNMENTS (64-PIN QFN)....................................................................................................7
PACKAGE IDENTIFICATION...........................................................................................................................................7
PIN DESCRIPTIONS ........................................................................................................................................................8
TRANSCEIVER INTERFACE............................................................................................................................................8
6.1.
CLOCK .........................................................................................................................................................................8
6.2.
RGMII.........................................................................................................................................................................9
6.3.
GMII (RTL8211EG-VB ONLY) ..................................................................................................................................9
6.4.
MANAGEMENT INTERFACE.........................................................................................................................................10
6.5.
RESET ........................................................................................................................................................................11
6.6.
MODE SELECTION ......................................................................................................................................................11
6.7.
LED DEFAULT SETTINGS...........................................................................................................................................11
6.8.
6.9.
REGULATOR AND REFERENCE....................................................................................................................................12
POWER AND GROUND ................................................................................................................................................12
6.10.
6.11. NOT CONNECTED.......................................................................................................................................................12
FUNCTION DESCRIPTION ..........................................................................................................................................13
TRANSMITTER............................................................................................................................................................13
7.1.1. RGMII/GMII (1000Mbps) Mode ..........................................................................................................................13
7.1.2. MII (100Mbps) Mode ...........................................................................................................................................13
7.1.3. MII (10Mbps) Mode .............................................................................................................................................13
RECEIVER...................................................................................................................................................................13
7.2.1. RGMII/GMII (1000Mbps) Mode ..........................................................................................................................13
7.2.2. MII (100Mbps) Mode ...........................................................................................................................................13
7.2.3. MII (10Mbps) Mode .............................................................................................................................................14
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................14
7.3.
7.4. WAKE-ON-LAN (WOL)............................................................................................................................................14
7.5.
INTERRUPT.................................................................................................................................................................15
7.6.
MDI INTERFACE ........................................................................................................................................................15
HARDWARE CONFIGURATION ....................................................................................................................................16
7.7.
LED AND PHY ADDRESS CONFIGURATION ...............................................................................................................17
7.8.
7.9.
GREEN ETHERNET (1000/100MBPS MODE ONLY) .....................................................................................................18
7.9.1. Cable Length Power Saving.................................................................................................................................18
7.9.2. Register Setting.....................................................................................................................................................18
7.10. MAC/PHY INTERFACE..............................................................................................................................................19
7.10.1.
MII ...................................................................................................................................................................19
7.1.
7.2.
Integrated 10/100/1000M Ethernet Transceiver
iv
Track ID: JATR-3375-16 Rev. 1.6
8.1.
8.2.
8.3.
8.4.
7.10.2.
7.10.3.
7.10.4.
7.10.5.
7.10.6.
7.11.1.
7.11.2.
7.11.3.
RTL8211E/RTL8211EG
Datasheet
GMII ................................................................................................................................................................19
RGMII..............................................................................................................................................................19
Management Interface.....................................................................................................................................19
Access to Extension Page (ExtPage) ...............................................................................................................21
Access to MDIO Manageable Device (MMD).................................................................................................21
7.11. AUTO-NEGOTIATION..................................................................................................................................................22
Auto-Negotiation Priority Resolution..............................................................................................................24
Auto-Negotiation Master/Slave Resolution .....................................................................................................25
Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution........................................................................25
7.12. CROSSOVER DETECTION AND AUTO-CORRECTION ....................................................................................................26
LED CONFIGURATION................................................................................................................................................27
7.13.
7.14.
POLARITY CORRECTION.............................................................................................................................................28
7.15.
POWER .......................................................................................................................................................................29
PHY RESET (HARDWARE RESET) ..............................................................................................................................29
7.16.
8. REGISTER DESCRIPTIONS.........................................................................................................................................30
REGISTER MAPPING AND DEFINITIONS.......................................................................................................................30
MMD REGISTER MAPPING AND DEFINITION..............................................................................................................31
EXTPAGE REGISTER MAPPING AND DEFINITION ........................................................................................................31
REGISTER TABLE .......................................................................................................................................................31
8.4.1. BMCR (Basic Mode Control Register, Address 0x00) .........................................................................................31
8.4.2. BMSR (Basic Mode Status Register, Address 0x01).............................................................................................33
8.4.3. PHYID1 (PHY Identifier Register 1, Address 0x02) ............................................................................................34
8.4.4. PHYID2 (PHY Identifier Register 2, Address 0x03) ............................................................................................34
8.4.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04) ...........................................................................34
8.4.6. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) .........................................................35
8.4.7. ANER (Auto-Negotiation Expansion Register, Address 0x06).............................................................................36
8.4.8. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07) .........................................................36
8.4.9. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)...........................................................37
8.4.10.
GBCR (1000Base-T Control Register, Address 0x09).....................................................................................37
GBSR (1000Base-T Status Register, Address 0x0A) .......................................................................................38
8.4.11.
MACR (MMD Access Control Register, Address 0x0D) .................................................................................38
8.4.12.
8.4.13.
MAADR (MMD Access Address Data Register, Address 0x0E)......................................................................39
8.4.14.
GBESR (1000Base-T Extended Status Register, Address 0x0F) .....................................................................39
8.4.15.
PHYCR (PHY Specific Control Register, Address 0x10).................................................................................39
PHYSR (PHY Specific Status Register, Address 0x11)....................................................................................40
8.4.16.
8.4.17.
INER (Interrupt Enable Register, Address 0x12) ............................................................................................41
8.4.18.
INSR (Interrupt Status Register, Address 0x13) ..............................................................................................42
8.4.19.
RXERC (Receive Error Counter, Address 0x18).............................................................................................42
LDPSR (Link Down Power Saving Register, Address 0x1B) ..........................................................................42
8.4.20.
EPAGSR (Extension Page Select Register, Address 0x1E) .............................................................................42
8.4.21.
8.4.22.
PAGSEL (Page Select Register, Address 0x1F) ..............................................................................................43
8.4.23.
PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) ....................................................................43
PS1R (PCS Status1 Register, MMD Device 3, Address 0x01) ........................................................................43
8.4.24.
EEECR (EEE Capability Register, MMD Device 3, Address 0x14)................................................................44
8.4.25.
8.4.26.
EEEWER (EEE Wake Error Register, MMD Device 3, Address 0x16) ..........................................................44
8.4.27.
EEEAR (EEE Advertisement Register, MMD Device 7, Address 0x3c) ..........................................................44
8.4.28.
EEELPAR (EEE Link Partner Ability Register, MMD Device 7, Address 0x3d)............................................44
LACR (LED Action Control Register, ExtPage 0x2c, Address 0x1a)..............................................................45
8.4.29.
8.4.30.
LCR (LED Control Register, ExtPage 0x2c, Address 0x1c)............................................................................45
8.4.31.
ACCR (Auto-Crossover Control Register, ExtPage 0x2d, Address 0x18).......................................................45
SWITCHING REGULATOR..........................................................................................................................................46
PCB LAYOUT.............................................................................................................................................................46
9.
9.1.
Integrated 10/100/1000M Ethernet Transceiver
v
Track ID: JATR-3375-16 Rev. 1.6
9.2.
9.3.
9.4.
9.5.
RTL8211E/RTL8211EG
Datasheet
INDUCTOR AND CAPACITOR PARTS LIST....................................................................................................................47
MEASUREMENT CRITERIA..........................................................................................................................................48
EFFICIENCY MEASUREMENT ......................................................................................................................................54
POWER SEQUENCE .....................................................................................................................................................55
CHARACTERISTICS.................................................................................................................................................56
10.1. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................56
10.2. RECOMMENDED OPERATING CONDITIONS .................................................................................................................56
10.3. CRYSTAL REQUIREMENTS..........................................................................................................................................57
10.4. OSCILLATOR/EXTERNAL CLOCK REQUIREMENTS ......................................................................................................57
10.5. DC CHARACTERISTICS...............................................................................................................................................58
10.6. AC CHARACTERISTICS...............................................................................................................................................59
MDC/MDIO Timing ........................................................................................................................................59
MII Transmission Cycle Timing (RTL8211EG-VB Only)................................................................................60
MII Reception Cycle Timing (RTL8211EG-VB Only) .....................................................................................61
GMII Timing Modes (RTL8211EG-VB Only)..................................................................................................62
RGMII Timing Modes......................................................................................................................................63
MECHANICAL DIMENSIONS.................................................................................................................................66
11.1. RTL8211E-VB/RTL8211E-VL MECHANICAL DIMENSIONS (48-PIN QFN)..............................................................66
11.2. MECHANICAL DIMENSIONS NOTES (RTL8211E-VB/RTL8211E-VL) ......................................................................67
11.3. RTL8211EG-VB MECHANICAL DIMENSIONS (64-PIN QFN) ....................................................................................68
11.4. MECHANICAL DIMENSIONS NOTES (RTL8211EG-VB) .............................................................................................69
ORDERING INFORMATION...................................................................................................................................70
10.6.1.
10.6.2.
10.6.3.
10.6.4.
10.6.5.
10.
11.
12.
Integrated 10/100/1000M Ethernet Transceiver
vi
Track ID: JATR-3375-16 Rev. 1.6
RTL8211E/RTL8211EG
Datasheet
List of Tables
TABLE 1. TRANSCEIVER INTERFACE..............................................................................................................................................8
TABLE 2. CLOCK............................................................................................................................................................................8
TABLE 3. RGMII ...........................................................................................................................................................................9
TABLE 4. GMII (RTL8211EG-VB ONLY) ....................................................................................................................................9
TABLE 5. MANAGEMENT INTERFACE...........................................................................................................................................10
TABLE 6. RESET...........................................................................................................................................................................11
TABLE 7. MODE SELECTION ........................................................................................................................................................11
TABLE 8. LED DEFAULT SETTINGS .............................................................................................................................................11
TABLE 9. REGULATOR AND REFERENCE......................................................................................................................................12
TABLE 10. POWER AND GROUND ..................................................................................................................................................12
TABLE 11. NOT CONNECTED.........................................................................................................................................................12
TABLE 12. CONFIG PINS VS. CONFIGURATION REGISTER............................................................................................................16
TABLE 13. CONFIGURATION REGISTER DEFINITION ......................................................................................................................16
TABLE 14. MANAGEMENT FRAME FORMAT ..................................................................................................................................20
TABLE 15. MANAGEMENT FRAME DESCRIPTION...........................................................................................................................20
TABLE 16. 1000BASE-T BASE AND NEXT PAGE BIT ASSIGNMENTS..............................................................................................22
TABLE 17. LED DEFAULT DEFINITIONS........................................................................................................................................27
TABLE 18. LED REGISTER TABLE.................................................................................................................................................27
TABLE 19. LED CONFIGURATION TABLE......................................................................................................................................28
TABLE 20. REGISTER MAPPING AND DEFINITIONS ........................................................................................................................30
TABLE 21. MMD REGISTER MAPPING AND DEFINITION ...............................................................................................................31
TABLE 22. EXTPAGE REGISTER MAPPING AND DEFINITION..........................................................................................................31
TABLE 23. BMCR (BASIC MODE CONTROL REGISTER, ADDRESS 0X00) ......................................................................................31
TABLE 24. BMSR (BASIC MODE STATUS REGISTER, ADDRESS 0X01)..........................................................................................33
TABLE 25. PHYID1 (PHY IDENTIFIER REGISTER 1, ADDRESS 0X02) ...........................................................................................34
TABLE 26. PHYID2 (PHY IDENTIFIER REGISTER 2, ADDRESS 0X03) ...........................................................................................34
TABLE 27. ANAR (AUTO-NEGOTIATION ADVERTISING REGISTER, ADDRESS 0X04)....................................................................34
TABLE 28. ANLPAR (AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER, ADDRESS 0X05) ...............................................35
TABLE 29. ANER (AUTO-NEGOTIATION EXPANSION REGISTER, ADDRESS 0X06)........................................................................36
TABLE 30. ANNPTR (AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER, ADDRESS 0X07).................................................36
TABLE 31. ANNPRR (AUTO-NEGOTIATION NEXT PAGE RECEIVE REGISTER, ADDRESS 0X08) ...................................................37
TABLE 32. GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) .......................................................................................37
TABLE 33. GBSR (1000BASE-T STATUS REGISTER, ADDRESS 0X0A)..........................................................................................38
TABLE 34. MACR (MMD ACCESS CONTROL REGISTER, ADDRESS 0X0D) ..................................................................................38
TABLE 35. MAADR (MMD ACCESS ADDRESS DATA REGISTER, ADDRESS 0X0E) ......................................................................39
TABLE 36. GBESR (1000BASE-T EXTENDED STATUS REGISTER, ADDRESS 0X0F)......................................................................39
TABLE 37. PHYCR (PHY SPECIFIC CONTROL REGISTER, ADDRESS 0X10) ..................................................................................39
TABLE 38. PHYSR (PHY SPECIFIC STATUS REGISTER, ADDRESS 0X11)......................................................................................40
TABLE 39. INER (INTERRUPT ENABLE REGISTER, ADDRESS 0X12)..............................................................................................41
TABLE 40. INSR (INTERRUPT STATUS REGISTER, ADDRESS 0X13)...............................................................................................42
TABLE 41. RXERC (RECEIVE ERROR COUNTER, ADDRESS 0X18)................................................................................................42
TABLE 42. LDPSR (LINK DOWN POWER SAVING REGISTER, ADDRESS 0X1B).............................................................................42
TABLE 43. EPAGSR (EXTENSION PAGE SELECT REGISTER, ADDRESS 0X1E) ..............................................................................42
TABLE 44. PAGSEL (PAGE SELECT REGISTER, ADDRESS 0X1F)..................................................................................................43
TABLE 45. PC1R (PCS CONTROL 1 REGISTER, MMD DEVICE 3, ADDRESS 0X00)........................................................................43
TABLE 46. PS1R (PCS STATUS 1 REGISTER, MMD DEVICE 3, ADDRESS 0X01)...........................................................................43
TABLE 47. EEECR (EEE CAPABILITY REGISTER, MMD DEVICE 3, ADDRESS 0X14) ...................................................................44
TABLE 48. EEEWER (EEE WAKE ERROR REGISTER, MMD DEVICE 3, ADDRESS 0X16).............................................................44
TABLE 49. EEEAR (EEE ADVERTISEMENT REGISTER, MMD DEVICE 7, ADDRESS 0X3C)...........................................................44
TABLE 50. EEELPAR (EEE LINK PARTNER ABILITY REGISTER, MMD DEVICE 7, ADDRESS 0X3D)............................................44
TABLE 51. LACR (LED ACTION CONTROL REGISTER, EXTPAGE 0X2C, ADDRESS 0X1A) ............................................................45
Integrated 10/100/1000M Ethernet Transceiver
vii
Track ID: JATR-3375-16 Rev. 1.6
RTL8211E/RTL8211EG
Datasheet
TABLE 52. LCR (LED CONTROL REGISTER, EXTPAGE 0X2C, ADDRESS 0X1C) ............................................................................45
TABLE 53. ACCR (AUTO-CROSSOVER CONTROL REGISTER, EXTPAGE 0X2D, ADDRESS 0X18) ...................................................45
TABLE 54. INDUCTOR AND CAPACITOR PARTS LIST......................................................................................................................47
TABLE 55. POWER SEQUENCE PARAMETER ...................................................................................................................................55
TABLE 56. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................56
TABLE 57. RECOMMENDED OPERATING CONDITIONS ...................................................................................................................56
TABLE 58. CRYSTAL REQUIREMENTS............................................................................................................................................57
TABLE 59. OSCILLATOR/EXTERNAL CLOCK REQUIREMENTS........................................................................................................57
TABLE 60. DC CHARACTERISTICS.................................................................................................................................................58
TABLE 61. MDC/MDIO MANAGEMENT TIMING PARAMETERS ....................................................................................................59
TABLE 62. MII TRANSMISSION CYCLE TIMING .............................................................................................................................60
TABLE 63. MII RECEPTION CYCLE TIMING ...................................................................................................................................61
TABLE 64. GMII TIMING PARAMETERS ........................................................................................................................................62
TABLE 65. RGMII TIMING PARAMETERS......................................................................................................................................65
TABLE 66. ORDERING INFORMATION ............................................................................................................................................70
Integrated 10/100/1000M Ethernet Transceiver
viii
Track ID: JATR-3375-16 Rev. 1.6
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