dac7724DA转换器.pdf

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® DAC7724 DAC7725 DAC7724 DAC7725 For most current data sheet and other product information, visit www.burr-brown.com 12-Bit Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES l LOW POWER: 250mW max l SINGLE SUPPLY OUTPUT RANGE: +10V l DUAL SUPPLY OUTPUT RANGE: – 10V l SETTLING TIME: 10m s to 0.012% l 12-BIT LINEARITY AND MONOTONICITY: –40 C to +85 C l RESET TO MID-SCALE (DAC7724) OR ZERO-SCALE (DAC7725) l DATA READBACK l DOUBLE-BUFFERED DATA INPUTS APPLICATIONS l PROCESS CONTROL l CLOSED-LOOP SERVO-CONTROL l MOTOR CONTROL l DATA ACQUISITION SYSTEMS DESCRIPTION The DAC7724 and DAC7725 are 12-bit quad voltage output digital-to-analog converters with guaranteed 12-bit monotonic performance over the specified tem- perature range. They accept 12-bit parallel input data, have double-buffered DAC input logic (allowing simul- taneous update of all DACs), and provide a readback mode of the internal input registers. An asynchronous reset clears all registers to a mid-scale code of 800H (DAC7724) or to a zero-scale of 000H (DAC7725). The DAC7724 and DAC7725 can operate from a single +15V supply, or from +15V and –15V supplies. Low power and small size per DAC make the DAC7724 and DAC7725 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7724 and DAC7725 are available in a PLCC-28 or a SO-28 package, and offer guaranteed specifications over the –40 C to +85 C temperature range. GND VDD VCC VREFH DB0-DB11 12 I/O Buffer Input Register A DAC Register A DAC A VOUTA Input Register B DAC Register B DAC B VOUTB A0 A1 R/W CS Control Logic Input Register C DAC Register C DAC C VOUTC Input Register D DAC Register D DAC D VOUTD International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 RESET LDAC VREFL VSS © 1999 Burr-Brown Corporation PDS-1517B Printed in U.S.A. April, 2000 SBAS112

SPECIFICATION (DUAL SUPPLY) At TA = –40 C to +85 C, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, VREFL = –10V, unless otherwise noted. PARAMETER ACCURACY Linearity Error Linearity Matching(2) Differential Linearity Error Monotonicity Zero-Scale Error Zero-Scale Drift Zero-Scale Matching(2) Full-Scale Error Full-Scale Matching(2) Power Supply Sensitivity ANALOG OUTPUT Voltage Output(3) Output Current Load Capacitance Short-Circuit Current Short-Circuit Duration REFERENCE INPUT VREFH Input Range VREFL Input Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format POWER SUPPLY REQUIREMENTS VDD VCC VSS IDD ICC ISS Power Dissipation TEMPERATURE RANGE Specified Performance DAC7724N, U DAC7725N, U DAC7724NB, UB DAC7725NB, UB CONDITIONS MIN TYP MAX MIN TYP MAX UNITS TMIN to TMAX Code = 000H Code = FFFH At Full Scale 12 1 10 – 2 – 2 – 1 – 2 – 2 – 2 – 2 VREFL – 5 VREFH No Oscillation To VSS, VCC, or GND 500 – 20 Indefinite To – 0.012%, 20V Output Step Full-Scale Step f = 10kHz IIH £ – 10m A IIL £ – 10m A IOH = –0.8mA IOL = 1.6mA VREFL +1.25 –10 –0.5 –3.5 +10 VREFH – 1.25 3.0 0 10 8 0.25 2 65 TTL-Compatible CMOS 2.4 –0.3 3.6 0.0 +4.75 +14.25 –14.25 –8 –40 Straight Binary 50 6 –6 180 VDD +0.3 0.8 VDD 0.4 +5.25 +15.75 –15.75 8.5 250 +85 – 1 – 1 – 1 [ – 1 [ – 1 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ LSB(1) LSB LSB Bits LSB ppm/ C LSB LSB LSB ppm/V V mA pF mA V V mA mA m s LSB nV-s nV/ Hz V V V V V V V m A mA mA mW C [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ NOTES: (1) LSB means Least Significant Bit, when VREFH equals +10V and VREFL equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within the specified error band. (3) Ideal output voltage, does not take into account zero or full-scale error. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7724, 7725 2

SPECIFICATION (SINGLE SUPPLY) At TA = –40 C to +85 C, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, VREFL = 0V, unless otherwise noted. PARAMETER ACCURACY Linearity Error(1) Linearity Matching(3) Differential Linearity Error Monotonicity Zero-Scale Error Zero-Scale Drift Zero-Scale Matching(3) Full-Scale Error Full-Scale Matching(3) Power Supply Sensitivity ANALOG OUTPUT Voltage Output(4) Output Current Load Capacitance Short-Circuit Current Short-Circuit Duration REFERENCE INPUT VREFH Input Range VREFL Input Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time(5) Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format POWER SUPPLY REQUIREMENTS VDD VCC IDD ICC Power Dissipation TEMPERATURE RANGE Specified Performance DAC7724N, U DAC7725N, U DAC7724NB, UB DAC7725NB, UB CONDITIONS MIN TYP MAX MIN TYP MAX UNITS TMIN to TMAX Code = 004H Code = FFFH At Full Scale No Oscillation To VCC or GND To – 0.012%, 10V Output Step f = 10kHz IIH £ – 10m A IIL £ – 10m A IOH = –0.8mA IOL = 1.6mA – 2 – 2 – 1 – 4 – 4 – 4 – 4 12 2 20 VREFL – 5 VREFH 500 – 20 Indefinite VREFL +1.25 0 –0.3 –2.0 +10 VREFH – 1.25 1.5 0 10 8 0.25 2 65 TTL-Compatible CMOS VDD +0.3 0.8 VDD 0.4 +5.25 15.75 2.4 –0.3 3.6 0.0 +4.75 14.25 Straight Binary 50 3.0 45 –40 +85 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ – 1 – 1 – 1 [ – 2 [ – 2 [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [ LSB(2) LSB LSB Bits LSB ppm/ C LSB LSB LSB ppm /V V mA pF mA V V mA mA m s LSB nV-s nV/ Hz V V V V V V m A mA mW C [ [ [ [ [ [ [ [ [ [ [ [ NOTES: (1) If VSS = 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit, when VREFH equals +10V and VREFL equals 0V, then one LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error. (5) Full-scale positive 10V step and negative step from code FFFH to 004H. 3 DAC7724, 7725 ®

ABSOLUTE MAXIMUM RATINGS(1) VCC to VSS ........................................................................... –0.3V to +32V VCC to GND ......................................................................... –0.3V to +16V VSS to GND ......................................................................... +0.3V to –16V VDD to GND ............................................................................. –0.3V to 6V VREFH to GND ....................................................................... –9V to +11V VREFL to GND (VSS = –15V) ................................................. –11V to +9V VREFL to GND (VSS = 0V) .................................................... –0.3V to +9V VREFH to VREFL ....................................................................... –1V to +22V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150 C Operating Temperature Range ........................................ –40 C to +85 C Storage Temperature Range ......................................... –65 C to +150 C Lead Temperature (soldering, 10s) ............................................... +300 C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION MAXIMUM LINEARITY MAXIMUM DIFFERENTIAL ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NONLINEARITY ERROR (LSB) PACKAGE PACKAGE DRAWING NUMBER SPECIFICATION TEMPERATURE RANGE – 1 " – 1 " – 1 " – 1 " – 1 " – 1 " – 1 " – 1 " PLCC-28 " PLCC-28 " SO-28 " SO-28 " PLCC-28 " PLCC-28 " SO-28 " SO-28 " 251 " 251 " 217 " 217 " 251 " 251 " 217 " 217 " –40 C to +85 C –40 C to +85 C " " " " " " " " –40 C to +85 C –40 C to +85 C –40 C to +85 C –40 C to +85 C –40 C to +85 C –40 C to +85 C PRODUCT DAC7724N " DAC7724NB " DAC7724U " DAC7724UB " DAC7725N " DAC7725NB " DAC7725U " DAC7725UB " ERROR (LSB) – 2 " – 1 " – 2 " – 1 " – 2 " – 1 " – 2 " – 1 " ORDERING NUMBER(1) DAC7724N DAC7724N/750 DAC7724NB TRANSPORT MEDIA Rails Tape and Reel Rails DAC7724NB/750 Tape and Reel DAC7724U DAC7724U/1K DAC7724UB Rails Tape and Reel Rails DAC7724UB/1K Tape and Reel DAC7725N DAC7725N/750 DAC7725NB Rails Tape and Reel Rails DAC7725NB/750 Tape and Reel DAC7725U DAC7725U/1K DAC7725UB Rails Tape and Reel Rails DAC7725UB/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /750 indicates 750 devices per reel). Ordering 750 pieces of “DAC7724/750” will get a single 750-piece Tape and Reel. ESD PROTECTION CIRCUITS VCC VSS VDD VOUT 1 of 4 VCC VSS VDD GND RefH RefL Typ of Each Logic Input Pin Typ of Each I/O Pin ® DAC7724, 7725 4

PIN CONFIGURATIONS Top View SO VREFH VOUTB VOUTA VSS GND RESET LDAC (LSB) DB0 DB1 1 2 3 4 5 6 7 8 9 DB2 10 DB3 11 DB4 12 DB5 13 DB6 14 DAC7724 DAC7725 28 27 26 25 24 VREFL VOUTC VOUTD VCC VDD 23 CS 22 A0 21 A1 20 R/W 19 DB11 (MSB) 18 DB10 17 DB9 16 DB8 15 DB7 PIN DESCRIPTIONS PIN NAME DESCRIPTION PLCC A T U O V B T U O V H F E R V L F E R V C T U O V D T U O V S S V 4 3 2 1 28 27 26 DAC7724 DAC7725 12 4 B D 13 5 B D 14 6 B D 15 7 B D 16 8 B D 17 9 B D 18 0 1 B D 25 24 VCC VDD 23 CS 22 A0 21 A1 20 R/W 19 DB11 (MSB) GND RESET LDAC (LSB) DB0 DB1 5 6 7 8 9 DB2 10 DB3 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VREFH VOUTB VOUTA VSS GND RESET LDAC DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 R/W A1 A0 CS VDD VCC VOUTD VOUTC VREFL Reference Input Voltage High. Sets maximum output voltage for all DACs. DAC B Voltage Output. DAC A Voltage Output. Negative Analog Supply Voltage, 0V or –15V. Ground. Asynchronous Reset Input. Sets DAC and input registers to either mid-scale (800H, DAC7724) or zero-scale (000H, DAC7725) when LOW. Load DAC Input. All DAC Registers are transparent when LOW. Data Bit 0. Least significant bit of 12-bit word. Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11. Most significant bit of 12-bit word. Read/Write Control Input (read = HIGH, write = LOW). Register/DAC Select (C or D = HIGH, A or B = LOW). Register/DAC Select (B or D = HIGH, A or C = LOW). Chip Select Input. Positive Digital Supply, +5V. Positive Analog Supply Voltage, +15V nominal. DAC D Voltage Output. DAC C Voltage Output. Reference Input Voltage Low. Sets minimum output voltage for all DACs. 5 DAC7724, 7725 ®

TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25 C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE Single Channel 25°C (Typical of Each Output Channel) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE Single Channel 85°C (Typical of Each Output Channel) ) B S L ( E L ) B S L ( E L D 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code ZERO-SCALE ERROR vs TEMPERATURE (Code 004H) DAC B DAC D DAC A DAC C ) V m ( r o r r l E e a c S - o r e Z 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) ) B S L ( E L ) B S L ( E L D 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE Single Channel –40°C (Typical of Each Output Channel) ) B S L ( E L ) B S L ( E L D 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code ) V m ( r o r r l E e a c S - l l u F FULL-SCALE ERROR vs TEMPERATURE (Code FFFH) DAC A DAC B DAC D DAC C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) ) A m ( t n e r r u C F E R V ) A m ( t n e r r u C F E R V 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 000H ® DAC7724, 7725 6 CURRENT vs CODE All DACs Sent to Indicated Code VREFH VREFL 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code

TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25 C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified. ) A m ( t n e r r u C t n e c s e u Q i 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 POWER SUPPLY CURRENT vs TEMPERATURE POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE ICC IDD No Load 3.00 2.50 2.00 1.50 1.00 0.50 ) A m ( C C I ICC IDD –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) 0 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code OUTPUT VOLTAGE vs SETTLING TIME (0V to +10V) Large Signal Settling Time: 5V/div Small Signal Settling Time: 1LSB/div e g a t l o V t u p t u O OUTPUT VOLTAGE vs SETTLING TIME (+10V to 0V) Large Signal Settling Time: 5V/div Small Signal Settling Time: 1LSB/div e g a t l o V t u p t u O Time (2µs/div) +5V LDAC 0 Time (2µs/div) +5V LDAC 0 OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE i / ) v d V m 0 0 2 ( e g a t l o V t u p t u O 7FFH to 800H Time (1µs/div) +5V LDAC 0 i / ) v d V m 0 0 2 ( e g a t l o V t u p t u O 800H to 7FFH Time (1µs/div) +5V LDAC 0 ® 7 DAC7724, 7725

TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25 C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified. OUTPUT NOISE vs FREQUENCY LOGIC SUPPLY CURRENT vs LOGIC INPUT LEVEL FOR DATA BITS 1000 ) z H √ / V n ( i e s o N 100 Code 004H Code FFFH 10 0 0.1 1 10 100 1000 10000 Frequency (kHz) 16 14 12 10 8 6 4 2 ) V ( T U O V 0 0.01 OUTPUT VOLTAGE vs RLOAD Source Sink 0.1 1 10 100 RLOAD (kW) 5 4 3 2 1 0 20 15 10 5 0 –5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Logic Input Level for Data Bits (V) SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE Short to Ground ) A m l ( t n e r r u C y p p u S c g o L i ) A m ( T U O I –10 –15 –20 Short to VCC 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code ) B d ( R R S P 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 POWER SUPPLY REJECTION RATIO vs FREQUENCY +15V +5V 101 102 103 104 Frequency (Hz) 105 106 ® DAC7724, 7725 8

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