联想Y500 NM-A142 LA-8692P.pdf

发布时间：2022-06-07 发布人：admin 分类：说明书资料大小：2.05M 资料格式：pdf 举报版权申诉

mr_fei-13108202-16359647455655881609.pdf-第1页.png

第1页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第2页.png

第2页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第3页.png

第3页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第4页.png

第4页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第5页.png

第5页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第6页.png

第6页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第7页.png

第7页 / 共66页

mr_fei-13108202-16359647455655881609.pdf-第8页.png

第8页 / 共66页

文本预览

A B C D E 1 2 3 4 LA-8692P Rev0.2 Schematic Brandy3.0 (Y500) QIQY6 w w w . c h i n a f i x . c o m 2012-02-05 Rev0.2 nVIDIA N13P GT-1 + 2nd VGA N13P GT-1 Intel IVY Bridge Processor with DDRIII + Panther Point PCH 1 2 3 4 A B C D Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom Custom Custom Size Document Number Size Document Number Size Document Number Compal Electronics, Inc. Compal Electronics, Inc. Compal Electronics, Inc. Cover Page Cover Page Cover Page LA-8692P LA-8692P LA-8692P Rev Rev Rev 0.2 0.2 0.2 Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 Sheet Sheet Sheet 1 1 1 of of of 66 66 66 E

A B C D E Chief River PCI-Express 16X Gen3 Intel 1 2 3 4 PEG 8~15 PEG 0~7 2nd VGA N13P-GT1 VRAM 64*32 GDDR5*8 Sub/B (SLI) Page 32 N13P-GT1 VRAM 64*32 GDDR5*8 Page 23,24,25,26,27,28,29,30,31 HDMI Conn. Page 37 HDMI1.4b RJ45 Conn. Page 40 Power Circuit DC/DC Page 54,55,56,57,58,59, 60,61,62,63,64 DC/DC Interface CKT. Page 53 RTC CKT. Page 54 POWER/B Conn. Page 51 AUDIO, USB/B Conn. Page 49 ODD/B Conn. page 42 A NOVO/B Conn. Page 51 CRT Conn. Page 36 LVDS Conn. Page 34 IVY Bridge Processor Memory BUS (DDRIII) Dual Channel Atheros AR8161 1G AR8151 1G PCIe port 1 Page 39 CardReader JMB389 SD/MMC/MS/XD PCIe port 4 Page 44 PCH USB 3.0 3x 5V 5GT/s USB 2.0 2x 5V 480MHz FCBGA 989 Balls 25mm*25mm PCIe Gen1 1x 1.5V 5GT/s Socket-rPGA989 37.5mm*37.5mm DMI *4 5GT/s FDI *8 2.7GT/s USB Left USB 3.0 Port 2 USB 3.0 Port 3 Int. Camera USB 3.0 Port 0 USB 2.0 Port 0 1.5V DDRIII 1066/1333/1600 MT/s USB 2.0 1x 5V 480MHz USB 2.0 3x 5V 480MHz Intel Panther Point w w w . c h i n a f i x . c o m Codec ALC269Q-VC3 Thermal Sensor EMC 1403 EC ITE IT8580E SATA Gen3 Port 0 5V 6GHz(600MB/s) SATA Gen1 Port2 5V 3GHz(300MB/s) SATA Gen3 Port 1 5V 6GHz(600MB/s) PCIeMini Card WLAN PCIeMini Card WLAN Int. MIC Conn. (JCMOS Conn.) PCIe Gen1 2x 5V 480MHz Touch Pad Int.KBD Page 46 Page 46 Page 41 HD Audio 3.3V 24MHz PCIe Gen1 1x 1.5V 5GT/s SATA ODD SATA Port 1 page 41 SATA HDD SATA Port 1 page 41 PCIe Port 2 page 38 USB Port 10 page 38 Page 50 Sub/B LPC BUS 3.3V 33MHz SPI ROM (4MB+2MB) Page 14 SPI BUS 3.3V 33MHz Page 45 Page 43 TV USB 2.0 Port 12 Page 38 Page 48 BT USB 2.0 Port 13 Page 50 Page 47 mSATA SSD SATA Port 0 page 38 PCIeMini Card TV PCIe Port 3 Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Size Document Number Size Document Number Custom Custom Custom B C D DDR3-SO-DIMM X2 BANK 0, 1, 2, 3 UP TO 16G USB Charger PS8710BT Page 50 USB Right USB 2.0 Port 9, Cha Sub/B Page 50 HP Conn. USB Port 12 page 38 SPK Conn. Page 43 Ext. MIC Conn. Page 49 Sub/B Page 49 Compal Electronics, Inc. Compal Electronics, Inc. Compal Electronics, Inc. MB Block Diagram MB Block Diagram MB Block Diagram LA-8692P Rev Rev Rev 0.2 0.2 0.2 Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 Sheet Sheet Sheet 2 2 2 of of of 66 66 66 E 1 2 3 4

A B C D E Voltage Rails power plane 1 State S0 S3 2 S5 S4/AC S5 S4/ Battery only S5 S4/AC & Battery don't exist +B O O O O X +5VALW +3VALW O O O X X SMBUS Control Table Main2ndVGAXXXX VGA SOURCE SMB_EC_CK1 IT8580E X SMB_EC_DA1 +3VALW SMB_EC_CK2 IT8580E XX SMB_EC_DA2 +3VALW SMBCLK PCH X SMBDATA +3VALW SML0CLK PCH SML0DATA +3VALW SML1CLK PCH V+3VS V SML1DATA +3VS +3VALW PCH SM Bus address EC SM Bus1 address Smart Battery 0001 011X b 1001 000Xb 1001 010Xb Address Address DDR DIMM0 DDR DIMM2 Device Device 3 4 ZZZ ZZZ DA80000T20J DA80000T20J BATTIT8580E XXX V +3VALW X XXX V X +3VS SODIMM XXX V +3VS X EC SM Bus2 address Device Address Thermal Sensor EMC1403-2 1001_101xb Master VGA Slave VGA A B C D Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Custom Custom Custom Size Document Number Size Document Number Size Document Number Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 +5VS +3VS +1.5VS +VCCSA STATE SIGNAL SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW Full ON HIGH HIGH HIGH HIGH S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON +V ON ON +VS Clock ON ON ON LOW +V1.5S_VCCP +1.5V O LOW X O O X X X XHCI Port HIGH ON +1.8VS +1.05VS +0.75VS LOW LOW OFF OFF OFF OFF OFF OFF OFF OFF LOW LOW LOW LOW +GFX_CORE LOW HIGH LOW HIGH +CPU_CORE ON ON ON +VGA_CORE X X X +3.3VS_VGA +1.5VS_VGA +1.05VS_VGA USB 2.0 USB 3.0 S5 (Soft OFF) S3 (Suspend to RAM) S4 (Suspend to Disk) USB Port Table 4 External USB Port Camera Camera BOM Structure Table BOM Structure w w w . c h i n a f i x . c o m Thermal Sensor XX X X V +3VS WLANWWAN X VXX +3VS X PCH XXX V +3VS X HDMI@ TV@ CMOS@ 8161@ 8151@ 8161S@ 8151S@ SURGE@ X76@ GC6@ NOGC6@ AOAC@ USB Port (Left Side) USB Port (Left Side) USB Port (Left Side) USB Port (Left Side) PCIE PORT LIST Device LAN WLAN TV Card Reader Mini Card(TV) Blue Tooth KBL@ ME@ OPT@ SLI@ USB Port (Right Side) 8 9 10 11 12 13 Mini Card(WLAN) DS3@ GT@ @ 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 1 2 3 4 HDMI part EHCI2 EHCI1 0x9E 0x9C ME part Port NV chip part Unpop BTO Item TV module part CMOS Camera part AR8161 LAN part AR8151 LAN part AR8161 LAN surge part AR8151 LAN surge part AR8151&8161 LAN surge part X76 Level part for VRAM NV CG6 support part NV no CG6 support part AOAC support part K/B Light part For optimus function part For SLI function part Deep S3 support part 1 2 3 4 Compal Electronics, Inc. Compal Electronics, Inc. Compal Electronics, Inc. Notes List Notes List Notes List LA-8692P LA-8692P LA-8692P Sheet Sheet Sheet E Rev Rev Rev 0.2 0.2 0.2 3 3 3 of of of 66 66 66

D C B A 5 4 3 2 1 Hot plug detect for IFP link E Performance Mode P0 TDP at Tj = 102 C* (GDDR5) VGA and GDDR5 Voltage Rails (N13Px GPIO) GPIO I/O ACTIVE Function Description GPU (4) Products (W) Mem (1,5) (W) NVCLK /MCLK NVVDD FBVDD (1.35V) FBVDDQ (GPU+Mem) (1.35V) PCI Express I/O and (1.05V) (6) PLLVDD (1.8V) I/O and PLLVDD (1.05V) Other (3.3V) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) GPU VID4 GPU VID3 VGA_BL_PWM VGA_ENVDD VGA_ENBKL GPU VID1 GPU VID2 DPRSLPVR_VGA GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 OUT OUT OUT OUT OUT OUT OUT OUT GPIO8 I/O GPIO9 OUT GPIO10 OUT GPIO11 OUT GPIO12 IN GPIO13 OUT GPIO14 OUT - - - - - - - - - - - - - - Thermal Catastrophic Over Temperature GPIO9 Memory VREF Control GPU VID0 AC Power Detect Input GPU VID5 FB_CLAMP_TOGGLE_REQ# (10K pull High) GPIO15 IN N/A (100K pull low) GPIO16 OUT GPIO17 GPIO18 GPIO19 IN IN IN - N/A - - GPIO16 GPIO17 dGPU_HDMI_HPD GPIO19 +3VS_VGA +VGA_CORE +1.5VS_VGA +1.05VS_VGA tNVVDD >0 tFBVDDQ >0 tPEX_VDD >0 1. all power rail ramp up time should be larger than 40us Other Power rail +3VS_VGA Tpower-off <10ms N13X 128bit 1GB GDDR5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0 1 GPU STRAP1 Power Rail SOR2_EXPOSED PU 25K GC6@ Device ID 0x0FDB 0x9E 0x9C USER[1] USER[0] SMB_ALT_ADDR (ROM_SO Bit 1) PU 5K OPT@,SLI@ RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] FB[0] USER[2] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] SLOT_CLK_CFG PEX_PLL_EN_TERM SOR1_EXPOSED SOR0_EXPOSED SMB_ALT_ADDR VGA_DEVICE +3VS_VGA RESERVED ROM_SI ROM_SO STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 +3VS_VGA USER[3] +3VS_VGA FB[1] PU 45K PD 5K PD 10K PCIE_MAX_SPEED DP_PLL_VDD33V +3VS_VGA SOR3_EXPOSED +3VS_VGA PCI_DEVID[4] +3VS_VGA RAM_CFG[3] N13P-GT (28nm) +3VS_VGA PCI_DEVID[3] ROM_SO ROM_SCLK STRAP0 STRAP2 STRAP3 STRAP4 N13P-GT1 28nm PCIE_SPEED_ CHANGE_GEN3 setting I2C Slave addrees ID Logical Strapping Bit3 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0] Logical Strapping Bit1 Logical Strapping Bit0 Physical Strapping pin ROM_SCLK Logical Strapping Bit2 SUB_VENDOR w w w . c h i n a f i x . c o m FB Memory (GDDR5) Compal Secret Data Compal Secret Data Compal Secret Data Hynix 2500MHz Hynix 2500MHz Samsung 2500MHz Samsung 2500MHz K4G10325FD-FC04 K4G20325FD-FC04 N13P-GT ROM_SI PU 5K SLI@ PD 5K OPT@ 32Mx32 PD 45K 32Mx32 PD 35K 64Mx32 PD 25K 64Mx32 PD 30K H5GQ2H24MFR-T2C Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date H5GQ1H24BFR-T2C PU 10K GPU PD 45K D C B A Compal Electronics, Inc. Compal Electronics, Inc. Compal Electronics, Inc. Title Title Title Size Size Size Document Number Document Number Document Number VGA Notes List VGA Notes List VGA Notes List LA-8692P LA-8692P LA-8692P Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 Sheet Sheet Sheet 4 4 4 of of of 66 66 66 1 Rev Rev Rev 0.2 0.2 0.2 1.all GPU power rails should be turned off within 10ms 2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ 2011/07/21 2011/07/21 2011/07/21 Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2

5 4 3 2 1 D C B A +1.05VS <16> <16> FDI_FSYNC0 FDI_FSYNC1 <16> FDI_INT <16> <16> FDI_LSYNC0 FDI_LSYNC1 R7 R7 24.9_0402_1% 24.9_0402_1% 1 2 eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> <16> JCPU1A JCPU1A PCIE_CRX_GTX_P[0..15] <23,32> PCIE_CRX_GTX_N[0..15] <23,32> R1 R1 24.9_0402_1% 24.9_0402_1% PEG_COMP 0:Lane Reversed * +1.05VS 1 2 B27 B25 A25 B24 B28 B26 A24 B23 G21 E22 F21 D21 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO J22 J21 H22 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G22 DMI_TX[0] D22 DMI_TX[1] F20 C21 DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N15 w w w . c h i n a f i x . c o m PCIE_CTX_GRX_C_N0 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_P0 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N15 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P15 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P15 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K 0.22U_0402_10V6K PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 1 C20 C20 1 C23 C23 1 C25 C25 1 C30 C30 1 C18 C18 1 C22 C22 1 C28 C28 1 C32 C32 SLI@C19 SLI@ 1 C19 SLI@ 1 C24 SLI@C24 SLI@C29 SLI@ 1 C29 SLI@C17 SLI@ 1 C17 SLI@C21 SLI@ 1 C21 1 SLI@C27 SLI@ C27 SLI@C26 SLI@ 1 C26 SLI@C31 SLI@ 1 C31 1 C1 C1 1 C2 C2 1 C3 C3 1 C4 C4 1 C5 C5 1 C6 C6 1 C7 C7 1 C8 C8 SLI@C9 SLI@ 1 C9 1 SLI@C10 SLI@ C10 SLI@ 1 SLI@C11 C11 SLI@C12 SLI@ 1 C12 SLI@C13 SLI@ 1 C13 SLI@C14 SLI@ 1 C14 SLI@ 1 SLI@C15 C15 1 SLI@C16 SLI@ C16 S S C C I I H H P P A A R R G G - - * * S S S S E E R R P P X X E E I I C C P P FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] A21 H19 E19 F18 B21 C20 D18 E17 A22 G19 E20 G18 B20 C19 D19 F17 J18 J17 H20 J19 H17 I I D D F F ) ) R R ( ( l l e e t t n n I I eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1 A18 A17 B16 C15 D15 C17 F16 C16 G15 C18 E16 D16 F15 EDP_COMP eDP_HPD eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX eDP_AUX# 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE ME@ ME@ I I M M D D P P D D e e PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils - typical impedance = 14.5 mohms PEG Static Lane Reversal - CFG2 is for the 16x CFG2 1: Normal Operation; Lane # definition matches socket pin map definition PCIE_CTX_GRX_N[0..15] <23,32> PCIE_CTX_GRX_P[0..15] <23,32> D C B A 5 4 3 2 Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title Compal Electronics, Inc. PROCESSOR(1/7) DMI,FDI,PEG PROCESSOR(1/7) DMI,FDI,PEG PROCESSOR(1/7) DMI,FDI,PEG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Size Document Number Size Document Number Custom Custom Custom Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 LA-8692P LA-8692P LA-8692P Sheet Sheet Sheet 1 5 5 5 of of of 66 66 66 Rev Rev Rev 0.2 0.2 0.2

5 4 3 2 1 D C B A +1.05VS R9 R9 62_0402_5% 62_0402_5% 1 2 Reserve 43 Ohm resistor closs to EC(250~750mils) <45> H_PECI <45,54> H_PROCHOT# H_PROCHOT# <19> H_THRMTRIP# 1 <16> 0_0402_5%1 0_0402_5% R26 R26 2 <19,6> H_CPUPWRGD C550 C550 100P_0402_50V8J 100P_0402_50V8J 1 2 R27 R27 10K_0402_5% 10K_0402_5% 2 1 9/23 ESD Request <16> SYS_PWROK +3VS +3VALW 1 2 R65 R65 R338 R338 0_0402_5% @ 0_0402_5% @ 10K_0402_5% 10K_0402_5% 2 1 <16> PM_DRAM_PWRGD 1 2 1 2 C33 C33 0.1U_0402_16V4Z 0.1U_0402_16V4Z U1 U1 O 4 PM_SYS_PWRGD_BUF 74AHC1G09GW_TSSOP5 74AHC1G09GW_TSSOP5 5 B A P G 3 CLK_CPU_DMI CLK_CPU_DMI# <15> <15> H_PM_SYNC 1 1 1 R29 R29 1 1 1 1 1 +1.05VS T14 T14 PAD PAD AK1 A5 A4 JCPU1B JCPU1B SKTOCC# UNCOREPWRGOOD SM_DRAMPWROK H_DRAMRST# <7> PROCHOT# THERMTRIP# <19> H_SNB_IVB# PROC_SELECT# C26 AN34 CATERR# PECI SM_DRAMRST# R8 H_DRAMRST# H_PM_SYNC_R AM34 PM_SYNC 1 1 R1499 R1499 R1500 R1500 R1501 R1501 R1502 R1502 R1503 R1503 TDI TDO DBR# H_CATERR# AL33 H_PECI AN33 BCLK BCLK# A28 A27 H_THRMTRIP# AN32 R16 R16 R17 R17 R18 R18 2 2 2 A16 A15 R12 R12 R13 R13 2 2 PRDY# PREQ# TCK TMS TRST# R15 R15 56_0402_5% 56_0402_5% R22 R22 0_0402_5% 0_0402_5% 1 2 H_CPUPWRGD_R AP33 BUF_CPU_RST# AR33 XDP_TDI_R XDP_TDO_R XDP_PRDY# XDP_PREQ# AP29 AP27 AR26 AR27 AP30 AR28 AP26 XDP_TDI XDP_TDO PM_DRAM_PWRGD_R V8 C C S S I I M M 2 H_PROCHOT#_R AL32 C C S S I I M M 1 130_0402_5% 130_0402_5% 2 R1504 R1504 R1505 R1505 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 2 2 XDP_PRDY#_R XDP_PREQ#_R 1 1 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% CLK_CPU_DMI CLK_CPU_DMI# DPLL_REF_CLK DPLL_REF_CLK# 3 3 R R D D D D XDP_TCK XDP_TMS XDP_TRST# 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 S S K K C C O O L L C C 140_0402_1% 140_0402_1% 25.5_0402_1% 25.5_0402_1% 200_0402_1% 200_0402_1% SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] XDP_TCK_R XDP_TMS_R XDP_TRST#_R L L A A M M R R E E H H T T M M P P B B & & G G A A T T J J T T N N E E M M E E G G A A N N A A M M R R W W P P w w w . c h i n a f i x . c o m XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R +1.05VS <18,23,32,38,39,44,45,6> 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32 Buffered reset to CPU 2 2 2 2 PAD PAD PAD PAD PAD PAD PAD PAD C34 C34 0.1U_0402_16V4Z 0.1U_0402_16V4Z TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE R30 R30 200_0402_5% 200_0402_5% SN74LVC1G07DCKR_SC70-5 SN74LVC1G07DCKR_SC70-5 <8> CFG0 <16,60> 1 1 1 1 R1506 R1506 R1507 R1507 R1508 R1508 R1509 R1509 This is NC pin R34 R34 2 43_0402_1% 43_0402_1% 1 2 AL35 XDP_DBRESET# R28 R28 2 R32 R32 75_0402_5% 75_0402_5% 1 2 P NC G A @R35 R35 @ 0_0402_5% 0_0402_5% 1 1K_0402_5% 1K_0402_5% +3VS +1.05VS 1 1 2 Y PLT_RST# PLT_RST# BUF_CPU_RST# BUFO_CPU_RST# 4 U2 U2 5 3V T31 T31 T30 T30 T33 T33 T32 T32 1.05V 1 2 +3VS 3 RESET# ME@ ME@ +1.5V_CPU_VDDQ 1 2 DDR3 Compensation Signals PU/PD for JTAG signals +1.05VS XDP_TMS XDP_TDI XDP_TDO R20 R20 R21 R21 R23 R23 XDP_TCK XDP_TRST# R24 R24 R25 R25 2 2 2 2 2 1 1 1 @ @ 1 1 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% XDP Connector JXDP1 JXDP1 @ @ XDP_PREQ#_R XDP_PRDY#_R XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R R1510 R1510 1K_0402_5% 1K_0402_5% 2 1 H_CPUPWRGD_R PBTN_OUT# 1 2 CFG0_R 1K_0402_5% 1K_0402_5% VGATE CLK_BCLK_ITP CLK_BCLK_ITP# PLT_RST# PLT_RST# XDP_DBRESET# XDP_TDO_R XDP_TRST#_R XDP_TDI_R XDP_TMS_R XDP_TCK_R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MOLEX 52435-2671 MOLEX 52435-2671 <19,6> <16,45> H_CPUPWRGD PBTN_OUT# R1511 R1511 <15> <15> VGATE CLK_BCLK_ITP CLK_BCLK_ITP# <18,23,32,38,39,44,45,6> D C B A 5 4 3 2 Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title Compal Electronics, Inc. PROCESSOR(2/7) PM,XDP,CLK PROCESSOR(2/7) PM,XDP,CLK PROCESSOR(2/7) PM,XDP,CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Size Document Number Size Document Number Custom Custom Custom Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 LA-8692P LA-8692P LA-8692P Sheet Sheet Sheet 1 6 6 6 of of of 66 66 66 Rev Rev Rev 0.2 0.2 0.2

5 4 3 2 1 JCPU1C JCPU1C JCPU1D JCPU1D D C B A <12> DDR_A_D[0..63] <12> <12> <12> DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 <12> <12> <12> DDR_A_CAS# DDR_A_RAS# DDR_A_WE# DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] AE8 AD9 AF9 SA_CAS# SA_RAS# SA_WE# SA_CK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA <12> <13> <12> <12> DDR_B_D[0..63] <12> DDR_A_DQS#[0..7] <12> SA_CK[2] SA_CLK#[2] SA_CKE[2] SA_CK[1] SA_CLK#[1] SA_CKE[1] M_ODT0 M_ODT1 <12> <12> SA_CK[3] SA_CLK#[3] SA_CKE[3] AB3 AA3 W10 AK3 AL3 AG1 AH1 AH3 AG3 AG2 AH2 AA5 AB5 V10 AB4 AA4 W9 DDR_CS0_DIMMA# DDR_CS1_DIMMA# <12> <12> SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] C4 G6 J3 M6 AL6 AM8 AR12 AM15 M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA <12> <12> SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 A A Y Y R R O O M M E E M M M M E E T T S S Y Y S S R R D D D D C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] w w w . c h i n a f i x . c o m DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] B B Y Y R R O O M M E E M M M M E E T T S S Y Y S S R R D D D D DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_B_CAS# DDR_B_RAS# DDR_B_WE# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 <13> <13> <13> <13> <13> <13> AA9 AA7 R6 SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 SB_CAS# SB_RAS# SB_WE# DDR3_DRAMRST# <12,13> TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE DDR_A_DQS[0..7] <12> R38 R38 1K_0402_5% 1K_0402_5% DDR_A_MA[0..15] <12> ME@ ME@ SB_CK[0] SB_CLK#[0] SB_CKE[0] SB_CK[1] SB_CLK#[1] SB_CKE[1] SB_CK[2] SB_CLK#[2] SB_CKE[2] SB_CK[3] SB_CLK#[3] SB_CKE[3] SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] AE2 AD2 R9 AE1 AD1 R10 AB2 AA2 T9 AA1 AB1 T10 AD3 AE3 AD6 AE6 AE4 AD4 AD5 AE5 D7 F3 K6 N3 AN5 AP9 AK12 AP15 C7 G3 J6 M3 AN6 AP8 AK11 AP14 AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB <13> <13> <13> M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB <13> <13> <13> D DDR_CS2_DIMMB# DDR_CS3_DIMMB# <13> <13> M_ODT2 M_ODT3 <13> <13> DDR_B_DQS#[0..7] <13> C DDR_B_DQS[0..7] <13> DDR_B_MA[0..15] <13> B A Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Size Document Number Size Document Number Custom Custom Custom Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 Compal Electronics, Inc. PROCESSOR(3/7) DDRIII PROCESSOR(3/7) DDRIII PROCESSOR(3/7) DDRIII LA-8692P LA-8692P LA-8692P Sheet Sheet Sheet 1 Rev Rev Rev 0.2 0.2 0.2 7 7 7 of of of 66 66 66 TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE ME@ ME@ +1.5V R37 R37 1K_0402_5% 1K_0402_5% 1 2 <6> H_DRAMRST# H_DRAMRST# 3 S S 1 D D DDR3_DRAMRST#_R 1 2 R39 R39 4.99K_0402_1% 4.99K_0402_1% No DS3 to stuff R40 2 1 Q2 Q2 G G 2 BSS138_NL_SOT23-3 BSS138_NL_SOT23-3 <15> DRAMRST_CNTRL_PCH <10> DRAMRST_CNTRL <45> DRAMRST_CNTRL_EC 1 R40 R40 1 R64 R64 @ @ DRAMRST_CNTRL 2 0_0402_5% 0_0402_5% 2 0_0402_5% 0_0402_5% DS3@ DS3@ 1 2 C35 C35 0.047U_0402_16V4Z 0.047U_0402_16V4Z Module design used 0.047u 5 4 3 2

D C B A 5 4 3 2 1 CFG Straps for Processor CFG2 1 @ @ R41 R41 1K_0402_1% 1K_0402_1% 2 PEG Static Lane Reversal - CFG2 is for the 16x CFG2 * 1: Normal Operation; Lane # definition matches socket pin map definition 1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port 11/24 Intel recommend to reserve test point JCPU1E JCPU1E PAD PAD T13 T13 <6> CFG0 G G F F C C CFG4 * AH27 AH26 L7 AG7 AE7 AK2 W8 RSVD33 RSVD34 RSVD35 AT26 AM33 AJ27 0:Lane Reversed CFG0 CFG2 CFG5 CFG6 CFG7 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 VCC_DIE_SENSE VSS Display Port Presence Strap AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] w w w . c h i n a f i x . c o m F25 RSVD8 F24 RSVD9 F23 RSVD10 D24 RSVD11 G25 RSVD12 G24 RSVD13 E23 RSVD14 D23 C30 RSVD15 RSVD16 A31 RSVD17 B30 RSVD18 B29 D30 RSVD19 RSVD20 B31 A30 RSVD21 RSVD22 C29 RSVD23 VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9 RSVD_NCTF10 RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5 D D E E V V R R E E S S E E R R PCIE Port Bifurcation Straps RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13 T56 PAD T56 PAD T57 PAD T57 PAD T58 PAD T58 PAD T59 PAD T59 PAD AJ31 AH31 AJ33 AH33 AJ26 PEG DEFER TRAINING RSVD37 RSVD38 RSVD39 RSVD40 J20 B18 RSVD24 RSVD25 RSVD51 RSVD52 AJ32 AK32 BCLK_ITP BCLK_ITP# AN35 AM35 R43 R43 1K_0402_1% 1K_0402_1% R44 @ R44 @ 1K_0402_1% 1K_0402_1% @R45 R45 @ 1K_0402_1% 1K_0402_1% TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE AR35 AT34 AT33 AP35 AR34 J15 RSVD27 B34 A33 A34 B35 C35 1 1 2 2 AT2 AT1 AR1 B1 KEY CFG6 CFG5 CFG[6:5] T8 J16 H16 G16 CFG7 1 2 RSVD5 ME@ ME@ 11: (Default) x16 - Device 1 functions 1 and 2 disabled * 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training D C B A 5 4 3 2 Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 2011/07/21 2011/07/21 2011/07/21 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date 2012/12/31 2012/12/31 2012/12/31 Title Title Title Compal Electronics, Inc. PROCESSOR(4/7) RSVD,CFG PROCESSOR(4/7) RSVD,CFG PROCESSOR(4/7) RSVD,CFG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Size Document Number Size Document Number Size Document Number Custom Custom Custom LA-8692P LA-8692P LA-8692P Rev Rev Rev 0.2 0.2 0.2 Date: Date: Date: Saturday, April 28, 2012 Saturday, April 28, 2012 Saturday, April 28, 2012 Sheet Sheet Sheet 8 8 8 of of of 66 66 66 1

分享到：

赞收藏

资料库

联想Y500 NM-A142 LA-8692P.pdf

相关推荐

操作系统

热门标签

最新资料