第1页 / 共82页
第2页 / 共82页
第3页 / 共82页
第4页 / 共82页
第5页 / 共82页
第6页 / 共82页
第7页 / 共82页
第8页 / 共82页
IT8892_IT8893_F_V0.7_081911(1).pdf
1. Features
2. General Description
3. Block Diagram
4. Pin Configuration
4.1 IT8892E Pin Configuration
4.2 IT8893E Pin Configuration
5. Pin Description
5.1 IT8892E Pin Description
5.2 IT8893E Pin Description
6. Functional Description
6.1 Register Description
6.1.1 Register Abbreviation
6.1.2 List of PCI Configuration Registers
6.2 Register Definition of PCI Configuration Register
6.2.1 Vendor ID Register (VID)
6.2.2 Device ID Register (DID)
6.2.3 PCI Command Register (PCICMD)
6.2.4 Status Register (STS)
6.2.5 Revision ID Register (REVID)
6.2.6 Class Code Register (CC)
6.2.7 Cache Line Size Register (CLS)
6.2.8 Master Latency Timer Register (MLT)
6.2.9 Header Type Register (HEADTYP)
6.2.10 BIST Register (BIST)
6.2.11 Base Address Register 0 (BAR0)
6.2.12 Base Address Register 1 (BAR1)
6.2.13 Primary Bus Number Register (PBN)
6.2.14 Secondary Bus Number Register (SCBN)
6.2.15 Subordinate Bus Number Register (SBBN)
6.2.16 Secondary Latency Timer Register (SLT)
6.2.17 I/O Base Register (IOB)
6.2.18 I/O Limit Register (IOL)
6.2.19 Secondary Status Register (SECSTS)
6.2.20 Memory Base Register (MB)
6.2.21 Memory Limit Register (ML)
6.2.22 Prefetchable Memory Base Register (PMB)
6.2.23 Prefetchable Memory Limit Register (PML)
6.2.24 Prefetchable Base Upper 32 Bits Register (PMB_UPPER)
6.2.25 Prefetchable Limit Upper 32 Bits Register (PML_UPPER)
6.2.26 I/O Limit Upper 16 Bits Register (IOLU16)
6.2.27 I/O Base Upper 16 Bits Register (IOBU16)
6.2.28 Capabilities Pointer Register (CAPP)
6.2.29 Interrupt Line Register (INTRL)
6.2.30 Interrupt Pin Register (INTRP)
6.2.31 Bridge Control Register (BRIDGE_CNT)
6.2.32 Initial Posted Flow Control Credit (IPTFCC)
6.2.33 Initial Non-Posted Flow Control Credit (INPFCC)
6.2.34 Initial Completion Flow Control Credit (ICPLFCC)
6.2.35 Link Layer Control Register (LLCR)
6.2.36 Transaction Layer Control Register (TLCR)
6.2.37 PHY Control Register (PHYCR)
6.2.38 PCI Port 80 Debug Register (P80DR)
6.2.39 PCI Control Register (PCICR)
6.2.40 PCI PAD Skew Control Register (PPSCR)
6.2.41 Serial EEPROM Control Register (SEEPROMCR)
6.2.42 PCI Express Capability Identifier Register (EXP_CAPID)
6.2.43 PCI Express Next Pointer Register (EXP_NXTP)
6.2.44 PCI Express Capability Register (EXP_CAP)
6.2.45 PCI Express Device Capabilities Register (EXP_DEVCAP)
6.2.46 PCI Express Device Control Register (EXP_DEVCNTL)
6.2.47 PCI Express Device Status Register (EXP_DSTS)
6.2.48 PCI Express Link Capabilities Register (EXP_LCAP)
6.2.49 PCI Express Link Control Register (EXP_LCNTL)
6.2.50 PCI Express Link Status Register (EXP_LSTS)
6.2.51 Power Management Capability ID Register (PM_CAPID)
6.2.52 Power Management Next Pointer Register (PM_NXTPTR)
6.2.53 Power Management Capabilities Register (PM_CAP)
6.2.54 Power Management Control and Status Register (PM_CNTLSTS)
6.2.55 SSID Capability ID Register (SSID_CAPID)
6.2.56 SSID Next Pointer Register (SSID_NXTPTR)
6.2.57 SSID Register (SSID)
6.2.58 Dummy Register (DMR)
6.2.59 Transaction Layer Control Register1 (TLCR1)
6.2.60 Transaction Layer Control Register2 (TLCR2)
6.2.61 7-Segment Display Register (7SDR)
6.2.62 GPIO Input Status (GPIOIS)
6.2.63 GPIO Output Register (GPIOOR)
6.2.64 GPIO Output Enable Register (GPIOOER)
6.2.65 GPIO Pull-Up Register (GPIOPUR)
6.2.66 GPIO Pull-Down Register (GPIOPDR)
6.2.67 Device Serial Number Enhanced Capability Header (DSN_ECAPHDR)
6.2.68 Serial Number Register (DSN_SNR)
6.3 PCI Clock
6.4 Reset
6.5 Power Management
6.6 PCI Intrrupt
6.7 PCI Arbiter
6.8 EEPROM
6.8.1 Overview
6.8.2 EEPROM Read Status Operation
6.8.3 EEPROM Write Enable Operation
6.8.4 EEPROM Write Operation
6.8.5 EEPROM Read Operation
6.8.6 Suggested EEPROM Data Content
6.9 Legacy Mode
7. DC Characteristics
8. AC Characteristics
9. PCI Express Interface Characteristics
10. Package Information
11. Ordering Information
12. Top Marking Information
IT8892E/IT8893E
PCI Express to PCI Bridge
Preliminary Specification V0.7
(For F Version)
ITE TECH. INC.
This specification is subject to Change without notice. It is provided “AS IS” and for reference only. For
purchasing information, please contact the nearest ITE TECH sales representatives.
Please note that the IT8892E/IT8893E V0.7 is applicable only to the F version.
CONFIDENTIAL
CONFIDENTIAL
Copyright © 2011 ITE Tech. Inc.
This is a Preliminary document release. All specifications are subject to change without notice.
The material contained in this document supersedes all previous material issued for the products herein
referenced. Please contact ITE Tech. Inc. for the latest document(s).
All sales are subject to ITE’s Standard Terms and Conditions, a copy of which is included in the back of this
document.
ITE, IT8892E/IT8893E is a trademark of ITE Tech. Inc.
All other trademarks are claimed by their respective owners.
All specifications are subject to change without notice.
Additional copies of this manual or other ITE literature may be obtained from:
If you have any marketing or sales questions, please contact:
P.Y. Chang, at ITE Taiwan:
E-mail: p.y.chang@ite.com.tw, Tel: 886-2-29126889 X6052, Fax: 886-2-29102551
You may also find the local sales representative nearest you on the ITE web site.
To find out more about ITE, visit our World Wide Web at:
http://www.ite.com.tw
Or e-mail itesupport@ite.com.tw for more product information/services
ITE Tech. Inc.
Marketing Department
7F, No.233-1, Baociao Rd., Sindian City,
Taipei County 23145, Taiwan, ROC
Phone:
Fax:
(02) 29126889
(02) 2910-2551, 2910-2552
CONFIDENTIAL
CONFIDENTIAL
Revision History
Revision History
Revision
Feature update
PCI Express
Maximum payload size up to 256 bytes
PCI
Suport of up to six queues for memory read cycles
Suported number of outstanding memory read cycles changed
from eight to 24
Revision ID Register (REVID)
Class Code Register (CC)
Secondary Discard Timer (SDT)
Data Credit (DC)
Header Credit (HC)
Initial Non-Posted Flow Control Credit (INPFCC)
Data Credit (DC)
Header Credit (HC)
Memory Read Lock Enable (MRLE)
PCI Output PAD Skew Control
PCI Input PAD Skew Control
Max_Read_Request Size (MRRS)
Default of the following registers updated:
Note below added to PCI Express related registers:
These bits will be hidden with legacy mode.
Registers below added:
Transaction Layer Control Register1 / Transaction Layer Control
Register2
Dummy Register (0000FFFFh)
Capabilities Pointer Register (CAPP)
Default and description updated
Transaction Layer Control Register (TLCR)
PCI Control Register (PCICR)
Function of bit 12 changed into "PCI Clock Slew Control"
Description of bit 31-15 updated
Page No.
-
-
-
-
33
37
39
Section
-
-
-
-
6.2.28
6.2.36
6.2.39
www.ite.com.tw
A
IT8892E/IT8893E V0.7
CONFIDENTIAL
CONFIDENTIAL
CONTENTS
Contents
4.1
4.2
5.1
5.2
1. Features
................................................................................................................................................1
2. General Description .......................................................................................................................................3
3. Block Diagram................................................................................................................................................5
4. Pin Configuration............................................................................................................................................7
IT8892E Pin Configuration ..................................................................................................................7
IT8893E Pin Configuration ................................................................................................................10
5. Pin Description .............................................................................................................................................13
IT8892E Pin Description....................................................................................................................13
IT8893E Pin Description....................................................................................................................16
6. Functional Description..................................................................................................................................21
6.1 Register Description..........................................................................................................................21
6.1.1 Register Abbreviation ...........................................................................................................21
6.1.2 List of PCI Configuration Registers ......................................................................................21
6.2 Register Definition of PCI Configuration Register.............................................................................24
6.2.1 Vendor ID Register (VID)......................................................................................................24
6.2.2 Device ID Register (DID) ......................................................................................................24
6.2.3 PCI Command Register (PCICMD)......................................................................................24
6.2.4 Status Register (STS)...........................................................................................................25
6.2.5 Revision ID Register (REVID) ..............................................................................................26
6.2.6 Class Code Register (CC) ....................................................................................................26
6.2.7 Cache Line Size Register (CLS)...........................................................................................27
6.2.8 Master Latency Timer Register (MLT)..................................................................................27
6.2.9 Header Type Register (HEADTYP)......................................................................................27
6.2.10 BIST Register (BIST)............................................................................................................27
6.2.11 Base Address Register 0 (BAR0).........................................................................................27
6.2.12 Base Address Register 1 (BAR1).........................................................................................28
6.2.13 Primary Bus Number Register (PBN)...................................................................................28
6.2.14 Secondary Bus Number Register (SCBN) ...........................................................................28
6.2.15 Subordinate Bus Number Register (SBBN) .........................................................................28
6.2.16 Secondary Latency Timer Register (SLT) ............................................................................29
6.2.17 I/O Base Register (IOB)........................................................................................................29
6.2.18 I/O Limit Register (IOL).........................................................................................................29
6.2.19 Secondary Status Register (SECSTS).................................................................................29
6.2.20 Memory Base Register (MB) ................................................................................................31
6.2.21 Memory Limit Register (ML) .................................................................................................31
6.2.22 Prefetchable Memory Base Register (PMB) ........................................................................31
6.2.23 Prefetchable Memory Limit Register (PML) .........................................................................31
6.2.24 Prefetchable Base Upper 32 Bits Register (PMB_UPPER) .................................................32
6.2.25 Prefetchable Limit Upper 32 Bits Register (PML_UPPER) ..................................................32
6.2.26 I/O Limit Upper 16 Bits Register (IOLU16) ...........................................................................32
6.2.27 I/O Base Upper 16 Bits Register (IOBU16) ..........................................................................32
6.2.28 Capabilities Pointer Register (CAPP)...................................................................................33
6.2.29 Interrupt Line Register (INTRL) ............................................................................................33
6.2.30 Interrupt Pin Register (INTRP) .............................................................................................33
6.2.31 Bridge Control Register (BRIDGE_CNT) .............................................................................33
6.2.32 Initial Posted Flow Control Credit (IPTFCC).........................................................................36
6.2.33 Initial Non-Posted Flow Control Credit (INPFCC) ................................................................36
6.2.34 Initial Completion Flow Control Credit (ICPLFCC) ...............................................................37
6.2.35 Link Layer Control Register (LLCR) .....................................................................................37
6.2.36 Transaction Layer Control Register (TLCR).........................................................................37
www.ite.com.tw
i
IT8892E/IT8893E V0.7
CONFIDENTIAL
IT8892E/IT8893E (For F Version)
6.2.37 PHY Control Register (PHYCR) ...........................................................................................38
6.2.38 PCI Port 80 Debug Register (P80DR)..................................................................................38
6.2.39 PCI Control Register (PCICR) ..............................................................................................39
6.2.40 PCI PAD Skew Control Register (PPSCR) ..........................................................................39
6.2.41 Serial EEPROM Control Register (SEEPROMCR)..............................................................40
6.2.42 PCI Express Capability Identifier Register (EXP_CAPID)....................................................41
6.2.43 PCI Express Next Pointer Register (EXP_NXTP) ................................................................41
6.2.44 PCI Express Capability Register (EXP_CAP) ......................................................................41
6.2.45 PCI Express Device Capabilities Register (EXP_DEVCAP)................................................41
6.2.46 PCI Express Device Control Register (EXP_DEVCNTL).....................................................42
6.2.47 PCI Express Device Status Register (EXP_DSTS)..............................................................43
6.2.48 PCI Express Link Capabilities Register (EXP_LCAP)..........................................................44
6.2.49 PCI Express Link Control Register (EXP_LCNTL)...............................................................44
6.2.50 PCI Express Link Status Register (EXP_LSTS)...................................................................45
6.2.51 Power Management Capability ID Register (PM_CAPID) ...................................................45
6.2.52 Power Management Next Pointer Register (PM_NXTPTR).................................................45
6.2.53 Power Management Capabilities Register (PM_CAP).........................................................45
6.2.54 Power Management Control and Status Register (PM_CNTLSTS) ....................................46
6.2.55 SSID Capability ID Register (SSID_CAPID) ........................................................................47
6.2.56 SSID Next Pointer Register (SSID_NXTPTR)......................................................................47
6.2.57 SSID Register (SSID) ...........................................................................................................47
6.2.58 Dummy Register (DMR) .......................................................................................................47
6.2.59 Transaction Layer Control Register1 (TLCR1).....................................................................47
6.2.60 Transaction Layer Control Register2 (TLCR2).....................................................................49
6.2.61 7-Segment Display Register (7SDR)....................................................................................49
6.2.62 GPIO Input Status (GPIOIS).................................................................................................50
6.2.63 GPIO Output Register (GPIOOR).........................................................................................50
6.2.64 GPIO Output Enable Register (GPIOOER)..........................................................................50
6.2.65 GPIO Pull-Up Register (GPIOPUR) .....................................................................................50
6.2.66 GPIO Pull-Down Register (GPIOPDR).................................................................................51
6.2.67 Device Serial Number Enhanced Capability Header (DSN_ECAPHDR).............................51
6.2.68 Serial Number Register (DSN_SNR) ...................................................................................52
6.3 PCI Clock...........................................................................................................................................52
6.4 Reset 54
6.5 Power Management ..........................................................................................................................54
6.6 PCI Intrrupt ........................................................................................................................................55
6.7 PCI Arbiter.........................................................................................................................................55
6.8 EEPROM...........................................................................................................................................56
6.8.1 Overview...............................................................................................................................56
6.8.2 EEPROM Read Status Operation ........................................................................................57
6.8.3 EEPROM Write Enable Operation........................................................................................57
6.8.4 EEPROM Write Operation....................................................................................................58
6.8.5 EEPROM Read Operation....................................................................................................58
6.8.6 Suggested EEPROM Data Content......................................................................................58
6.9 Legacy Mode.....................................................................................................................................59
7. DC Characteristics .......................................................................................................................................61
8. AC Characteristics .......................................................................................................................................63
9. PCI Express Interface Characteristics .........................................................................................................65
10. Package Information ....................................................................................................................................67
11. Ordering Information ....................................................................................................................................69
12. Top Marking Information ..............................................................................................................................71
www.ite.com.tw
ii
IT8892E/IT8893E V0.7
CONFIDENTIAL
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
